atsams70q21/aes/
aes_idr.rs

1#[doc = "Register `AES_IDR` writer"]
2pub struct W(crate::W<AES_IDR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<AES_IDR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<AES_IDR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<AES_IDR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `DATRDY` writer - Data Ready Interrupt Disable"]
23pub struct DATRDY_W<'a> {
24    w: &'a mut W,
25}
26impl<'a> DATRDY_W<'a> {
27    #[doc = r"Sets the field bit"]
28    #[inline(always)]
29    pub fn set_bit(self) -> &'a mut W {
30        self.bit(true)
31    }
32    #[doc = r"Clears the field bit"]
33    #[inline(always)]
34    pub fn clear_bit(self) -> &'a mut W {
35        self.bit(false)
36    }
37    #[doc = r"Writes raw bits to the field"]
38    #[inline(always)]
39    pub fn bit(self, value: bool) -> &'a mut W {
40        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
41        self.w
42    }
43}
44#[doc = "Field `URAD` writer - Unspecified Register Access Detection Interrupt Disable"]
45pub struct URAD_W<'a> {
46    w: &'a mut W,
47}
48impl<'a> URAD_W<'a> {
49    #[doc = r"Sets the field bit"]
50    #[inline(always)]
51    pub fn set_bit(self) -> &'a mut W {
52        self.bit(true)
53    }
54    #[doc = r"Clears the field bit"]
55    #[inline(always)]
56    pub fn clear_bit(self) -> &'a mut W {
57        self.bit(false)
58    }
59    #[doc = r"Writes raw bits to the field"]
60    #[inline(always)]
61    pub fn bit(self, value: bool) -> &'a mut W {
62        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
63        self.w
64    }
65}
66#[doc = "Field `TAGRDY` writer - GCM Tag Ready Interrupt Disable"]
67pub struct TAGRDY_W<'a> {
68    w: &'a mut W,
69}
70impl<'a> TAGRDY_W<'a> {
71    #[doc = r"Sets the field bit"]
72    #[inline(always)]
73    pub fn set_bit(self) -> &'a mut W {
74        self.bit(true)
75    }
76    #[doc = r"Clears the field bit"]
77    #[inline(always)]
78    pub fn clear_bit(self) -> &'a mut W {
79        self.bit(false)
80    }
81    #[doc = r"Writes raw bits to the field"]
82    #[inline(always)]
83    pub fn bit(self, value: bool) -> &'a mut W {
84        self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
85        self.w
86    }
87}
88impl W {
89    #[doc = "Bit 0 - Data Ready Interrupt Disable"]
90    #[inline(always)]
91    pub fn datrdy(&mut self) -> DATRDY_W {
92        DATRDY_W { w: self }
93    }
94    #[doc = "Bit 8 - Unspecified Register Access Detection Interrupt Disable"]
95    #[inline(always)]
96    pub fn urad(&mut self) -> URAD_W {
97        URAD_W { w: self }
98    }
99    #[doc = "Bit 16 - GCM Tag Ready Interrupt Disable"]
100    #[inline(always)]
101    pub fn tagrdy(&mut self) -> TAGRDY_W {
102        TAGRDY_W { w: self }
103    }
104    #[doc = "Writes raw bits to the register."]
105    #[inline(always)]
106    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
107        self.0.bits(bits);
108        self
109    }
110}
111#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aes_idr](index.html) module"]
112pub struct AES_IDR_SPEC;
113impl crate::RegisterSpec for AES_IDR_SPEC {
114    type Ux = u32;
115}
116#[doc = "`write(|w| ..)` method takes [aes_idr::W](W) writer structure"]
117impl crate::Writable for AES_IDR_SPEC {
118    type Writer = W;
119}
120#[doc = "`reset()` method sets AES_IDR to value 0"]
121impl crate::Resettable for AES_IDR_SPEC {
122    #[inline(always)]
123    fn reset_value() -> Self::Ux {
124        0
125    }
126}
atsams70q21/aes/aes_idr.rs

atsams70q21/aes/
aes_idr.rs
