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#[doc = r"Value read from the register"] pub struct R { bits: u32, } #[doc = r"Value to write to the register"] pub struct W { bits: u32, } impl super::USBHS_HSTDMACONTROL { #[doc = r"Modifies the contents of the register"] #[inline(always)] pub fn modify<F>(&self, f: F) where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, { let bits = self.register.get(); self.register.set(f(&R { bits }, &mut W { bits }).bits); } #[doc = r"Reads the contents of the register"] #[inline(always)] pub fn read(&self) -> R { R { bits: self.register.get(), } } #[doc = r"Writes to the register"] #[inline(always)] pub fn write<F>(&self, f: F) where F: FnOnce(&mut W) -> &mut W, { self.register.set( f(&mut W { bits: Self::reset_value(), }) .bits, ); } #[doc = r"Reset value of the register"] #[inline(always)] pub const fn reset_value() -> u32 { 0 } #[doc = r"Writes the reset value to the register"] #[inline(always)] pub fn reset(&self) { self.register.set(Self::reset_value()) } } #[doc = r"Reader of the field"] pub type CHANN_ENB_R = crate::FR<bool, bool>; #[doc = r"Proxy"] pub struct _CHANN_ENBW<'a> { w: &'a mut W, } impl<'a> _CHANN_ENBW<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); self.w } } #[doc = r"Reader of the field"] pub type LDNXT_DSC_R = crate::FR<bool, bool>; #[doc = r"Proxy"] pub struct _LDNXT_DSCW<'a> { w: &'a mut W, } impl<'a> _LDNXT_DSCW<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); self.w } } #[doc = r"Reader of the field"] pub type END_TR_EN_R = crate::FR<bool, bool>; #[doc = r"Proxy"] pub struct _END_TR_ENW<'a> { w: &'a mut W, } impl<'a> _END_TR_ENW<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); self.w } } #[doc = r"Reader of the field"] pub type END_B_EN_R = crate::FR<bool, bool>; #[doc = r"Proxy"] pub struct _END_B_ENW<'a> { w: &'a mut W, } impl<'a> _END_B_ENW<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); self.w } } #[doc = r"Reader of the field"] pub type END_TR_IT_R = crate::FR<bool, bool>; #[doc = r"Proxy"] pub struct _END_TR_ITW<'a> { w: &'a mut W, } impl<'a> _END_TR_ITW<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); self.w } } #[doc = r"Reader of the field"] pub type END_BUFFIT_R = crate::FR<bool, bool>; #[doc = r"Proxy"] pub struct _END_BUFFITW<'a> { w: &'a mut W, } impl<'a> _END_BUFFITW<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); self.w } } #[doc = r"Reader of the field"] pub type DESC_LD_IT_R = crate::FR<bool, bool>; #[doc = r"Proxy"] pub struct _DESC_LD_ITW<'a> { w: &'a mut W, } impl<'a> _DESC_LD_ITW<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); self.w } } #[doc = r"Reader of the field"] pub type BURST_LCK_R = crate::FR<bool, bool>; #[doc = r"Proxy"] pub struct _BURST_LCKW<'a> { w: &'a mut W, } impl<'a> _BURST_LCKW<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); self.w } } #[doc = r"Reader of the field"] pub type BUFF_LENGTH_R = crate::FR<u16, u16>; #[doc = r"Proxy"] pub struct _BUFF_LENGTHW<'a> { w: &'a mut W, } impl<'a> _BUFF_LENGTHW<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u16) -> &'a mut W { self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); self.w } } impl R { #[doc = r"Value of the register as raw bits"] #[inline(always)] pub fn bits(&self) -> u32 { self.bits } #[doc = "Bit 0 - Channel Enable Command"] #[inline(always)] pub fn chann_enb(&self) -> CHANN_ENB_R { CHANN_ENB_R::new((self.bits() & 0x01) != 0) } #[doc = "Bit 1 - Load Next Channel Transfer Descriptor Enable Command"] #[inline(always)] pub fn ldnxt_dsc(&self) -> LDNXT_DSC_R { LDNXT_DSC_R::new(((self.bits() >> 1) & 0x01) != 0) } #[doc = "Bit 2 - End of Transfer Enable Control (OUT transfers only)"] #[inline(always)] pub fn end_tr_en(&self) -> END_TR_EN_R { END_TR_EN_R::new(((self.bits() >> 2) & 0x01) != 0) } #[doc = "Bit 3 - End of Buffer Enable Control"] #[inline(always)] pub fn end_b_en(&self) -> END_B_EN_R { END_B_EN_R::new(((self.bits() >> 3) & 0x01) != 0) } #[doc = "Bit 4 - End of Transfer Interrupt Enable"] #[inline(always)] pub fn end_tr_it(&self) -> END_TR_IT_R { END_TR_IT_R::new(((self.bits() >> 4) & 0x01) != 0) } #[doc = "Bit 5 - End of Buffer Interrupt Enable"] #[inline(always)] pub fn end_buffit(&self) -> END_BUFFIT_R { END_BUFFIT_R::new(((self.bits() >> 5) & 0x01) != 0) } #[doc = "Bit 6 - Descriptor Loaded Interrupt Enable"] #[inline(always)] pub fn desc_ld_it(&self) -> DESC_LD_IT_R { DESC_LD_IT_R::new(((self.bits() >> 6) & 0x01) != 0) } #[doc = "Bit 7 - Burst Lock Enable"] #[inline(always)] pub fn burst_lck(&self) -> BURST_LCK_R { BURST_LCK_R::new(((self.bits() >> 7) & 0x01) != 0) } #[doc = "Bits 16:31 - Buffer Byte Length (Write-only)"] #[inline(always)] pub fn buff_length(&self) -> BUFF_LENGTH_R { BUFF_LENGTH_R::new(((self.bits() >> 16) & 0xffff) as u16) } } impl W { #[doc = r"Writes raw bits to the register"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; self } #[doc = "Bit 0 - Channel Enable Command"] #[inline(always)] pub fn chann_enb(&mut self) -> _CHANN_ENBW { _CHANN_ENBW { w: self } } #[doc = "Bit 1 - Load Next Channel Transfer Descriptor Enable Command"] #[inline(always)] pub fn ldnxt_dsc(&mut self) -> _LDNXT_DSCW { _LDNXT_DSCW { w: self } } #[doc = "Bit 2 - End of Transfer Enable Control (OUT transfers only)"] #[inline(always)] pub fn end_tr_en(&mut self) -> _END_TR_ENW { _END_TR_ENW { w: self } } #[doc = "Bit 3 - End of Buffer Enable Control"] #[inline(always)] pub fn end_b_en(&mut self) -> _END_B_ENW { _END_B_ENW { w: self } } #[doc = "Bit 4 - End of Transfer Interrupt Enable"] #[inline(always)] pub fn end_tr_it(&mut self) -> _END_TR_ITW { _END_TR_ITW { w: self } } #[doc = "Bit 5 - End of Buffer Interrupt Enable"] #[inline(always)] pub fn end_buffit(&mut self) -> _END_BUFFITW { _END_BUFFITW { w: self } } #[doc = "Bit 6 - Descriptor Loaded Interrupt Enable"] #[inline(always)] pub fn desc_ld_it(&mut self) -> _DESC_LD_ITW { _DESC_LD_ITW { w: self } } #[doc = "Bit 7 - Burst Lock Enable"] #[inline(always)] pub fn burst_lck(&mut self) -> _BURST_LCKW { _BURST_LCKW { w: self } } #[doc = "Bits 16:31 - Buffer Byte Length (Write-only)"] #[inline(always)] pub fn buff_length(&mut self) -> _BUFF_LENGTHW { _BUFF_LENGTHW { w: self } } }