atsams70n21/usbhs/usbhs_devdma/
usbhs_devdmacontrol.rs

1#[doc = "Register `USBHS_DEVDMACONTROL` reader"]
2pub struct R(crate::R<USBHS_DEVDMACONTROL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<USBHS_DEVDMACONTROL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<USBHS_DEVDMACONTROL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<USBHS_DEVDMACONTROL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `USBHS_DEVDMACONTROL` writer"]
17pub struct W(crate::W<USBHS_DEVDMACONTROL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<USBHS_DEVDMACONTROL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<USBHS_DEVDMACONTROL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<USBHS_DEVDMACONTROL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CHANN_ENB` reader - Channel Enable Command"]
38pub struct CHANN_ENB_R(crate::FieldReader<bool, bool>);
39impl CHANN_ENB_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: bool) -> Self {
42        CHANN_ENB_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for CHANN_ENB_R {
46    type Target = crate::FieldReader<bool, bool>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `CHANN_ENB` writer - Channel Enable Command"]
53pub struct CHANN_ENB_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> CHANN_ENB_W<'a> {
57    #[doc = r"Sets the field bit"]
58    #[inline(always)]
59    pub fn set_bit(self) -> &'a mut W {
60        self.bit(true)
61    }
62    #[doc = r"Clears the field bit"]
63    #[inline(always)]
64    pub fn clear_bit(self) -> &'a mut W {
65        self.bit(false)
66    }
67    #[doc = r"Writes raw bits to the field"]
68    #[inline(always)]
69    pub fn bit(self, value: bool) -> &'a mut W {
70        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
71        self.w
72    }
73}
74#[doc = "Field `LDNXT_DSC` reader - Load Next Channel Transfer Descriptor Enable Command"]
75pub struct LDNXT_DSC_R(crate::FieldReader<bool, bool>);
76impl LDNXT_DSC_R {
77    #[inline(always)]
78    pub(crate) fn new(bits: bool) -> Self {
79        LDNXT_DSC_R(crate::FieldReader::new(bits))
80    }
81}
82impl core::ops::Deref for LDNXT_DSC_R {
83    type Target = crate::FieldReader<bool, bool>;
84    #[inline(always)]
85    fn deref(&self) -> &Self::Target {
86        &self.0
87    }
88}
89#[doc = "Field `LDNXT_DSC` writer - Load Next Channel Transfer Descriptor Enable Command"]
90pub struct LDNXT_DSC_W<'a> {
91    w: &'a mut W,
92}
93impl<'a> LDNXT_DSC_W<'a> {
94    #[doc = r"Sets the field bit"]
95    #[inline(always)]
96    pub fn set_bit(self) -> &'a mut W {
97        self.bit(true)
98    }
99    #[doc = r"Clears the field bit"]
100    #[inline(always)]
101    pub fn clear_bit(self) -> &'a mut W {
102        self.bit(false)
103    }
104    #[doc = r"Writes raw bits to the field"]
105    #[inline(always)]
106    pub fn bit(self, value: bool) -> &'a mut W {
107        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
108        self.w
109    }
110}
111#[doc = "Field `END_TR_EN` reader - End of Transfer Enable Control (OUT transfers only)"]
112pub struct END_TR_EN_R(crate::FieldReader<bool, bool>);
113impl END_TR_EN_R {
114    #[inline(always)]
115    pub(crate) fn new(bits: bool) -> Self {
116        END_TR_EN_R(crate::FieldReader::new(bits))
117    }
118}
119impl core::ops::Deref for END_TR_EN_R {
120    type Target = crate::FieldReader<bool, bool>;
121    #[inline(always)]
122    fn deref(&self) -> &Self::Target {
123        &self.0
124    }
125}
126#[doc = "Field `END_TR_EN` writer - End of Transfer Enable Control (OUT transfers only)"]
127pub struct END_TR_EN_W<'a> {
128    w: &'a mut W,
129}
130impl<'a> END_TR_EN_W<'a> {
131    #[doc = r"Sets the field bit"]
132    #[inline(always)]
133    pub fn set_bit(self) -> &'a mut W {
134        self.bit(true)
135    }
136    #[doc = r"Clears the field bit"]
137    #[inline(always)]
138    pub fn clear_bit(self) -> &'a mut W {
139        self.bit(false)
140    }
141    #[doc = r"Writes raw bits to the field"]
142    #[inline(always)]
143    pub fn bit(self, value: bool) -> &'a mut W {
144        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
145        self.w
146    }
147}
148#[doc = "Field `END_B_EN` reader - End of Buffer Enable Control"]
149pub struct END_B_EN_R(crate::FieldReader<bool, bool>);
150impl END_B_EN_R {
151    #[inline(always)]
152    pub(crate) fn new(bits: bool) -> Self {
153        END_B_EN_R(crate::FieldReader::new(bits))
154    }
155}
156impl core::ops::Deref for END_B_EN_R {
157    type Target = crate::FieldReader<bool, bool>;
158    #[inline(always)]
159    fn deref(&self) -> &Self::Target {
160        &self.0
161    }
162}
163#[doc = "Field `END_B_EN` writer - End of Buffer Enable Control"]
164pub struct END_B_EN_W<'a> {
165    w: &'a mut W,
166}
167impl<'a> END_B_EN_W<'a> {
168    #[doc = r"Sets the field bit"]
169    #[inline(always)]
170    pub fn set_bit(self) -> &'a mut W {
171        self.bit(true)
172    }
173    #[doc = r"Clears the field bit"]
174    #[inline(always)]
175    pub fn clear_bit(self) -> &'a mut W {
176        self.bit(false)
177    }
178    #[doc = r"Writes raw bits to the field"]
179    #[inline(always)]
180    pub fn bit(self, value: bool) -> &'a mut W {
181        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
182        self.w
183    }
184}
185#[doc = "Field `END_TR_IT` reader - End of Transfer Interrupt Enable"]
186pub struct END_TR_IT_R(crate::FieldReader<bool, bool>);
187impl END_TR_IT_R {
188    #[inline(always)]
189    pub(crate) fn new(bits: bool) -> Self {
190        END_TR_IT_R(crate::FieldReader::new(bits))
191    }
192}
193impl core::ops::Deref for END_TR_IT_R {
194    type Target = crate::FieldReader<bool, bool>;
195    #[inline(always)]
196    fn deref(&self) -> &Self::Target {
197        &self.0
198    }
199}
200#[doc = "Field `END_TR_IT` writer - End of Transfer Interrupt Enable"]
201pub struct END_TR_IT_W<'a> {
202    w: &'a mut W,
203}
204impl<'a> END_TR_IT_W<'a> {
205    #[doc = r"Sets the field bit"]
206    #[inline(always)]
207    pub fn set_bit(self) -> &'a mut W {
208        self.bit(true)
209    }
210    #[doc = r"Clears the field bit"]
211    #[inline(always)]
212    pub fn clear_bit(self) -> &'a mut W {
213        self.bit(false)
214    }
215    #[doc = r"Writes raw bits to the field"]
216    #[inline(always)]
217    pub fn bit(self, value: bool) -> &'a mut W {
218        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
219        self.w
220    }
221}
222#[doc = "Field `END_BUFFIT` reader - End of Buffer Interrupt Enable"]
223pub struct END_BUFFIT_R(crate::FieldReader<bool, bool>);
224impl END_BUFFIT_R {
225    #[inline(always)]
226    pub(crate) fn new(bits: bool) -> Self {
227        END_BUFFIT_R(crate::FieldReader::new(bits))
228    }
229}
230impl core::ops::Deref for END_BUFFIT_R {
231    type Target = crate::FieldReader<bool, bool>;
232    #[inline(always)]
233    fn deref(&self) -> &Self::Target {
234        &self.0
235    }
236}
237#[doc = "Field `END_BUFFIT` writer - End of Buffer Interrupt Enable"]
238pub struct END_BUFFIT_W<'a> {
239    w: &'a mut W,
240}
241impl<'a> END_BUFFIT_W<'a> {
242    #[doc = r"Sets the field bit"]
243    #[inline(always)]
244    pub fn set_bit(self) -> &'a mut W {
245        self.bit(true)
246    }
247    #[doc = r"Clears the field bit"]
248    #[inline(always)]
249    pub fn clear_bit(self) -> &'a mut W {
250        self.bit(false)
251    }
252    #[doc = r"Writes raw bits to the field"]
253    #[inline(always)]
254    pub fn bit(self, value: bool) -> &'a mut W {
255        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
256        self.w
257    }
258}
259#[doc = "Field `DESC_LD_IT` reader - Descriptor Loaded Interrupt Enable"]
260pub struct DESC_LD_IT_R(crate::FieldReader<bool, bool>);
261impl DESC_LD_IT_R {
262    #[inline(always)]
263    pub(crate) fn new(bits: bool) -> Self {
264        DESC_LD_IT_R(crate::FieldReader::new(bits))
265    }
266}
267impl core::ops::Deref for DESC_LD_IT_R {
268    type Target = crate::FieldReader<bool, bool>;
269    #[inline(always)]
270    fn deref(&self) -> &Self::Target {
271        &self.0
272    }
273}
274#[doc = "Field `DESC_LD_IT` writer - Descriptor Loaded Interrupt Enable"]
275pub struct DESC_LD_IT_W<'a> {
276    w: &'a mut W,
277}
278impl<'a> DESC_LD_IT_W<'a> {
279    #[doc = r"Sets the field bit"]
280    #[inline(always)]
281    pub fn set_bit(self) -> &'a mut W {
282        self.bit(true)
283    }
284    #[doc = r"Clears the field bit"]
285    #[inline(always)]
286    pub fn clear_bit(self) -> &'a mut W {
287        self.bit(false)
288    }
289    #[doc = r"Writes raw bits to the field"]
290    #[inline(always)]
291    pub fn bit(self, value: bool) -> &'a mut W {
292        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
293        self.w
294    }
295}
296#[doc = "Field `BURST_LCK` reader - Burst Lock Enable"]
297pub struct BURST_LCK_R(crate::FieldReader<bool, bool>);
298impl BURST_LCK_R {
299    #[inline(always)]
300    pub(crate) fn new(bits: bool) -> Self {
301        BURST_LCK_R(crate::FieldReader::new(bits))
302    }
303}
304impl core::ops::Deref for BURST_LCK_R {
305    type Target = crate::FieldReader<bool, bool>;
306    #[inline(always)]
307    fn deref(&self) -> &Self::Target {
308        &self.0
309    }
310}
311#[doc = "Field `BURST_LCK` writer - Burst Lock Enable"]
312pub struct BURST_LCK_W<'a> {
313    w: &'a mut W,
314}
315impl<'a> BURST_LCK_W<'a> {
316    #[doc = r"Sets the field bit"]
317    #[inline(always)]
318    pub fn set_bit(self) -> &'a mut W {
319        self.bit(true)
320    }
321    #[doc = r"Clears the field bit"]
322    #[inline(always)]
323    pub fn clear_bit(self) -> &'a mut W {
324        self.bit(false)
325    }
326    #[doc = r"Writes raw bits to the field"]
327    #[inline(always)]
328    pub fn bit(self, value: bool) -> &'a mut W {
329        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
330        self.w
331    }
332}
333#[doc = "Field `BUFF_LENGTH` reader - Buffer Byte Length (Write-only)"]
334pub struct BUFF_LENGTH_R(crate::FieldReader<u16, u16>);
335impl BUFF_LENGTH_R {
336    #[inline(always)]
337    pub(crate) fn new(bits: u16) -> Self {
338        BUFF_LENGTH_R(crate::FieldReader::new(bits))
339    }
340}
341impl core::ops::Deref for BUFF_LENGTH_R {
342    type Target = crate::FieldReader<u16, u16>;
343    #[inline(always)]
344    fn deref(&self) -> &Self::Target {
345        &self.0
346    }
347}
348#[doc = "Field `BUFF_LENGTH` writer - Buffer Byte Length (Write-only)"]
349pub struct BUFF_LENGTH_W<'a> {
350    w: &'a mut W,
351}
352impl<'a> BUFF_LENGTH_W<'a> {
353    #[doc = r"Writes raw bits to the field"]
354    #[inline(always)]
355    pub unsafe fn bits(self, value: u16) -> &'a mut W {
356        self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16);
357        self.w
358    }
359}
360impl R {
361    #[doc = "Bit 0 - Channel Enable Command"]
362    #[inline(always)]
363    pub fn chann_enb(&self) -> CHANN_ENB_R {
364        CHANN_ENB_R::new((self.bits & 0x01) != 0)
365    }
366    #[doc = "Bit 1 - Load Next Channel Transfer Descriptor Enable Command"]
367    #[inline(always)]
368    pub fn ldnxt_dsc(&self) -> LDNXT_DSC_R {
369        LDNXT_DSC_R::new(((self.bits >> 1) & 0x01) != 0)
370    }
371    #[doc = "Bit 2 - End of Transfer Enable Control (OUT transfers only)"]
372    #[inline(always)]
373    pub fn end_tr_en(&self) -> END_TR_EN_R {
374        END_TR_EN_R::new(((self.bits >> 2) & 0x01) != 0)
375    }
376    #[doc = "Bit 3 - End of Buffer Enable Control"]
377    #[inline(always)]
378    pub fn end_b_en(&self) -> END_B_EN_R {
379        END_B_EN_R::new(((self.bits >> 3) & 0x01) != 0)
380    }
381    #[doc = "Bit 4 - End of Transfer Interrupt Enable"]
382    #[inline(always)]
383    pub fn end_tr_it(&self) -> END_TR_IT_R {
384        END_TR_IT_R::new(((self.bits >> 4) & 0x01) != 0)
385    }
386    #[doc = "Bit 5 - End of Buffer Interrupt Enable"]
387    #[inline(always)]
388    pub fn end_buffit(&self) -> END_BUFFIT_R {
389        END_BUFFIT_R::new(((self.bits >> 5) & 0x01) != 0)
390    }
391    #[doc = "Bit 6 - Descriptor Loaded Interrupt Enable"]
392    #[inline(always)]
393    pub fn desc_ld_it(&self) -> DESC_LD_IT_R {
394        DESC_LD_IT_R::new(((self.bits >> 6) & 0x01) != 0)
395    }
396    #[doc = "Bit 7 - Burst Lock Enable"]
397    #[inline(always)]
398    pub fn burst_lck(&self) -> BURST_LCK_R {
399        BURST_LCK_R::new(((self.bits >> 7) & 0x01) != 0)
400    }
401    #[doc = "Bits 16:31 - Buffer Byte Length (Write-only)"]
402    #[inline(always)]
403    pub fn buff_length(&self) -> BUFF_LENGTH_R {
404        BUFF_LENGTH_R::new(((self.bits >> 16) & 0xffff) as u16)
405    }
406}
407impl W {
408    #[doc = "Bit 0 - Channel Enable Command"]
409    #[inline(always)]
410    pub fn chann_enb(&mut self) -> CHANN_ENB_W {
411        CHANN_ENB_W { w: self }
412    }
413    #[doc = "Bit 1 - Load Next Channel Transfer Descriptor Enable Command"]
414    #[inline(always)]
415    pub fn ldnxt_dsc(&mut self) -> LDNXT_DSC_W {
416        LDNXT_DSC_W { w: self }
417    }
418    #[doc = "Bit 2 - End of Transfer Enable Control (OUT transfers only)"]
419    #[inline(always)]
420    pub fn end_tr_en(&mut self) -> END_TR_EN_W {
421        END_TR_EN_W { w: self }
422    }
423    #[doc = "Bit 3 - End of Buffer Enable Control"]
424    #[inline(always)]
425    pub fn end_b_en(&mut self) -> END_B_EN_W {
426        END_B_EN_W { w: self }
427    }
428    #[doc = "Bit 4 - End of Transfer Interrupt Enable"]
429    #[inline(always)]
430    pub fn end_tr_it(&mut self) -> END_TR_IT_W {
431        END_TR_IT_W { w: self }
432    }
433    #[doc = "Bit 5 - End of Buffer Interrupt Enable"]
434    #[inline(always)]
435    pub fn end_buffit(&mut self) -> END_BUFFIT_W {
436        END_BUFFIT_W { w: self }
437    }
438    #[doc = "Bit 6 - Descriptor Loaded Interrupt Enable"]
439    #[inline(always)]
440    pub fn desc_ld_it(&mut self) -> DESC_LD_IT_W {
441        DESC_LD_IT_W { w: self }
442    }
443    #[doc = "Bit 7 - Burst Lock Enable"]
444    #[inline(always)]
445    pub fn burst_lck(&mut self) -> BURST_LCK_W {
446        BURST_LCK_W { w: self }
447    }
448    #[doc = "Bits 16:31 - Buffer Byte Length (Write-only)"]
449    #[inline(always)]
450    pub fn buff_length(&mut self) -> BUFF_LENGTH_W {
451        BUFF_LENGTH_W { w: self }
452    }
453    #[doc = "Writes raw bits to the register."]
454    #[inline(always)]
455    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
456        self.0.bits(bits);
457        self
458    }
459}
460#[doc = "Device DMA Channel Control Register (n = 1)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usbhs_devdmacontrol](index.html) module"]
461pub struct USBHS_DEVDMACONTROL_SPEC;
462impl crate::RegisterSpec for USBHS_DEVDMACONTROL_SPEC {
463    type Ux = u32;
464}
465#[doc = "`read()` method returns [usbhs_devdmacontrol::R](R) reader structure"]
466impl crate::Readable for USBHS_DEVDMACONTROL_SPEC {
467    type Reader = R;
468}
469#[doc = "`write(|w| ..)` method takes [usbhs_devdmacontrol::W](W) writer structure"]
470impl crate::Writable for USBHS_DEVDMACONTROL_SPEC {
471    type Writer = W;
472}
473#[doc = "`reset()` method sets USBHS_DEVDMACONTROL to value 0"]
474impl crate::Resettable for USBHS_DEVDMACONTROL_SPEC {
475    #[inline(always)]
476    fn reset_value() -> Self::Ux {
477        0
478    }
479}
atsams70n21/usbhs/usbhs_devdma/usbhs_devdmacontrol.rs

atsams70n21/usbhs/usbhs_devdma/
usbhs_devdmacontrol.rs
