atsams70n21/pioa/
pio_pcimr.rs

1#[doc = "Register `PIO_PCIMR` reader"]
2pub struct R(crate::R<PIO_PCIMR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PIO_PCIMR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PIO_PCIMR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PIO_PCIMR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `DRDY` reader - Parallel Capture Mode Data Ready Interrupt Mask"]
17pub struct DRDY_R(crate::FieldReader<bool, bool>);
18impl DRDY_R {
19    #[inline(always)]
20    pub(crate) fn new(bits: bool) -> Self {
21        DRDY_R(crate::FieldReader::new(bits))
22    }
23}
24impl core::ops::Deref for DRDY_R {
25    type Target = crate::FieldReader<bool, bool>;
26    #[inline(always)]
27    fn deref(&self) -> &Self::Target {
28        &self.0
29    }
30}
31#[doc = "Field `OVRE` reader - Parallel Capture Mode Overrun Error Interrupt Mask"]
32pub struct OVRE_R(crate::FieldReader<bool, bool>);
33impl OVRE_R {
34    #[inline(always)]
35    pub(crate) fn new(bits: bool) -> Self {
36        OVRE_R(crate::FieldReader::new(bits))
37    }
38}
39impl core::ops::Deref for OVRE_R {
40    type Target = crate::FieldReader<bool, bool>;
41    #[inline(always)]
42    fn deref(&self) -> &Self::Target {
43        &self.0
44    }
45}
46#[doc = "Field `ENDRX` reader - End of Reception Transfer Interrupt Mask"]
47pub struct ENDRX_R(crate::FieldReader<bool, bool>);
48impl ENDRX_R {
49    #[inline(always)]
50    pub(crate) fn new(bits: bool) -> Self {
51        ENDRX_R(crate::FieldReader::new(bits))
52    }
53}
54impl core::ops::Deref for ENDRX_R {
55    type Target = crate::FieldReader<bool, bool>;
56    #[inline(always)]
57    fn deref(&self) -> &Self::Target {
58        &self.0
59    }
60}
61#[doc = "Field `RXBUFF` reader - Reception Buffer Full Interrupt Mask"]
62pub struct RXBUFF_R(crate::FieldReader<bool, bool>);
63impl RXBUFF_R {
64    #[inline(always)]
65    pub(crate) fn new(bits: bool) -> Self {
66        RXBUFF_R(crate::FieldReader::new(bits))
67    }
68}
69impl core::ops::Deref for RXBUFF_R {
70    type Target = crate::FieldReader<bool, bool>;
71    #[inline(always)]
72    fn deref(&self) -> &Self::Target {
73        &self.0
74    }
75}
76impl R {
77    #[doc = "Bit 0 - Parallel Capture Mode Data Ready Interrupt Mask"]
78    #[inline(always)]
79    pub fn drdy(&self) -> DRDY_R {
80        DRDY_R::new((self.bits & 0x01) != 0)
81    }
82    #[doc = "Bit 1 - Parallel Capture Mode Overrun Error Interrupt Mask"]
83    #[inline(always)]
84    pub fn ovre(&self) -> OVRE_R {
85        OVRE_R::new(((self.bits >> 1) & 0x01) != 0)
86    }
87    #[doc = "Bit 2 - End of Reception Transfer Interrupt Mask"]
88    #[inline(always)]
89    pub fn endrx(&self) -> ENDRX_R {
90        ENDRX_R::new(((self.bits >> 2) & 0x01) != 0)
91    }
92    #[doc = "Bit 3 - Reception Buffer Full Interrupt Mask"]
93    #[inline(always)]
94    pub fn rxbuff(&self) -> RXBUFF_R {
95        RXBUFF_R::new(((self.bits >> 3) & 0x01) != 0)
96    }
97}
98#[doc = "Parallel Capture Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pio_pcimr](index.html) module"]
99pub struct PIO_PCIMR_SPEC;
100impl crate::RegisterSpec for PIO_PCIMR_SPEC {
101    type Ux = u32;
102}
103#[doc = "`read()` method returns [pio_pcimr::R](R) reader structure"]
104impl crate::Readable for PIO_PCIMR_SPEC {
105    type Reader = R;
106}
107#[doc = "`reset()` method sets PIO_PCIMR to value 0"]
108impl crate::Resettable for PIO_PCIMR_SPEC {
109    #[inline(always)]
110    fn reset_value() -> Self::Ux {
111        0
112    }
113}
atsams70n21/pioa/pio_pcimr.rs

atsams70n21/pioa/
pio_pcimr.rs
