atsams70j21/xdmac/xdmac_chid/
xdmac_cis.rs

1#[doc = "Register `XDMAC_CIS` reader"]
2pub struct R(crate::R<XDMAC_CIS_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<XDMAC_CIS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<XDMAC_CIS_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<XDMAC_CIS_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `BIS` reader - End of Block Interrupt Status Bit"]
17pub struct BIS_R(crate::FieldReader<bool, bool>);
18impl BIS_R {
19    #[inline(always)]
20    pub(crate) fn new(bits: bool) -> Self {
21        BIS_R(crate::FieldReader::new(bits))
22    }
23}
24impl core::ops::Deref for BIS_R {
25    type Target = crate::FieldReader<bool, bool>;
26    #[inline(always)]
27    fn deref(&self) -> &Self::Target {
28        &self.0
29    }
30}
31#[doc = "Field `LIS` reader - End of Linked List Interrupt Status Bit"]
32pub struct LIS_R(crate::FieldReader<bool, bool>);
33impl LIS_R {
34    #[inline(always)]
35    pub(crate) fn new(bits: bool) -> Self {
36        LIS_R(crate::FieldReader::new(bits))
37    }
38}
39impl core::ops::Deref for LIS_R {
40    type Target = crate::FieldReader<bool, bool>;
41    #[inline(always)]
42    fn deref(&self) -> &Self::Target {
43        &self.0
44    }
45}
46#[doc = "Field `DIS` reader - End of Disable Interrupt Status Bit"]
47pub struct DIS_R(crate::FieldReader<bool, bool>);
48impl DIS_R {
49    #[inline(always)]
50    pub(crate) fn new(bits: bool) -> Self {
51        DIS_R(crate::FieldReader::new(bits))
52    }
53}
54impl core::ops::Deref for DIS_R {
55    type Target = crate::FieldReader<bool, bool>;
56    #[inline(always)]
57    fn deref(&self) -> &Self::Target {
58        &self.0
59    }
60}
61#[doc = "Field `FIS` reader - End of Flush Interrupt Status Bit"]
62pub struct FIS_R(crate::FieldReader<bool, bool>);
63impl FIS_R {
64    #[inline(always)]
65    pub(crate) fn new(bits: bool) -> Self {
66        FIS_R(crate::FieldReader::new(bits))
67    }
68}
69impl core::ops::Deref for FIS_R {
70    type Target = crate::FieldReader<bool, bool>;
71    #[inline(always)]
72    fn deref(&self) -> &Self::Target {
73        &self.0
74    }
75}
76#[doc = "Field `RBEIS` reader - Read Bus Error Interrupt Status Bit"]
77pub struct RBEIS_R(crate::FieldReader<bool, bool>);
78impl RBEIS_R {
79    #[inline(always)]
80    pub(crate) fn new(bits: bool) -> Self {
81        RBEIS_R(crate::FieldReader::new(bits))
82    }
83}
84impl core::ops::Deref for RBEIS_R {
85    type Target = crate::FieldReader<bool, bool>;
86    #[inline(always)]
87    fn deref(&self) -> &Self::Target {
88        &self.0
89    }
90}
91#[doc = "Field `WBEIS` reader - Write Bus Error Interrupt Status Bit"]
92pub struct WBEIS_R(crate::FieldReader<bool, bool>);
93impl WBEIS_R {
94    #[inline(always)]
95    pub(crate) fn new(bits: bool) -> Self {
96        WBEIS_R(crate::FieldReader::new(bits))
97    }
98}
99impl core::ops::Deref for WBEIS_R {
100    type Target = crate::FieldReader<bool, bool>;
101    #[inline(always)]
102    fn deref(&self) -> &Self::Target {
103        &self.0
104    }
105}
106#[doc = "Field `ROIS` reader - Request Overflow Error Interrupt Status Bit"]
107pub struct ROIS_R(crate::FieldReader<bool, bool>);
108impl ROIS_R {
109    #[inline(always)]
110    pub(crate) fn new(bits: bool) -> Self {
111        ROIS_R(crate::FieldReader::new(bits))
112    }
113}
114impl core::ops::Deref for ROIS_R {
115    type Target = crate::FieldReader<bool, bool>;
116    #[inline(always)]
117    fn deref(&self) -> &Self::Target {
118        &self.0
119    }
120}
121impl R {
122    #[doc = "Bit 0 - End of Block Interrupt Status Bit"]
123    #[inline(always)]
124    pub fn bis(&self) -> BIS_R {
125        BIS_R::new((self.bits & 0x01) != 0)
126    }
127    #[doc = "Bit 1 - End of Linked List Interrupt Status Bit"]
128    #[inline(always)]
129    pub fn lis(&self) -> LIS_R {
130        LIS_R::new(((self.bits >> 1) & 0x01) != 0)
131    }
132    #[doc = "Bit 2 - End of Disable Interrupt Status Bit"]
133    #[inline(always)]
134    pub fn dis(&self) -> DIS_R {
135        DIS_R::new(((self.bits >> 2) & 0x01) != 0)
136    }
137    #[doc = "Bit 3 - End of Flush Interrupt Status Bit"]
138    #[inline(always)]
139    pub fn fis(&self) -> FIS_R {
140        FIS_R::new(((self.bits >> 3) & 0x01) != 0)
141    }
142    #[doc = "Bit 4 - Read Bus Error Interrupt Status Bit"]
143    #[inline(always)]
144    pub fn rbeis(&self) -> RBEIS_R {
145        RBEIS_R::new(((self.bits >> 4) & 0x01) != 0)
146    }
147    #[doc = "Bit 5 - Write Bus Error Interrupt Status Bit"]
148    #[inline(always)]
149    pub fn wbeis(&self) -> WBEIS_R {
150        WBEIS_R::new(((self.bits >> 5) & 0x01) != 0)
151    }
152    #[doc = "Bit 6 - Request Overflow Error Interrupt Status Bit"]
153    #[inline(always)]
154    pub fn rois(&self) -> ROIS_R {
155        ROIS_R::new(((self.bits >> 6) & 0x01) != 0)
156    }
157}
158#[doc = "Channel Interrupt Status Register (chid = 0)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xdmac_cis](index.html) module"]
159pub struct XDMAC_CIS_SPEC;
160impl crate::RegisterSpec for XDMAC_CIS_SPEC {
161    type Ux = u32;
162}
163#[doc = "`read()` method returns [xdmac_cis::R](R) reader structure"]
164impl crate::Readable for XDMAC_CIS_SPEC {
165    type Reader = R;
166}
167#[doc = "`reset()` method sets XDMAC_CIS to value 0"]
168impl crate::Resettable for XDMAC_CIS_SPEC {
169    #[inline(always)]
170    fn reset_value() -> Self::Ux {
171        0
172    }
173}
atsams70j21/xdmac/xdmac_chid/xdmac_cis.rs

atsams70j21/xdmac/xdmac_chid/
xdmac_cis.rs
