atsams70j21/pmc/
ckgr_pllar.rs1#[doc = "Register `CKGR_PLLAR` reader"]
2pub struct R(crate::R<CKGR_PLLAR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CKGR_PLLAR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CKGR_PLLAR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CKGR_PLLAR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CKGR_PLLAR` writer"]
17pub struct W(crate::W<CKGR_PLLAR_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CKGR_PLLAR_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CKGR_PLLAR_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CKGR_PLLAR_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "PLLA Front End Divider\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum DIVA_A {
41 #[doc = "0: Divider output is 0 and PLLA is disabled."]
42 _0 = 0,
43 #[doc = "1: Divider is bypassed (divide by 1) and PLLA is enabled."]
44 BYPASS = 1,
45}
46impl From<DIVA_A> for u8 {
47 #[inline(always)]
48 fn from(variant: DIVA_A) -> Self {
49 variant as _
50 }
51}
52#[doc = "Field `DIVA` reader - PLLA Front End Divider"]
53pub struct DIVA_R(crate::FieldReader<u8, DIVA_A>);
54impl DIVA_R {
55 #[inline(always)]
56 pub(crate) fn new(bits: u8) -> Self {
57 DIVA_R(crate::FieldReader::new(bits))
58 }
59 #[doc = r"Get enumerated values variant"]
60 #[inline(always)]
61 pub fn variant(&self) -> Option<DIVA_A> {
62 match self.bits {
63 0 => Some(DIVA_A::_0),
64 1 => Some(DIVA_A::BYPASS),
65 _ => None,
66 }
67 }
68 #[doc = "Checks if the value of the field is `_0`"]
69 #[inline(always)]
70 pub fn is_0(&self) -> bool {
71 **self == DIVA_A::_0
72 }
73 #[doc = "Checks if the value of the field is `BYPASS`"]
74 #[inline(always)]
75 pub fn is_bypass(&self) -> bool {
76 **self == DIVA_A::BYPASS
77 }
78}
79impl core::ops::Deref for DIVA_R {
80 type Target = crate::FieldReader<u8, DIVA_A>;
81 #[inline(always)]
82 fn deref(&self) -> &Self::Target {
83 &self.0
84 }
85}
86#[doc = "Field `DIVA` writer - PLLA Front End Divider"]
87pub struct DIVA_W<'a> {
88 w: &'a mut W,
89}
90impl<'a> DIVA_W<'a> {
91 #[doc = r"Writes `variant` to the field"]
92 #[inline(always)]
93 pub fn variant(self, variant: DIVA_A) -> &'a mut W {
94 unsafe { self.bits(variant.into()) }
95 }
96 #[doc = "Divider output is 0 and PLLA is disabled."]
97 #[inline(always)]
98 pub fn _0(self) -> &'a mut W {
99 self.variant(DIVA_A::_0)
100 }
101 #[doc = "Divider is bypassed (divide by 1) and PLLA is enabled."]
102 #[inline(always)]
103 pub fn bypass(self) -> &'a mut W {
104 self.variant(DIVA_A::BYPASS)
105 }
106 #[doc = r"Writes raw bits to the field"]
107 #[inline(always)]
108 pub unsafe fn bits(self, value: u8) -> &'a mut W {
109 self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
110 self.w
111 }
112}
113#[doc = "Field `PLLACOUNT` reader - PLLA Counter"]
114pub struct PLLACOUNT_R(crate::FieldReader<u8, u8>);
115impl PLLACOUNT_R {
116 #[inline(always)]
117 pub(crate) fn new(bits: u8) -> Self {
118 PLLACOUNT_R(crate::FieldReader::new(bits))
119 }
120}
121impl core::ops::Deref for PLLACOUNT_R {
122 type Target = crate::FieldReader<u8, u8>;
123 #[inline(always)]
124 fn deref(&self) -> &Self::Target {
125 &self.0
126 }
127}
128#[doc = "Field `PLLACOUNT` writer - PLLA Counter"]
129pub struct PLLACOUNT_W<'a> {
130 w: &'a mut W,
131}
132impl<'a> PLLACOUNT_W<'a> {
133 #[doc = r"Writes raw bits to the field"]
134 #[inline(always)]
135 pub unsafe fn bits(self, value: u8) -> &'a mut W {
136 self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8);
137 self.w
138 }
139}
140#[doc = "Field `MULA` reader - PLLA Multiplier"]
141pub struct MULA_R(crate::FieldReader<u16, u16>);
142impl MULA_R {
143 #[inline(always)]
144 pub(crate) fn new(bits: u16) -> Self {
145 MULA_R(crate::FieldReader::new(bits))
146 }
147}
148impl core::ops::Deref for MULA_R {
149 type Target = crate::FieldReader<u16, u16>;
150 #[inline(always)]
151 fn deref(&self) -> &Self::Target {
152 &self.0
153 }
154}
155#[doc = "Field `MULA` writer - PLLA Multiplier"]
156pub struct MULA_W<'a> {
157 w: &'a mut W,
158}
159impl<'a> MULA_W<'a> {
160 #[doc = r"Writes raw bits to the field"]
161 #[inline(always)]
162 pub unsafe fn bits(self, value: u16) -> &'a mut W {
163 self.w.bits = (self.w.bits & !(0x07ff << 16)) | ((value as u32 & 0x07ff) << 16);
164 self.w
165 }
166}
167#[doc = "Field `ONE` reader - Must Be Set to 1"]
168pub struct ONE_R(crate::FieldReader<bool, bool>);
169impl ONE_R {
170 #[inline(always)]
171 pub(crate) fn new(bits: bool) -> Self {
172 ONE_R(crate::FieldReader::new(bits))
173 }
174}
175impl core::ops::Deref for ONE_R {
176 type Target = crate::FieldReader<bool, bool>;
177 #[inline(always)]
178 fn deref(&self) -> &Self::Target {
179 &self.0
180 }
181}
182#[doc = "Field `ONE` writer - Must Be Set to 1"]
183pub struct ONE_W<'a> {
184 w: &'a mut W,
185}
186impl<'a> ONE_W<'a> {
187 #[doc = r"Sets the field bit"]
188 #[inline(always)]
189 pub fn set_bit(self) -> &'a mut W {
190 self.bit(true)
191 }
192 #[doc = r"Clears the field bit"]
193 #[inline(always)]
194 pub fn clear_bit(self) -> &'a mut W {
195 self.bit(false)
196 }
197 #[doc = r"Writes raw bits to the field"]
198 #[inline(always)]
199 pub fn bit(self, value: bool) -> &'a mut W {
200 self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29);
201 self.w
202 }
203}
204impl R {
205 #[doc = "Bits 0:7 - PLLA Front End Divider"]
206 #[inline(always)]
207 pub fn diva(&self) -> DIVA_R {
208 DIVA_R::new((self.bits & 0xff) as u8)
209 }
210 #[doc = "Bits 8:13 - PLLA Counter"]
211 #[inline(always)]
212 pub fn pllacount(&self) -> PLLACOUNT_R {
213 PLLACOUNT_R::new(((self.bits >> 8) & 0x3f) as u8)
214 }
215 #[doc = "Bits 16:26 - PLLA Multiplier"]
216 #[inline(always)]
217 pub fn mula(&self) -> MULA_R {
218 MULA_R::new(((self.bits >> 16) & 0x07ff) as u16)
219 }
220 #[doc = "Bit 29 - Must Be Set to 1"]
221 #[inline(always)]
222 pub fn one(&self) -> ONE_R {
223 ONE_R::new(((self.bits >> 29) & 0x01) != 0)
224 }
225}
226impl W {
227 #[doc = "Bits 0:7 - PLLA Front End Divider"]
228 #[inline(always)]
229 pub fn diva(&mut self) -> DIVA_W {
230 DIVA_W { w: self }
231 }
232 #[doc = "Bits 8:13 - PLLA Counter"]
233 #[inline(always)]
234 pub fn pllacount(&mut self) -> PLLACOUNT_W {
235 PLLACOUNT_W { w: self }
236 }
237 #[doc = "Bits 16:26 - PLLA Multiplier"]
238 #[inline(always)]
239 pub fn mula(&mut self) -> MULA_W {
240 MULA_W { w: self }
241 }
242 #[doc = "Bit 29 - Must Be Set to 1"]
243 #[inline(always)]
244 pub fn one(&mut self) -> ONE_W {
245 ONE_W { w: self }
246 }
247 #[doc = "Writes raw bits to the register."]
248 #[inline(always)]
249 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
250 self.0.bits(bits);
251 self
252 }
253}
254#[doc = "PLLA Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ckgr_pllar](index.html) module"]
255pub struct CKGR_PLLAR_SPEC;
256impl crate::RegisterSpec for CKGR_PLLAR_SPEC {
257 type Ux = u32;
258}
259#[doc = "`read()` method returns [ckgr_pllar::R](R) reader structure"]
260impl crate::Readable for CKGR_PLLAR_SPEC {
261 type Reader = R;
262}
263#[doc = "`write(|w| ..)` method takes [ckgr_pllar::W](W) writer structure"]
264impl crate::Writable for CKGR_PLLAR_SPEC {
265 type Writer = W;
266}
267#[doc = "`reset()` method sets CKGR_PLLAR to value 0"]
268impl crate::Resettable for CKGR_PLLAR_SPEC {
269 #[inline(always)]
270 fn reset_value() -> Self::Ux {
271 0
272 }
273}