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#[doc = r"Value read from the register"] pub struct R { bits: u32, } #[doc = r"Value to write to the register"] pub struct W { bits: u32, } impl super::MATRIX_SCFG { #[doc = r"Modifies the contents of the register"] #[inline(always)] pub fn modify<F>(&self, f: F) where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, { let bits = self.register.get(); self.register.set(f(&R { bits }, &mut W { bits }).bits); } #[doc = r"Reads the contents of the register"] #[inline(always)] pub fn read(&self) -> R { R { bits: self.register.get(), } } #[doc = r"Writes to the register"] #[inline(always)] pub fn write<F>(&self, f: F) where F: FnOnce(&mut W) -> &mut W, { self.register.set( f(&mut W { bits: Self::reset_value(), }) .bits, ); } #[doc = r"Reset value of the register"] #[inline(always)] pub const fn reset_value() -> u32 { 0 } #[doc = r"Writes the reset value to the register"] #[inline(always)] pub fn reset(&self) { self.register.set(Self::reset_value()) } } #[doc = r"Reader of the field"] pub type SLOT_CYCLE_R = crate::FR<u16, u16>; #[doc = r"Proxy"] pub struct _SLOT_CYCLEW<'a> { w: &'a mut W, } impl<'a> _SLOT_CYCLEW<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u16) -> &'a mut W { self.w.bits = (self.w.bits & !0x01ff) | ((value as u32) & 0x01ff); self.w } } #[doc = "Possible values of the field `DEFMSTR_TYPE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DEFMSTR_TYPER { #[doc = "No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access."] NONE, #[doc = "Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again."] LAST, #[doc = "Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again."] FIXED, } impl crate::ToBits<u8> for DEFMSTR_TYPER { #[inline(always)] fn _bits(&self) -> u8 { match *self { DEFMSTR_TYPER::NONE => 0, DEFMSTR_TYPER::LAST => 1, DEFMSTR_TYPER::FIXED => 2, } } } #[doc = r"Reader of the field"] pub type DEFMSTR_TYPE_R = crate::FR<u8, DEFMSTR_TYPER>; impl DEFMSTR_TYPE_R { #[doc = "Checks if the value of the field is `NONE`"] #[inline(always)] pub fn is_none(&self) -> bool { *self == DEFMSTR_TYPER::NONE } #[doc = "Checks if the value of the field is `LAST`"] #[inline(always)] pub fn is_last(&self) -> bool { *self == DEFMSTR_TYPER::LAST } #[doc = "Checks if the value of the field is `FIXED`"] #[inline(always)] pub fn is_fixed(&self) -> bool { *self == DEFMSTR_TYPER::FIXED } } #[doc = "Values that can be written to the field `DEFMSTR_TYPE`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum DEFMSTR_TYPEW { #[doc = "No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access."] NONE, #[doc = "Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again."] LAST, #[doc = "Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again."] FIXED, } impl DEFMSTR_TYPEW { #[allow(missing_docs)] #[doc(hidden)] #[inline(always)] pub fn _bits(&self) -> u8 { match *self { DEFMSTR_TYPEW::NONE => 0, DEFMSTR_TYPEW::LAST => 1, DEFMSTR_TYPEW::FIXED => 2, } } } #[doc = r"Proxy"] pub struct _DEFMSTR_TYPEW<'a> { w: &'a mut W, } impl<'a> _DEFMSTR_TYPEW<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: DEFMSTR_TYPEW) -> &'a mut W { unsafe { self.bits(variant._bits()) } } #[doc = "No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access."] #[inline(always)] pub fn none(self) -> &'a mut W { self.variant(DEFMSTR_TYPEW::NONE) } #[doc = "Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again."] #[inline(always)] pub fn last(self) -> &'a mut W { self.variant(DEFMSTR_TYPEW::LAST) } #[doc = "Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again."] #[inline(always)] pub fn fixed(self) -> &'a mut W { self.variant(DEFMSTR_TYPEW::FIXED) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16); self.w } } #[doc = r"Reader of the field"] pub type FIXED_DEFMSTR_R = crate::FR<u8, u8>; #[doc = r"Proxy"] pub struct _FIXED_DEFMSTRW<'a> { w: &'a mut W, } impl<'a> _FIXED_DEFMSTRW<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 18)) | (((value as u32) & 0x0f) << 18); self.w } } impl R { #[doc = r"Value of the register as raw bits"] #[inline(always)] pub fn bits(&self) -> u32 { self.bits } #[doc = "Bits 0:8 - Maximum Bus Grant Duration for Masters"] #[inline(always)] pub fn slot_cycle(&self) -> SLOT_CYCLE_R { SLOT_CYCLE_R::new((self.bits() & 0x01ff) as u16) } #[doc = "Bits 16:17 - Default Master Type"] #[inline(always)] pub fn defmstr_type(&self) -> DEFMSTR_TYPE_R { DEFMSTR_TYPE_R::new(((self.bits() >> 16) & 0x03) as u8) } #[doc = "Bits 18:21 - Fixed Default Master"] #[inline(always)] pub fn fixed_defmstr(&self) -> FIXED_DEFMSTR_R { FIXED_DEFMSTR_R::new(((self.bits() >> 18) & 0x0f) as u8) } } impl W { #[doc = r"Writes raw bits to the register"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; self } #[doc = "Bits 0:8 - Maximum Bus Grant Duration for Masters"] #[inline(always)] pub fn slot_cycle(&mut self) -> _SLOT_CYCLEW { _SLOT_CYCLEW { w: self } } #[doc = "Bits 16:17 - Default Master Type"] #[inline(always)] pub fn defmstr_type(&mut self) -> _DEFMSTR_TYPEW { _DEFMSTR_TYPEW { w: self } } #[doc = "Bits 18:21 - Fixed Default Master"] #[inline(always)] pub fn fixed_defmstr(&mut self) -> _FIXED_DEFMSTRW { _FIXED_DEFMSTRW { w: self } } }