atsams70j20/icm/
icm_ctrl.rs

1#[doc = "Register `ICM_CTRL` writer"]
2pub struct W(crate::W<ICM_CTRL_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<ICM_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<ICM_CTRL_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<ICM_CTRL_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `ENABLE` writer - ICM Enable"]
23pub struct ENABLE_W<'a> {
24    w: &'a mut W,
25}
26impl<'a> ENABLE_W<'a> {
27    #[doc = r"Sets the field bit"]
28    #[inline(always)]
29    pub fn set_bit(self) -> &'a mut W {
30        self.bit(true)
31    }
32    #[doc = r"Clears the field bit"]
33    #[inline(always)]
34    pub fn clear_bit(self) -> &'a mut W {
35        self.bit(false)
36    }
37    #[doc = r"Writes raw bits to the field"]
38    #[inline(always)]
39    pub fn bit(self, value: bool) -> &'a mut W {
40        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
41        self.w
42    }
43}
44#[doc = "Field `DISABLE` writer - ICM Disable Register"]
45pub struct DISABLE_W<'a> {
46    w: &'a mut W,
47}
48impl<'a> DISABLE_W<'a> {
49    #[doc = r"Sets the field bit"]
50    #[inline(always)]
51    pub fn set_bit(self) -> &'a mut W {
52        self.bit(true)
53    }
54    #[doc = r"Clears the field bit"]
55    #[inline(always)]
56    pub fn clear_bit(self) -> &'a mut W {
57        self.bit(false)
58    }
59    #[doc = r"Writes raw bits to the field"]
60    #[inline(always)]
61    pub fn bit(self, value: bool) -> &'a mut W {
62        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
63        self.w
64    }
65}
66#[doc = "Field `SWRST` writer - Software Reset"]
67pub struct SWRST_W<'a> {
68    w: &'a mut W,
69}
70impl<'a> SWRST_W<'a> {
71    #[doc = r"Sets the field bit"]
72    #[inline(always)]
73    pub fn set_bit(self) -> &'a mut W {
74        self.bit(true)
75    }
76    #[doc = r"Clears the field bit"]
77    #[inline(always)]
78    pub fn clear_bit(self) -> &'a mut W {
79        self.bit(false)
80    }
81    #[doc = r"Writes raw bits to the field"]
82    #[inline(always)]
83    pub fn bit(self, value: bool) -> &'a mut W {
84        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
85        self.w
86    }
87}
88#[doc = "Field `REHASH` writer - Recompute Internal Hash"]
89pub struct REHASH_W<'a> {
90    w: &'a mut W,
91}
92impl<'a> REHASH_W<'a> {
93    #[doc = r"Writes raw bits to the field"]
94    #[inline(always)]
95    pub unsafe fn bits(self, value: u8) -> &'a mut W {
96        self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4);
97        self.w
98    }
99}
100#[doc = "Field `RMDIS` writer - Region Monitoring Disable"]
101pub struct RMDIS_W<'a> {
102    w: &'a mut W,
103}
104impl<'a> RMDIS_W<'a> {
105    #[doc = r"Writes raw bits to the field"]
106    #[inline(always)]
107    pub unsafe fn bits(self, value: u8) -> &'a mut W {
108        self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8);
109        self.w
110    }
111}
112#[doc = "Field `RMEN` writer - Region Monitoring Enable"]
113pub struct RMEN_W<'a> {
114    w: &'a mut W,
115}
116impl<'a> RMEN_W<'a> {
117    #[doc = r"Writes raw bits to the field"]
118    #[inline(always)]
119    pub unsafe fn bits(self, value: u8) -> &'a mut W {
120        self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12);
121        self.w
122    }
123}
124impl W {
125    #[doc = "Bit 0 - ICM Enable"]
126    #[inline(always)]
127    pub fn enable(&mut self) -> ENABLE_W {
128        ENABLE_W { w: self }
129    }
130    #[doc = "Bit 1 - ICM Disable Register"]
131    #[inline(always)]
132    pub fn disable(&mut self) -> DISABLE_W {
133        DISABLE_W { w: self }
134    }
135    #[doc = "Bit 2 - Software Reset"]
136    #[inline(always)]
137    pub fn swrst(&mut self) -> SWRST_W {
138        SWRST_W { w: self }
139    }
140    #[doc = "Bits 4:7 - Recompute Internal Hash"]
141    #[inline(always)]
142    pub fn rehash(&mut self) -> REHASH_W {
143        REHASH_W { w: self }
144    }
145    #[doc = "Bits 8:11 - Region Monitoring Disable"]
146    #[inline(always)]
147    pub fn rmdis(&mut self) -> RMDIS_W {
148        RMDIS_W { w: self }
149    }
150    #[doc = "Bits 12:15 - Region Monitoring Enable"]
151    #[inline(always)]
152    pub fn rmen(&mut self) -> RMEN_W {
153        RMEN_W { w: self }
154    }
155    #[doc = "Writes raw bits to the register."]
156    #[inline(always)]
157    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
158        self.0.bits(bits);
159        self
160    }
161}
162#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icm_ctrl](index.html) module"]
163pub struct ICM_CTRL_SPEC;
164impl crate::RegisterSpec for ICM_CTRL_SPEC {
165    type Ux = u32;
166}
167#[doc = "`write(|w| ..)` method takes [icm_ctrl::W](W) writer structure"]
168impl crate::Writable for ICM_CTRL_SPEC {
169    type Writer = W;
170}
171#[doc = "`reset()` method sets ICM_CTRL to value 0"]
172impl crate::Resettable for ICM_CTRL_SPEC {
173    #[inline(always)]
174    fn reset_value() -> Self::Ux {
175        0
176    }
177}
atsams70j20/icm/icm_ctrl.rs

atsams70j20/icm/
icm_ctrl.rs
