atsaml21j18bu/rtc/mode2/
syncbusy.rs

1#[doc = "Register `SYNCBUSY` reader"]
2pub struct R(crate::R<SYNCBUSY_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SYNCBUSY_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SYNCBUSY_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SYNCBUSY_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `SWRST` reader - Software Reset Bit Busy"]
17pub type SWRST_R = crate::BitReader<bool>;
18#[doc = "Field `ENABLE` reader - Enable Bit Busy"]
19pub type ENABLE_R = crate::BitReader<bool>;
20#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"]
21pub type FREQCORR_R = crate::BitReader<bool>;
22#[doc = "Field `CLOCK` reader - CLOCK Register Busy"]
23pub type CLOCK_R = crate::BitReader<bool>;
24#[doc = "Field `ALARM0` reader - ALARM 0 Register Busy"]
25pub type ALARM0_R = crate::BitReader<bool>;
26#[doc = "Field `MASK0` reader - MASK 0 Register Busy"]
27pub type MASK0_R = crate::BitReader<bool>;
28#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable Bit Busy"]
29pub type CLOCKSYNC_R = crate::BitReader<bool>;
30impl R {
31    #[doc = "Bit 0 - Software Reset Bit Busy"]
32    #[inline(always)]
33    pub fn swrst(&self) -> SWRST_R {
34        SWRST_R::new((self.bits & 1) != 0)
35    }
36    #[doc = "Bit 1 - Enable Bit Busy"]
37    #[inline(always)]
38    pub fn enable(&self) -> ENABLE_R {
39        ENABLE_R::new(((self.bits >> 1) & 1) != 0)
40    }
41    #[doc = "Bit 2 - FREQCORR Register Busy"]
42    #[inline(always)]
43    pub fn freqcorr(&self) -> FREQCORR_R {
44        FREQCORR_R::new(((self.bits >> 2) & 1) != 0)
45    }
46    #[doc = "Bit 3 - CLOCK Register Busy"]
47    #[inline(always)]
48    pub fn clock(&self) -> CLOCK_R {
49        CLOCK_R::new(((self.bits >> 3) & 1) != 0)
50    }
51    #[doc = "Bit 5 - ALARM 0 Register Busy"]
52    #[inline(always)]
53    pub fn alarm0(&self) -> ALARM0_R {
54        ALARM0_R::new(((self.bits >> 5) & 1) != 0)
55    }
56    #[doc = "Bit 11 - MASK 0 Register Busy"]
57    #[inline(always)]
58    pub fn mask0(&self) -> MASK0_R {
59        MASK0_R::new(((self.bits >> 11) & 1) != 0)
60    }
61    #[doc = "Bit 15 - Clock Read Synchronization Enable Bit Busy"]
62    #[inline(always)]
63    pub fn clocksync(&self) -> CLOCKSYNC_R {
64        CLOCKSYNC_R::new(((self.bits >> 15) & 1) != 0)
65    }
66}
67#[doc = "MODE2 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"]
68pub struct SYNCBUSY_SPEC;
69impl crate::RegisterSpec for SYNCBUSY_SPEC {
70    type Ux = u32;
71}
72#[doc = "`read()` method returns [syncbusy::R](R) reader structure"]
73impl crate::Readable for SYNCBUSY_SPEC {
74    type Reader = R;
75}
76#[doc = "`reset()` method sets SYNCBUSY to value 0"]
77impl crate::Resettable for SYNCBUSY_SPEC {
78    const RESET_VALUE: Self::Ux = 0;
79}
atsaml21j18bu/rtc/mode2/syncbusy.rs

atsaml21j18bu/rtc/mode2/
syncbusy.rs
