atsaml21j18bu/dac/
dacctrl.rs

1#[doc = "Register `DACCTRL%s` reader"]
2pub struct R(crate::R<DACCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DACCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DACCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DACCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DACCTRL%s` writer"]
17pub struct W(crate::W<DACCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DACCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DACCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DACCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `LEFTADJ` reader - Left Adjusted Data"]
38pub type LEFTADJ_R = crate::BitReader<bool>;
39#[doc = "Field `LEFTADJ` writer - Left Adjusted Data"]
40pub type LEFTADJ_W<'a, const O: u8> = crate::BitWriter<'a, u16, DACCTRL_SPEC, bool, O>;
41#[doc = "Field `ENABLE` reader - Enable DAC0"]
42pub type ENABLE_R = crate::BitReader<bool>;
43#[doc = "Field `ENABLE` writer - Enable DAC0"]
44pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u16, DACCTRL_SPEC, bool, O>;
45#[doc = "Field `CCTRL` reader - Current Control"]
46pub type CCTRL_R = crate::FieldReader<u8, CCTRLSELECT_A>;
47#[doc = "Current Control\n\nValue on reset: 0"]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49#[repr(u8)]
50pub enum CCTRLSELECT_A {
51    #[doc = "0: GCLK_DAC <= 1.2MHz (100kSPS)"]
52    CC100K = 0,
53    #[doc = "1: 1.2MHz < GCLK_DAC <= 6MHz (500kSPS)"]
54    CC1M = 1,
55    #[doc = "2: 6MHz < GCLK_DAC <=12MHz (1MSPS)"]
56    CC12M = 2,
57}
58impl From<CCTRLSELECT_A> for u8 {
59    #[inline(always)]
60    fn from(variant: CCTRLSELECT_A) -> Self {
61        variant as _
62    }
63}
64impl CCTRL_R {
65    #[doc = "Get enumerated values variant"]
66    #[inline(always)]
67    pub fn variant(&self) -> Option<CCTRLSELECT_A> {
68        match self.bits {
69            0 => Some(CCTRLSELECT_A::CC100K),
70            1 => Some(CCTRLSELECT_A::CC1M),
71            2 => Some(CCTRLSELECT_A::CC12M),
72            _ => None,
73        }
74    }
75    #[doc = "Checks if the value of the field is `CC100K`"]
76    #[inline(always)]
77    pub fn is_cc100k(&self) -> bool {
78        *self == CCTRLSELECT_A::CC100K
79    }
80    #[doc = "Checks if the value of the field is `CC1M`"]
81    #[inline(always)]
82    pub fn is_cc1m(&self) -> bool {
83        *self == CCTRLSELECT_A::CC1M
84    }
85    #[doc = "Checks if the value of the field is `CC12M`"]
86    #[inline(always)]
87    pub fn is_cc12m(&self) -> bool {
88        *self == CCTRLSELECT_A::CC12M
89    }
90}
91#[doc = "Field `CCTRL` writer - Current Control"]
92pub type CCTRL_W<'a, const O: u8> =
93    crate::FieldWriter<'a, u16, DACCTRL_SPEC, u8, CCTRLSELECT_A, 2, O>;
94impl<'a, const O: u8> CCTRL_W<'a, O> {
95    #[doc = "GCLK_DAC <= 1.2MHz (100kSPS)"]
96    #[inline(always)]
97    pub fn cc100k(self) -> &'a mut W {
98        self.variant(CCTRLSELECT_A::CC100K)
99    }
100    #[doc = "1.2MHz < GCLK_DAC <= 6MHz (500kSPS)"]
101    #[inline(always)]
102    pub fn cc1m(self) -> &'a mut W {
103        self.variant(CCTRLSELECT_A::CC1M)
104    }
105    #[doc = "6MHz < GCLK_DAC <=12MHz (1MSPS)"]
106    #[inline(always)]
107    pub fn cc12m(self) -> &'a mut W {
108        self.variant(CCTRLSELECT_A::CC12M)
109    }
110}
111#[doc = "Field `RUNSTDBY` reader - Run in Standby"]
112pub type RUNSTDBY_R = crate::BitReader<bool>;
113#[doc = "Field `RUNSTDBY` writer - Run in Standby"]
114pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u16, DACCTRL_SPEC, bool, O>;
115#[doc = "Field `DITHER` reader - Dithering Mode"]
116pub type DITHER_R = crate::BitReader<bool>;
117#[doc = "Field `DITHER` writer - Dithering Mode"]
118pub type DITHER_W<'a, const O: u8> = crate::BitWriter<'a, u16, DACCTRL_SPEC, bool, O>;
119#[doc = "Field `REFRESH` reader - Refresh period"]
120pub type REFRESH_R = crate::FieldReader<u8, u8>;
121#[doc = "Field `REFRESH` writer - Refresh period"]
122pub type REFRESH_W<'a, const O: u8> = crate::FieldWriter<'a, u16, DACCTRL_SPEC, u8, u8, 4, O>;
123impl R {
124    #[doc = "Bit 0 - Left Adjusted Data"]
125    #[inline(always)]
126    pub fn leftadj(&self) -> LEFTADJ_R {
127        LEFTADJ_R::new((self.bits & 1) != 0)
128    }
129    #[doc = "Bit 1 - Enable DAC0"]
130    #[inline(always)]
131    pub fn enable(&self) -> ENABLE_R {
132        ENABLE_R::new(((self.bits >> 1) & 1) != 0)
133    }
134    #[doc = "Bits 2:3 - Current Control"]
135    #[inline(always)]
136    pub fn cctrl(&self) -> CCTRL_R {
137        CCTRL_R::new(((self.bits >> 2) & 3) as u8)
138    }
139    #[doc = "Bit 6 - Run in Standby"]
140    #[inline(always)]
141    pub fn runstdby(&self) -> RUNSTDBY_R {
142        RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0)
143    }
144    #[doc = "Bit 7 - Dithering Mode"]
145    #[inline(always)]
146    pub fn dither(&self) -> DITHER_R {
147        DITHER_R::new(((self.bits >> 7) & 1) != 0)
148    }
149    #[doc = "Bits 8:11 - Refresh period"]
150    #[inline(always)]
151    pub fn refresh(&self) -> REFRESH_R {
152        REFRESH_R::new(((self.bits >> 8) & 0x0f) as u8)
153    }
154}
155impl W {
156    #[doc = "Bit 0 - Left Adjusted Data"]
157    #[inline(always)]
158    #[must_use]
159    pub fn leftadj(&mut self) -> LEFTADJ_W<0> {
160        LEFTADJ_W::new(self)
161    }
162    #[doc = "Bit 1 - Enable DAC0"]
163    #[inline(always)]
164    #[must_use]
165    pub fn enable(&mut self) -> ENABLE_W<1> {
166        ENABLE_W::new(self)
167    }
168    #[doc = "Bits 2:3 - Current Control"]
169    #[inline(always)]
170    #[must_use]
171    pub fn cctrl(&mut self) -> CCTRL_W<2> {
172        CCTRL_W::new(self)
173    }
174    #[doc = "Bit 6 - Run in Standby"]
175    #[inline(always)]
176    #[must_use]
177    pub fn runstdby(&mut self) -> RUNSTDBY_W<6> {
178        RUNSTDBY_W::new(self)
179    }
180    #[doc = "Bit 7 - Dithering Mode"]
181    #[inline(always)]
182    #[must_use]
183    pub fn dither(&mut self) -> DITHER_W<7> {
184        DITHER_W::new(self)
185    }
186    #[doc = "Bits 8:11 - Refresh period"]
187    #[inline(always)]
188    #[must_use]
189    pub fn refresh(&mut self) -> REFRESH_W<8> {
190        REFRESH_W::new(self)
191    }
192    #[doc = "Writes raw bits to the register."]
193    #[inline(always)]
194    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
195        self.0.bits(bits);
196        self
197    }
198}
199#[doc = "DAC n Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dacctrl](index.html) module"]
200pub struct DACCTRL_SPEC;
201impl crate::RegisterSpec for DACCTRL_SPEC {
202    type Ux = u16;
203}
204#[doc = "`read()` method returns [dacctrl::R](R) reader structure"]
205impl crate::Readable for DACCTRL_SPEC {
206    type Reader = R;
207}
208#[doc = "`write(|w| ..)` method takes [dacctrl::W](W) writer structure"]
209impl crate::Writable for DACCTRL_SPEC {
210    type Writer = W;
211    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
212    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
213}
214#[doc = "`reset()` method sets DACCTRL%s to value 0"]
215impl crate::Resettable for DACCTRL_SPEC {
216    const RESET_VALUE: Self::Ux = 0;
217}
atsaml21j18bu/dac/dacctrl.rs

atsaml21j18bu/dac/
dacctrl.rs
