atsaml21j17bu/dsu/
ctrl.rs

1#[doc = "Register `CTRL` writer"]
2pub struct W(crate::W<CTRL_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<CTRL_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `SWRST` writer - Software Reset"]
23pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRL_SPEC, bool, O>;
24#[doc = "Field `CRC` writer - 32-bit Cyclic Redundancy Code"]
25pub type CRC_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRL_SPEC, bool, O>;
26#[doc = "Field `MBIST` writer - Memory built-in self-test"]
27pub type MBIST_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRL_SPEC, bool, O>;
28#[doc = "Field `CE` writer - Chip-Erase"]
29pub type CE_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRL_SPEC, bool, O>;
30#[doc = "Field `ARR` writer - Auxiliary Row Read"]
31pub type ARR_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRL_SPEC, bool, O>;
32#[doc = "Field `SMSA` writer - Start Memory Stream Access"]
33pub type SMSA_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRL_SPEC, bool, O>;
34impl W {
35    #[doc = "Bit 0 - Software Reset"]
36    #[inline(always)]
37    #[must_use]
38    pub fn swrst(&mut self) -> SWRST_W<0> {
39        SWRST_W::new(self)
40    }
41    #[doc = "Bit 2 - 32-bit Cyclic Redundancy Code"]
42    #[inline(always)]
43    #[must_use]
44    pub fn crc(&mut self) -> CRC_W<2> {
45        CRC_W::new(self)
46    }
47    #[doc = "Bit 3 - Memory built-in self-test"]
48    #[inline(always)]
49    #[must_use]
50    pub fn mbist(&mut self) -> MBIST_W<3> {
51        MBIST_W::new(self)
52    }
53    #[doc = "Bit 4 - Chip-Erase"]
54    #[inline(always)]
55    #[must_use]
56    pub fn ce(&mut self) -> CE_W<4> {
57        CE_W::new(self)
58    }
59    #[doc = "Bit 6 - Auxiliary Row Read"]
60    #[inline(always)]
61    #[must_use]
62    pub fn arr(&mut self) -> ARR_W<6> {
63        ARR_W::new(self)
64    }
65    #[doc = "Bit 7 - Start Memory Stream Access"]
66    #[inline(always)]
67    #[must_use]
68    pub fn smsa(&mut self) -> SMSA_W<7> {
69        SMSA_W::new(self)
70    }
71    #[doc = "Writes raw bits to the register."]
72    #[inline(always)]
73    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
74        self.0.bits(bits);
75        self
76    }
77}
78#[doc = "Control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
79pub struct CTRL_SPEC;
80impl crate::RegisterSpec for CTRL_SPEC {
81    type Ux = u8;
82}
83#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
84impl crate::Writable for CTRL_SPEC {
85    type Writer = W;
86    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
87    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
88}
89#[doc = "`reset()` method sets CTRL to value 0"]
90impl crate::Resettable for CTRL_SPEC {
91    const RESET_VALUE: Self::Ux = 0;
92}
atsaml21j17bu/dsu/ctrl.rs

atsaml21j17bu/dsu/
ctrl.rs
