atsaml21g18b/oscctrl/
intenset.rs

1#[doc = "Register `INTENSET` reader"]
2pub struct R(crate::R<INTENSET_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INTENSET_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INTENSET_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `INTENSET` writer"]
17pub struct W(crate::W<INTENSET_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INTENSET_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INTENSET_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"]
38pub type XOSCRDY_R = crate::BitReader<bool>;
39#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"]
40pub type XOSCRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>;
41#[doc = "Field `OSC16MRDY` reader - OSC16M Ready Interrupt Enable"]
42pub type OSC16MRDY_R = crate::BitReader<bool>;
43#[doc = "Field `OSC16MRDY` writer - OSC16M Ready Interrupt Enable"]
44pub type OSC16MRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>;
45#[doc = "Field `DFLLRDY` reader - DFLL Ready Interrupt Enable"]
46pub type DFLLRDY_R = crate::BitReader<bool>;
47#[doc = "Field `DFLLRDY` writer - DFLL Ready Interrupt Enable"]
48pub type DFLLRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>;
49#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds Interrupt Enable"]
50pub type DFLLOOB_R = crate::BitReader<bool>;
51#[doc = "Field `DFLLOOB` writer - DFLL Out Of Bounds Interrupt Enable"]
52pub type DFLLOOB_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>;
53#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine Interrupt Enable"]
54pub type DFLLLCKF_R = crate::BitReader<bool>;
55#[doc = "Field `DFLLLCKF` writer - DFLL Lock Fine Interrupt Enable"]
56pub type DFLLLCKF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>;
57#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse Interrupt Enable"]
58pub type DFLLLCKC_R = crate::BitReader<bool>;
59#[doc = "Field `DFLLLCKC` writer - DFLL Lock Coarse Interrupt Enable"]
60pub type DFLLLCKC_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>;
61#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped Interrupt Enable"]
62pub type DFLLRCS_R = crate::BitReader<bool>;
63#[doc = "Field `DFLLRCS` writer - DFLL Reference Clock Stopped Interrupt Enable"]
64pub type DFLLRCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>;
65#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"]
66pub type DPLLLCKR_R = crate::BitReader<bool>;
67#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"]
68pub type DPLLLCKR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>;
69#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"]
70pub type DPLLLCKF_R = crate::BitReader<bool>;
71#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"]
72pub type DPLLLCKF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>;
73#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"]
74pub type DPLLLTO_R = crate::BitReader<bool>;
75#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"]
76pub type DPLLLTO_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>;
77#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"]
78pub type DPLLLDRTO_R = crate::BitReader<bool>;
79#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"]
80pub type DPLLLDRTO_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>;
81impl R {
82    #[doc = "Bit 0 - XOSC Ready Interrupt Enable"]
83    #[inline(always)]
84    pub fn xoscrdy(&self) -> XOSCRDY_R {
85        XOSCRDY_R::new((self.bits & 1) != 0)
86    }
87    #[doc = "Bit 4 - OSC16M Ready Interrupt Enable"]
88    #[inline(always)]
89    pub fn osc16mrdy(&self) -> OSC16MRDY_R {
90        OSC16MRDY_R::new(((self.bits >> 4) & 1) != 0)
91    }
92    #[doc = "Bit 8 - DFLL Ready Interrupt Enable"]
93    #[inline(always)]
94    pub fn dfllrdy(&self) -> DFLLRDY_R {
95        DFLLRDY_R::new(((self.bits >> 8) & 1) != 0)
96    }
97    #[doc = "Bit 9 - DFLL Out Of Bounds Interrupt Enable"]
98    #[inline(always)]
99    pub fn dflloob(&self) -> DFLLOOB_R {
100        DFLLOOB_R::new(((self.bits >> 9) & 1) != 0)
101    }
102    #[doc = "Bit 10 - DFLL Lock Fine Interrupt Enable"]
103    #[inline(always)]
104    pub fn dflllckf(&self) -> DFLLLCKF_R {
105        DFLLLCKF_R::new(((self.bits >> 10) & 1) != 0)
106    }
107    #[doc = "Bit 11 - DFLL Lock Coarse Interrupt Enable"]
108    #[inline(always)]
109    pub fn dflllckc(&self) -> DFLLLCKC_R {
110        DFLLLCKC_R::new(((self.bits >> 11) & 1) != 0)
111    }
112    #[doc = "Bit 12 - DFLL Reference Clock Stopped Interrupt Enable"]
113    #[inline(always)]
114    pub fn dfllrcs(&self) -> DFLLRCS_R {
115        DFLLRCS_R::new(((self.bits >> 12) & 1) != 0)
116    }
117    #[doc = "Bit 16 - DPLL Lock Rise Interrupt Enable"]
118    #[inline(always)]
119    pub fn dplllckr(&self) -> DPLLLCKR_R {
120        DPLLLCKR_R::new(((self.bits >> 16) & 1) != 0)
121    }
122    #[doc = "Bit 17 - DPLL Lock Fall Interrupt Enable"]
123    #[inline(always)]
124    pub fn dplllckf(&self) -> DPLLLCKF_R {
125        DPLLLCKF_R::new(((self.bits >> 17) & 1) != 0)
126    }
127    #[doc = "Bit 18 - DPLL Time Out Interrupt Enable"]
128    #[inline(always)]
129    pub fn dplllto(&self) -> DPLLLTO_R {
130        DPLLLTO_R::new(((self.bits >> 18) & 1) != 0)
131    }
132    #[doc = "Bit 19 - DPLL Ratio Ready Interrupt Enable"]
133    #[inline(always)]
134    pub fn dpllldrto(&self) -> DPLLLDRTO_R {
135        DPLLLDRTO_R::new(((self.bits >> 19) & 1) != 0)
136    }
137}
138impl W {
139    #[doc = "Bit 0 - XOSC Ready Interrupt Enable"]
140    #[inline(always)]
141    #[must_use]
142    pub fn xoscrdy(&mut self) -> XOSCRDY_W<0> {
143        XOSCRDY_W::new(self)
144    }
145    #[doc = "Bit 4 - OSC16M Ready Interrupt Enable"]
146    #[inline(always)]
147    #[must_use]
148    pub fn osc16mrdy(&mut self) -> OSC16MRDY_W<4> {
149        OSC16MRDY_W::new(self)
150    }
151    #[doc = "Bit 8 - DFLL Ready Interrupt Enable"]
152    #[inline(always)]
153    #[must_use]
154    pub fn dfllrdy(&mut self) -> DFLLRDY_W<8> {
155        DFLLRDY_W::new(self)
156    }
157    #[doc = "Bit 9 - DFLL Out Of Bounds Interrupt Enable"]
158    #[inline(always)]
159    #[must_use]
160    pub fn dflloob(&mut self) -> DFLLOOB_W<9> {
161        DFLLOOB_W::new(self)
162    }
163    #[doc = "Bit 10 - DFLL Lock Fine Interrupt Enable"]
164    #[inline(always)]
165    #[must_use]
166    pub fn dflllckf(&mut self) -> DFLLLCKF_W<10> {
167        DFLLLCKF_W::new(self)
168    }
169    #[doc = "Bit 11 - DFLL Lock Coarse Interrupt Enable"]
170    #[inline(always)]
171    #[must_use]
172    pub fn dflllckc(&mut self) -> DFLLLCKC_W<11> {
173        DFLLLCKC_W::new(self)
174    }
175    #[doc = "Bit 12 - DFLL Reference Clock Stopped Interrupt Enable"]
176    #[inline(always)]
177    #[must_use]
178    pub fn dfllrcs(&mut self) -> DFLLRCS_W<12> {
179        DFLLRCS_W::new(self)
180    }
181    #[doc = "Bit 16 - DPLL Lock Rise Interrupt Enable"]
182    #[inline(always)]
183    #[must_use]
184    pub fn dplllckr(&mut self) -> DPLLLCKR_W<16> {
185        DPLLLCKR_W::new(self)
186    }
187    #[doc = "Bit 17 - DPLL Lock Fall Interrupt Enable"]
188    #[inline(always)]
189    #[must_use]
190    pub fn dplllckf(&mut self) -> DPLLLCKF_W<17> {
191        DPLLLCKF_W::new(self)
192    }
193    #[doc = "Bit 18 - DPLL Time Out Interrupt Enable"]
194    #[inline(always)]
195    #[must_use]
196    pub fn dplllto(&mut self) -> DPLLLTO_W<18> {
197        DPLLLTO_W::new(self)
198    }
199    #[doc = "Bit 19 - DPLL Ratio Ready Interrupt Enable"]
200    #[inline(always)]
201    #[must_use]
202    pub fn dpllldrto(&mut self) -> DPLLLDRTO_W<19> {
203        DPLLLDRTO_W::new(self)
204    }
205    #[doc = "Writes raw bits to the register."]
206    #[inline(always)]
207    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
208        self.0.bits(bits);
209        self
210    }
211}
212#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
213pub struct INTENSET_SPEC;
214impl crate::RegisterSpec for INTENSET_SPEC {
215    type Ux = u32;
216}
217#[doc = "`read()` method returns [intenset::R](R) reader structure"]
218impl crate::Readable for INTENSET_SPEC {
219    type Reader = R;
220}
221#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
222impl crate::Writable for INTENSET_SPEC {
223    type Writer = W;
224    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
225    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
226}
227#[doc = "`reset()` method sets INTENSET to value 0"]
228impl crate::Resettable for INTENSET_SPEC {
229    const RESET_VALUE: Self::Ux = 0;
230}
atsaml21g18b/oscctrl/intenset.rs

atsaml21g18b/oscctrl/
intenset.rs
