atsaml21g18a/gclk/
genctrl.rs

1#[doc = "Register `GENCTRL%s` reader"]
2pub struct R(crate::R<GENCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<GENCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<GENCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<GENCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `GENCTRL%s` writer"]
17pub struct W(crate::W<GENCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<GENCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<GENCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<GENCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SRC` reader - Source Select"]
38pub type SRC_R = crate::FieldReader<u8, SRCSELECT_A>;
39#[doc = "Source Select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum SRCSELECT_A {
43    #[doc = "0: XOSC oscillator output"]
44    XOSC = 0,
45    #[doc = "1: Generator input pad"]
46    GCLKIN = 1,
47    #[doc = "2: Generic clock generator 1 output"]
48    GCLKGEN1 = 2,
49    #[doc = "3: OSCULP32K oscillator output"]
50    OSCULP32K = 3,
51    #[doc = "4: OSC32K oscillator output"]
52    OSC32K = 4,
53    #[doc = "5: XOSC32K oscillator output"]
54    XOSC32K = 5,
55    #[doc = "6: OSC16M oscillator output"]
56    OSC16M = 6,
57    #[doc = "7: DFLL48M output"]
58    DFLL48M = 7,
59    #[doc = "8: DPLL96M output"]
60    DPLL96M = 8,
61}
62impl From<SRCSELECT_A> for u8 {
63    #[inline(always)]
64    fn from(variant: SRCSELECT_A) -> Self {
65        variant as _
66    }
67}
68impl SRC_R {
69    #[doc = "Get enumerated values variant"]
70    #[inline(always)]
71    pub fn variant(&self) -> Option<SRCSELECT_A> {
72        match self.bits {
73            0 => Some(SRCSELECT_A::XOSC),
74            1 => Some(SRCSELECT_A::GCLKIN),
75            2 => Some(SRCSELECT_A::GCLKGEN1),
76            3 => Some(SRCSELECT_A::OSCULP32K),
77            4 => Some(SRCSELECT_A::OSC32K),
78            5 => Some(SRCSELECT_A::XOSC32K),
79            6 => Some(SRCSELECT_A::OSC16M),
80            7 => Some(SRCSELECT_A::DFLL48M),
81            8 => Some(SRCSELECT_A::DPLL96M),
82            _ => None,
83        }
84    }
85    #[doc = "Checks if the value of the field is `XOSC`"]
86    #[inline(always)]
87    pub fn is_xosc(&self) -> bool {
88        *self == SRCSELECT_A::XOSC
89    }
90    #[doc = "Checks if the value of the field is `GCLKIN`"]
91    #[inline(always)]
92    pub fn is_gclkin(&self) -> bool {
93        *self == SRCSELECT_A::GCLKIN
94    }
95    #[doc = "Checks if the value of the field is `GCLKGEN1`"]
96    #[inline(always)]
97    pub fn is_gclkgen1(&self) -> bool {
98        *self == SRCSELECT_A::GCLKGEN1
99    }
100    #[doc = "Checks if the value of the field is `OSCULP32K`"]
101    #[inline(always)]
102    pub fn is_osculp32k(&self) -> bool {
103        *self == SRCSELECT_A::OSCULP32K
104    }
105    #[doc = "Checks if the value of the field is `OSC32K`"]
106    #[inline(always)]
107    pub fn is_osc32k(&self) -> bool {
108        *self == SRCSELECT_A::OSC32K
109    }
110    #[doc = "Checks if the value of the field is `XOSC32K`"]
111    #[inline(always)]
112    pub fn is_xosc32k(&self) -> bool {
113        *self == SRCSELECT_A::XOSC32K
114    }
115    #[doc = "Checks if the value of the field is `OSC16M`"]
116    #[inline(always)]
117    pub fn is_osc16m(&self) -> bool {
118        *self == SRCSELECT_A::OSC16M
119    }
120    #[doc = "Checks if the value of the field is `DFLL48M`"]
121    #[inline(always)]
122    pub fn is_dfll48m(&self) -> bool {
123        *self == SRCSELECT_A::DFLL48M
124    }
125    #[doc = "Checks if the value of the field is `DPLL96M`"]
126    #[inline(always)]
127    pub fn is_dpll96m(&self) -> bool {
128        *self == SRCSELECT_A::DPLL96M
129    }
130}
131#[doc = "Field `SRC` writer - Source Select"]
132pub type SRC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GENCTRL_SPEC, u8, SRCSELECT_A, 5, O>;
133impl<'a, const O: u8> SRC_W<'a, O> {
134    #[doc = "XOSC oscillator output"]
135    #[inline(always)]
136    pub fn xosc(self) -> &'a mut W {
137        self.variant(SRCSELECT_A::XOSC)
138    }
139    #[doc = "Generator input pad"]
140    #[inline(always)]
141    pub fn gclkin(self) -> &'a mut W {
142        self.variant(SRCSELECT_A::GCLKIN)
143    }
144    #[doc = "Generic clock generator 1 output"]
145    #[inline(always)]
146    pub fn gclkgen1(self) -> &'a mut W {
147        self.variant(SRCSELECT_A::GCLKGEN1)
148    }
149    #[doc = "OSCULP32K oscillator output"]
150    #[inline(always)]
151    pub fn osculp32k(self) -> &'a mut W {
152        self.variant(SRCSELECT_A::OSCULP32K)
153    }
154    #[doc = "OSC32K oscillator output"]
155    #[inline(always)]
156    pub fn osc32k(self) -> &'a mut W {
157        self.variant(SRCSELECT_A::OSC32K)
158    }
159    #[doc = "XOSC32K oscillator output"]
160    #[inline(always)]
161    pub fn xosc32k(self) -> &'a mut W {
162        self.variant(SRCSELECT_A::XOSC32K)
163    }
164    #[doc = "OSC16M oscillator output"]
165    #[inline(always)]
166    pub fn osc16m(self) -> &'a mut W {
167        self.variant(SRCSELECT_A::OSC16M)
168    }
169    #[doc = "DFLL48M output"]
170    #[inline(always)]
171    pub fn dfll48m(self) -> &'a mut W {
172        self.variant(SRCSELECT_A::DFLL48M)
173    }
174    #[doc = "DPLL96M output"]
175    #[inline(always)]
176    pub fn dpll96m(self) -> &'a mut W {
177        self.variant(SRCSELECT_A::DPLL96M)
178    }
179}
180#[doc = "Field `GENEN` reader - Generic Clock Generator Enable"]
181pub type GENEN_R = crate::BitReader<bool>;
182#[doc = "Field `GENEN` writer - Generic Clock Generator Enable"]
183pub type GENEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GENCTRL_SPEC, bool, O>;
184#[doc = "Field `IDC` reader - Improve Duty Cycle"]
185pub type IDC_R = crate::BitReader<bool>;
186#[doc = "Field `IDC` writer - Improve Duty Cycle"]
187pub type IDC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GENCTRL_SPEC, bool, O>;
188#[doc = "Field `OOV` reader - Output Off Value"]
189pub type OOV_R = crate::BitReader<bool>;
190#[doc = "Field `OOV` writer - Output Off Value"]
191pub type OOV_W<'a, const O: u8> = crate::BitWriter<'a, u32, GENCTRL_SPEC, bool, O>;
192#[doc = "Field `OE` reader - Output Enable"]
193pub type OE_R = crate::BitReader<bool>;
194#[doc = "Field `OE` writer - Output Enable"]
195pub type OE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GENCTRL_SPEC, bool, O>;
196#[doc = "Field `DIVSEL` reader - Divide Selection"]
197pub type DIVSEL_R = crate::BitReader<bool>;
198#[doc = "Field `DIVSEL` writer - Divide Selection"]
199pub type DIVSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GENCTRL_SPEC, bool, O>;
200#[doc = "Field `RUNSTDBY` reader - Run in Standby"]
201pub type RUNSTDBY_R = crate::BitReader<bool>;
202#[doc = "Field `RUNSTDBY` writer - Run in Standby"]
203pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, GENCTRL_SPEC, bool, O>;
204#[doc = "Field `DIV` reader - Division Factor"]
205pub type DIV_R = crate::FieldReader<u16, u16>;
206#[doc = "Field `DIV` writer - Division Factor"]
207pub type DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GENCTRL_SPEC, u16, u16, 16, O>;
208impl R {
209    #[doc = "Bits 0:4 - Source Select"]
210    #[inline(always)]
211    pub fn src(&self) -> SRC_R {
212        SRC_R::new((self.bits & 0x1f) as u8)
213    }
214    #[doc = "Bit 8 - Generic Clock Generator Enable"]
215    #[inline(always)]
216    pub fn genen(&self) -> GENEN_R {
217        GENEN_R::new(((self.bits >> 8) & 1) != 0)
218    }
219    #[doc = "Bit 9 - Improve Duty Cycle"]
220    #[inline(always)]
221    pub fn idc(&self) -> IDC_R {
222        IDC_R::new(((self.bits >> 9) & 1) != 0)
223    }
224    #[doc = "Bit 10 - Output Off Value"]
225    #[inline(always)]
226    pub fn oov(&self) -> OOV_R {
227        OOV_R::new(((self.bits >> 10) & 1) != 0)
228    }
229    #[doc = "Bit 11 - Output Enable"]
230    #[inline(always)]
231    pub fn oe(&self) -> OE_R {
232        OE_R::new(((self.bits >> 11) & 1) != 0)
233    }
234    #[doc = "Bit 12 - Divide Selection"]
235    #[inline(always)]
236    pub fn divsel(&self) -> DIVSEL_R {
237        DIVSEL_R::new(((self.bits >> 12) & 1) != 0)
238    }
239    #[doc = "Bit 13 - Run in Standby"]
240    #[inline(always)]
241    pub fn runstdby(&self) -> RUNSTDBY_R {
242        RUNSTDBY_R::new(((self.bits >> 13) & 1) != 0)
243    }
244    #[doc = "Bits 16:31 - Division Factor"]
245    #[inline(always)]
246    pub fn div(&self) -> DIV_R {
247        DIV_R::new(((self.bits >> 16) & 0xffff) as u16)
248    }
249}
250impl W {
251    #[doc = "Bits 0:4 - Source Select"]
252    #[inline(always)]
253    #[must_use]
254    pub fn src(&mut self) -> SRC_W<0> {
255        SRC_W::new(self)
256    }
257    #[doc = "Bit 8 - Generic Clock Generator Enable"]
258    #[inline(always)]
259    #[must_use]
260    pub fn genen(&mut self) -> GENEN_W<8> {
261        GENEN_W::new(self)
262    }
263    #[doc = "Bit 9 - Improve Duty Cycle"]
264    #[inline(always)]
265    #[must_use]
266    pub fn idc(&mut self) -> IDC_W<9> {
267        IDC_W::new(self)
268    }
269    #[doc = "Bit 10 - Output Off Value"]
270    #[inline(always)]
271    #[must_use]
272    pub fn oov(&mut self) -> OOV_W<10> {
273        OOV_W::new(self)
274    }
275    #[doc = "Bit 11 - Output Enable"]
276    #[inline(always)]
277    #[must_use]
278    pub fn oe(&mut self) -> OE_W<11> {
279        OE_W::new(self)
280    }
281    #[doc = "Bit 12 - Divide Selection"]
282    #[inline(always)]
283    #[must_use]
284    pub fn divsel(&mut self) -> DIVSEL_W<12> {
285        DIVSEL_W::new(self)
286    }
287    #[doc = "Bit 13 - Run in Standby"]
288    #[inline(always)]
289    #[must_use]
290    pub fn runstdby(&mut self) -> RUNSTDBY_W<13> {
291        RUNSTDBY_W::new(self)
292    }
293    #[doc = "Bits 16:31 - Division Factor"]
294    #[inline(always)]
295    #[must_use]
296    pub fn div(&mut self) -> DIV_W<16> {
297        DIV_W::new(self)
298    }
299    #[doc = "Writes raw bits to the register."]
300    #[inline(always)]
301    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
302        self.0.bits(bits);
303        self
304    }
305}
306#[doc = "Generic Clock Generator Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [genctrl](index.html) module"]
307pub struct GENCTRL_SPEC;
308impl crate::RegisterSpec for GENCTRL_SPEC {
309    type Ux = u32;
310}
311#[doc = "`read()` method returns [genctrl::R](R) reader structure"]
312impl crate::Readable for GENCTRL_SPEC {
313    type Reader = R;
314}
315#[doc = "`write(|w| ..)` method takes [genctrl::W](W) writer structure"]
316impl crate::Writable for GENCTRL_SPEC {
317    type Writer = W;
318    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
319    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
320}
321#[doc = "`reset()` method sets GENCTRL%s to value 0"]
322impl crate::Resettable for GENCTRL_SPEC {
323    const RESET_VALUE: Self::Ux = 0;
324}
atsaml21g18a/gclk/genctrl.rs

atsaml21g18a/gclk/
genctrl.rs
