atsaml21e18b/sercom0/i2cm/
ctrla.rs

1#[doc = "Register `CTRLA` reader"]
2pub struct R(crate::R<CTRLA_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRLA_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRLA_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRLA_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRLA` writer"]
17pub struct W(crate::W<CTRLA_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRLA_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRLA_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRLA_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SWRST` reader - Software Reset"]
38pub type SWRST_R = crate::BitReader<bool>;
39#[doc = "Field `SWRST` writer - Software Reset"]
40pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>;
41#[doc = "Field `ENABLE` reader - Enable"]
42pub type ENABLE_R = crate::BitReader<bool>;
43#[doc = "Field `ENABLE` writer - Enable"]
44pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>;
45#[doc = "Field `MODE` reader - Operating Mode"]
46pub type MODE_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `MODE` writer - Operating Mode"]
48pub type MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 3, O>;
49#[doc = "Field `RUNSTDBY` reader - Run in Standby"]
50pub type RUNSTDBY_R = crate::BitReader<bool>;
51#[doc = "Field `RUNSTDBY` writer - Run in Standby"]
52pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>;
53#[doc = "Field `PINOUT` reader - Pin Usage"]
54pub type PINOUT_R = crate::BitReader<bool>;
55#[doc = "Field `PINOUT` writer - Pin Usage"]
56pub type PINOUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>;
57#[doc = "Field `SDAHOLD` reader - SDA Hold Time"]
58pub type SDAHOLD_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `SDAHOLD` writer - SDA Hold Time"]
60pub type SDAHOLD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 2, O>;
61#[doc = "Field `MEXTTOEN` reader - Master SCL Low Extend Timeout"]
62pub type MEXTTOEN_R = crate::BitReader<bool>;
63#[doc = "Field `MEXTTOEN` writer - Master SCL Low Extend Timeout"]
64pub type MEXTTOEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>;
65#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"]
66pub type SEXTTOEN_R = crate::BitReader<bool>;
67#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"]
68pub type SEXTTOEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>;
69#[doc = "Field `SPEED` reader - Transfer Speed"]
70pub type SPEED_R = crate::FieldReader<u8, u8>;
71#[doc = "Field `SPEED` writer - Transfer Speed"]
72pub type SPEED_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 2, O>;
73#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"]
74pub type SCLSM_R = crate::BitReader<bool>;
75#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"]
76pub type SCLSM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>;
77#[doc = "Field `INACTOUT` reader - Inactive Time-Out"]
78pub type INACTOUT_R = crate::FieldReader<u8, u8>;
79#[doc = "Field `INACTOUT` writer - Inactive Time-Out"]
80pub type INACTOUT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 2, O>;
81#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"]
82pub type LOWTOUTEN_R = crate::BitReader<bool>;
83#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"]
84pub type LOWTOUTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>;
85impl R {
86    #[doc = "Bit 0 - Software Reset"]
87    #[inline(always)]
88    pub fn swrst(&self) -> SWRST_R {
89        SWRST_R::new((self.bits & 1) != 0)
90    }
91    #[doc = "Bit 1 - Enable"]
92    #[inline(always)]
93    pub fn enable(&self) -> ENABLE_R {
94        ENABLE_R::new(((self.bits >> 1) & 1) != 0)
95    }
96    #[doc = "Bits 2:4 - Operating Mode"]
97    #[inline(always)]
98    pub fn mode(&self) -> MODE_R {
99        MODE_R::new(((self.bits >> 2) & 7) as u8)
100    }
101    #[doc = "Bit 7 - Run in Standby"]
102    #[inline(always)]
103    pub fn runstdby(&self) -> RUNSTDBY_R {
104        RUNSTDBY_R::new(((self.bits >> 7) & 1) != 0)
105    }
106    #[doc = "Bit 16 - Pin Usage"]
107    #[inline(always)]
108    pub fn pinout(&self) -> PINOUT_R {
109        PINOUT_R::new(((self.bits >> 16) & 1) != 0)
110    }
111    #[doc = "Bits 20:21 - SDA Hold Time"]
112    #[inline(always)]
113    pub fn sdahold(&self) -> SDAHOLD_R {
114        SDAHOLD_R::new(((self.bits >> 20) & 3) as u8)
115    }
116    #[doc = "Bit 22 - Master SCL Low Extend Timeout"]
117    #[inline(always)]
118    pub fn mexttoen(&self) -> MEXTTOEN_R {
119        MEXTTOEN_R::new(((self.bits >> 22) & 1) != 0)
120    }
121    #[doc = "Bit 23 - Slave SCL Low Extend Timeout"]
122    #[inline(always)]
123    pub fn sexttoen(&self) -> SEXTTOEN_R {
124        SEXTTOEN_R::new(((self.bits >> 23) & 1) != 0)
125    }
126    #[doc = "Bits 24:25 - Transfer Speed"]
127    #[inline(always)]
128    pub fn speed(&self) -> SPEED_R {
129        SPEED_R::new(((self.bits >> 24) & 3) as u8)
130    }
131    #[doc = "Bit 27 - SCL Clock Stretch Mode"]
132    #[inline(always)]
133    pub fn sclsm(&self) -> SCLSM_R {
134        SCLSM_R::new(((self.bits >> 27) & 1) != 0)
135    }
136    #[doc = "Bits 28:29 - Inactive Time-Out"]
137    #[inline(always)]
138    pub fn inactout(&self) -> INACTOUT_R {
139        INACTOUT_R::new(((self.bits >> 28) & 3) as u8)
140    }
141    #[doc = "Bit 30 - SCL Low Timeout Enable"]
142    #[inline(always)]
143    pub fn lowtouten(&self) -> LOWTOUTEN_R {
144        LOWTOUTEN_R::new(((self.bits >> 30) & 1) != 0)
145    }
146}
147impl W {
148    #[doc = "Bit 0 - Software Reset"]
149    #[inline(always)]
150    #[must_use]
151    pub fn swrst(&mut self) -> SWRST_W<0> {
152        SWRST_W::new(self)
153    }
154    #[doc = "Bit 1 - Enable"]
155    #[inline(always)]
156    #[must_use]
157    pub fn enable(&mut self) -> ENABLE_W<1> {
158        ENABLE_W::new(self)
159    }
160    #[doc = "Bits 2:4 - Operating Mode"]
161    #[inline(always)]
162    #[must_use]
163    pub fn mode(&mut self) -> MODE_W<2> {
164        MODE_W::new(self)
165    }
166    #[doc = "Bit 7 - Run in Standby"]
167    #[inline(always)]
168    #[must_use]
169    pub fn runstdby(&mut self) -> RUNSTDBY_W<7> {
170        RUNSTDBY_W::new(self)
171    }
172    #[doc = "Bit 16 - Pin Usage"]
173    #[inline(always)]
174    #[must_use]
175    pub fn pinout(&mut self) -> PINOUT_W<16> {
176        PINOUT_W::new(self)
177    }
178    #[doc = "Bits 20:21 - SDA Hold Time"]
179    #[inline(always)]
180    #[must_use]
181    pub fn sdahold(&mut self) -> SDAHOLD_W<20> {
182        SDAHOLD_W::new(self)
183    }
184    #[doc = "Bit 22 - Master SCL Low Extend Timeout"]
185    #[inline(always)]
186    #[must_use]
187    pub fn mexttoen(&mut self) -> MEXTTOEN_W<22> {
188        MEXTTOEN_W::new(self)
189    }
190    #[doc = "Bit 23 - Slave SCL Low Extend Timeout"]
191    #[inline(always)]
192    #[must_use]
193    pub fn sexttoen(&mut self) -> SEXTTOEN_W<23> {
194        SEXTTOEN_W::new(self)
195    }
196    #[doc = "Bits 24:25 - Transfer Speed"]
197    #[inline(always)]
198    #[must_use]
199    pub fn speed(&mut self) -> SPEED_W<24> {
200        SPEED_W::new(self)
201    }
202    #[doc = "Bit 27 - SCL Clock Stretch Mode"]
203    #[inline(always)]
204    #[must_use]
205    pub fn sclsm(&mut self) -> SCLSM_W<27> {
206        SCLSM_W::new(self)
207    }
208    #[doc = "Bits 28:29 - Inactive Time-Out"]
209    #[inline(always)]
210    #[must_use]
211    pub fn inactout(&mut self) -> INACTOUT_W<28> {
212        INACTOUT_W::new(self)
213    }
214    #[doc = "Bit 30 - SCL Low Timeout Enable"]
215    #[inline(always)]
216    #[must_use]
217    pub fn lowtouten(&mut self) -> LOWTOUTEN_W<30> {
218        LOWTOUTEN_W::new(self)
219    }
220    #[doc = "Writes raw bits to the register."]
221    #[inline(always)]
222    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
223        self.0.bits(bits);
224        self
225    }
226}
227#[doc = "I2CM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"]
228pub struct CTRLA_SPEC;
229impl crate::RegisterSpec for CTRLA_SPEC {
230    type Ux = u32;
231}
232#[doc = "`read()` method returns [ctrla::R](R) reader structure"]
233impl crate::Readable for CTRLA_SPEC {
234    type Reader = R;
235}
236#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"]
237impl crate::Writable for CTRLA_SPEC {
238    type Writer = W;
239    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
240    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
241}
242#[doc = "`reset()` method sets CTRLA to value 0"]
243impl crate::Resettable for CTRLA_SPEC {
244    const RESET_VALUE: Self::Ux = 0;
245}
atsaml21e18b/sercom0/i2cm/ctrla.rs

atsaml21e18b/sercom0/i2cm/
ctrla.rs
