atsaml21e18a/pm/
stdbycfg.rs

1#[doc = "Register `STDBYCFG` reader"]
2pub struct R(crate::R<STDBYCFG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<STDBYCFG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<STDBYCFG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<STDBYCFG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `STDBYCFG` writer"]
17pub struct W(crate::W<STDBYCFG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<STDBYCFG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<STDBYCFG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<STDBYCFG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PDCFG` reader - Power Domain Configuration"]
38pub type PDCFG_R = crate::FieldReader<u8, PDCFGSELECT_A>;
39#[doc = "Power Domain Configuration\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum PDCFGSELECT_A {
43    #[doc = "0: All power domains switching is handled by hardware."]
44    DEFAULT = 0,
45    #[doc = "1: PD0 is forced ACTIVE. PD1 and PD2 power domains switching is handled by hardware."]
46    PD0 = 1,
47    #[doc = "2: PD0 and PD1 are forced ACTIVE. PD2 power domain switching is handled by hardware."]
48    PD01 = 2,
49    #[doc = "3: All power domains are forced ACTIVE."]
50    PD012 = 3,
51}
52impl From<PDCFGSELECT_A> for u8 {
53    #[inline(always)]
54    fn from(variant: PDCFGSELECT_A) -> Self {
55        variant as _
56    }
57}
58impl PDCFG_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> PDCFGSELECT_A {
62        match self.bits {
63            0 => PDCFGSELECT_A::DEFAULT,
64            1 => PDCFGSELECT_A::PD0,
65            2 => PDCFGSELECT_A::PD01,
66            3 => PDCFGSELECT_A::PD012,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `DEFAULT`"]
71    #[inline(always)]
72    pub fn is_default(&self) -> bool {
73        *self == PDCFGSELECT_A::DEFAULT
74    }
75    #[doc = "Checks if the value of the field is `PD0`"]
76    #[inline(always)]
77    pub fn is_pd0(&self) -> bool {
78        *self == PDCFGSELECT_A::PD0
79    }
80    #[doc = "Checks if the value of the field is `PD01`"]
81    #[inline(always)]
82    pub fn is_pd01(&self) -> bool {
83        *self == PDCFGSELECT_A::PD01
84    }
85    #[doc = "Checks if the value of the field is `PD012`"]
86    #[inline(always)]
87    pub fn is_pd012(&self) -> bool {
88        *self == PDCFGSELECT_A::PD012
89    }
90}
91#[doc = "Field `PDCFG` writer - Power Domain Configuration"]
92pub type PDCFG_W<'a, const O: u8> =
93    crate::FieldWriterSafe<'a, u16, STDBYCFG_SPEC, u8, PDCFGSELECT_A, 2, O>;
94impl<'a, const O: u8> PDCFG_W<'a, O> {
95    #[doc = "All power domains switching is handled by hardware."]
96    #[inline(always)]
97    pub fn default(self) -> &'a mut W {
98        self.variant(PDCFGSELECT_A::DEFAULT)
99    }
100    #[doc = "PD0 is forced ACTIVE. PD1 and PD2 power domains switching is handled by hardware."]
101    #[inline(always)]
102    pub fn pd0(self) -> &'a mut W {
103        self.variant(PDCFGSELECT_A::PD0)
104    }
105    #[doc = "PD0 and PD1 are forced ACTIVE. PD2 power domain switching is handled by hardware."]
106    #[inline(always)]
107    pub fn pd01(self) -> &'a mut W {
108        self.variant(PDCFGSELECT_A::PD01)
109    }
110    #[doc = "All power domains are forced ACTIVE."]
111    #[inline(always)]
112    pub fn pd012(self) -> &'a mut W {
113        self.variant(PDCFGSELECT_A::PD012)
114    }
115}
116#[doc = "Field `DPGPD0` reader - Dynamic Power Gating for PD0"]
117pub type DPGPD0_R = crate::BitReader<bool>;
118#[doc = "Field `DPGPD0` writer - Dynamic Power Gating for PD0"]
119pub type DPGPD0_W<'a, const O: u8> = crate::BitWriter<'a, u16, STDBYCFG_SPEC, bool, O>;
120#[doc = "Field `DPGPD1` reader - Dynamic Power Gating for PD1"]
121pub type DPGPD1_R = crate::BitReader<bool>;
122#[doc = "Field `DPGPD1` writer - Dynamic Power Gating for PD1"]
123pub type DPGPD1_W<'a, const O: u8> = crate::BitWriter<'a, u16, STDBYCFG_SPEC, bool, O>;
124#[doc = "Field `AVREGSD` reader - Automatic VREG Switching Disable"]
125pub type AVREGSD_R = crate::BitReader<bool>;
126#[doc = "Field `AVREGSD` writer - Automatic VREG Switching Disable"]
127pub type AVREGSD_W<'a, const O: u8> = crate::BitWriter<'a, u16, STDBYCFG_SPEC, bool, O>;
128#[doc = "Field `LINKPD` reader - Linked Power Domain"]
129pub type LINKPD_R = crate::FieldReader<u8, LINKPDSELECT_A>;
130#[doc = "Linked Power Domain\n\nValue on reset: 0"]
131#[derive(Clone, Copy, Debug, PartialEq, Eq)]
132#[repr(u8)]
133pub enum LINKPDSELECT_A {
134    #[doc = "0: Power domains are not linked"]
135    DEFAULT = 0,
136    #[doc = "1: PD0 and PD1 power domains are linked"]
137    PD01 = 1,
138    #[doc = "2: PD1 and PD2 power domains are linked"]
139    PD12 = 2,
140    #[doc = "3: All power domains are linked"]
141    PD012 = 3,
142}
143impl From<LINKPDSELECT_A> for u8 {
144    #[inline(always)]
145    fn from(variant: LINKPDSELECT_A) -> Self {
146        variant as _
147    }
148}
149impl LINKPD_R {
150    #[doc = "Get enumerated values variant"]
151    #[inline(always)]
152    pub fn variant(&self) -> LINKPDSELECT_A {
153        match self.bits {
154            0 => LINKPDSELECT_A::DEFAULT,
155            1 => LINKPDSELECT_A::PD01,
156            2 => LINKPDSELECT_A::PD12,
157            3 => LINKPDSELECT_A::PD012,
158            _ => unreachable!(),
159        }
160    }
161    #[doc = "Checks if the value of the field is `DEFAULT`"]
162    #[inline(always)]
163    pub fn is_default(&self) -> bool {
164        *self == LINKPDSELECT_A::DEFAULT
165    }
166    #[doc = "Checks if the value of the field is `PD01`"]
167    #[inline(always)]
168    pub fn is_pd01(&self) -> bool {
169        *self == LINKPDSELECT_A::PD01
170    }
171    #[doc = "Checks if the value of the field is `PD12`"]
172    #[inline(always)]
173    pub fn is_pd12(&self) -> bool {
174        *self == LINKPDSELECT_A::PD12
175    }
176    #[doc = "Checks if the value of the field is `PD012`"]
177    #[inline(always)]
178    pub fn is_pd012(&self) -> bool {
179        *self == LINKPDSELECT_A::PD012
180    }
181}
182#[doc = "Field `LINKPD` writer - Linked Power Domain"]
183pub type LINKPD_W<'a, const O: u8> =
184    crate::FieldWriterSafe<'a, u16, STDBYCFG_SPEC, u8, LINKPDSELECT_A, 2, O>;
185impl<'a, const O: u8> LINKPD_W<'a, O> {
186    #[doc = "Power domains are not linked"]
187    #[inline(always)]
188    pub fn default(self) -> &'a mut W {
189        self.variant(LINKPDSELECT_A::DEFAULT)
190    }
191    #[doc = "PD0 and PD1 power domains are linked"]
192    #[inline(always)]
193    pub fn pd01(self) -> &'a mut W {
194        self.variant(LINKPDSELECT_A::PD01)
195    }
196    #[doc = "PD1 and PD2 power domains are linked"]
197    #[inline(always)]
198    pub fn pd12(self) -> &'a mut W {
199        self.variant(LINKPDSELECT_A::PD12)
200    }
201    #[doc = "All power domains are linked"]
202    #[inline(always)]
203    pub fn pd012(self) -> &'a mut W {
204        self.variant(LINKPDSELECT_A::PD012)
205    }
206}
207#[doc = "Field `BBIASHS` reader - Back Bias for HMCRAMCHS"]
208pub type BBIASHS_R = crate::FieldReader<u8, u8>;
209#[doc = "Field `BBIASHS` writer - Back Bias for HMCRAMCHS"]
210pub type BBIASHS_W<'a, const O: u8> = crate::FieldWriter<'a, u16, STDBYCFG_SPEC, u8, u8, 2, O>;
211#[doc = "Field `BBIASLP` reader - Back Bias for HMCRAMCLP"]
212pub type BBIASLP_R = crate::FieldReader<u8, u8>;
213#[doc = "Field `BBIASLP` writer - Back Bias for HMCRAMCLP"]
214pub type BBIASLP_W<'a, const O: u8> = crate::FieldWriter<'a, u16, STDBYCFG_SPEC, u8, u8, 2, O>;
215#[doc = "Field `BBIASPP` reader - Back Bias for PicoPram"]
216pub type BBIASPP_R = crate::FieldReader<u8, u8>;
217#[doc = "Field `BBIASPP` writer - Back Bias for PicoPram"]
218pub type BBIASPP_W<'a, const O: u8> = crate::FieldWriter<'a, u16, STDBYCFG_SPEC, u8, u8, 2, O>;
219impl R {
220    #[doc = "Bits 0:1 - Power Domain Configuration"]
221    #[inline(always)]
222    pub fn pdcfg(&self) -> PDCFG_R {
223        PDCFG_R::new((self.bits & 3) as u8)
224    }
225    #[doc = "Bit 4 - Dynamic Power Gating for PD0"]
226    #[inline(always)]
227    pub fn dpgpd0(&self) -> DPGPD0_R {
228        DPGPD0_R::new(((self.bits >> 4) & 1) != 0)
229    }
230    #[doc = "Bit 5 - Dynamic Power Gating for PD1"]
231    #[inline(always)]
232    pub fn dpgpd1(&self) -> DPGPD1_R {
233        DPGPD1_R::new(((self.bits >> 5) & 1) != 0)
234    }
235    #[doc = "Bit 7 - Automatic VREG Switching Disable"]
236    #[inline(always)]
237    pub fn avregsd(&self) -> AVREGSD_R {
238        AVREGSD_R::new(((self.bits >> 7) & 1) != 0)
239    }
240    #[doc = "Bits 8:9 - Linked Power Domain"]
241    #[inline(always)]
242    pub fn linkpd(&self) -> LINKPD_R {
243        LINKPD_R::new(((self.bits >> 8) & 3) as u8)
244    }
245    #[doc = "Bits 10:11 - Back Bias for HMCRAMCHS"]
246    #[inline(always)]
247    pub fn bbiashs(&self) -> BBIASHS_R {
248        BBIASHS_R::new(((self.bits >> 10) & 3) as u8)
249    }
250    #[doc = "Bits 12:13 - Back Bias for HMCRAMCLP"]
251    #[inline(always)]
252    pub fn bbiaslp(&self) -> BBIASLP_R {
253        BBIASLP_R::new(((self.bits >> 12) & 3) as u8)
254    }
255    #[doc = "Bits 14:15 - Back Bias for PicoPram"]
256    #[inline(always)]
257    pub fn bbiaspp(&self) -> BBIASPP_R {
258        BBIASPP_R::new(((self.bits >> 14) & 3) as u8)
259    }
260}
261impl W {
262    #[doc = "Bits 0:1 - Power Domain Configuration"]
263    #[inline(always)]
264    #[must_use]
265    pub fn pdcfg(&mut self) -> PDCFG_W<0> {
266        PDCFG_W::new(self)
267    }
268    #[doc = "Bit 4 - Dynamic Power Gating for PD0"]
269    #[inline(always)]
270    #[must_use]
271    pub fn dpgpd0(&mut self) -> DPGPD0_W<4> {
272        DPGPD0_W::new(self)
273    }
274    #[doc = "Bit 5 - Dynamic Power Gating for PD1"]
275    #[inline(always)]
276    #[must_use]
277    pub fn dpgpd1(&mut self) -> DPGPD1_W<5> {
278        DPGPD1_W::new(self)
279    }
280    #[doc = "Bit 7 - Automatic VREG Switching Disable"]
281    #[inline(always)]
282    #[must_use]
283    pub fn avregsd(&mut self) -> AVREGSD_W<7> {
284        AVREGSD_W::new(self)
285    }
286    #[doc = "Bits 8:9 - Linked Power Domain"]
287    #[inline(always)]
288    #[must_use]
289    pub fn linkpd(&mut self) -> LINKPD_W<8> {
290        LINKPD_W::new(self)
291    }
292    #[doc = "Bits 10:11 - Back Bias for HMCRAMCHS"]
293    #[inline(always)]
294    #[must_use]
295    pub fn bbiashs(&mut self) -> BBIASHS_W<10> {
296        BBIASHS_W::new(self)
297    }
298    #[doc = "Bits 12:13 - Back Bias for HMCRAMCLP"]
299    #[inline(always)]
300    #[must_use]
301    pub fn bbiaslp(&mut self) -> BBIASLP_W<12> {
302        BBIASLP_W::new(self)
303    }
304    #[doc = "Bits 14:15 - Back Bias for PicoPram"]
305    #[inline(always)]
306    #[must_use]
307    pub fn bbiaspp(&mut self) -> BBIASPP_W<14> {
308        BBIASPP_W::new(self)
309    }
310    #[doc = "Writes raw bits to the register."]
311    #[inline(always)]
312    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
313        self.0.bits(bits);
314        self
315    }
316}
317#[doc = "Standby Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stdbycfg](index.html) module"]
318pub struct STDBYCFG_SPEC;
319impl crate::RegisterSpec for STDBYCFG_SPEC {
320    type Ux = u16;
321}
322#[doc = "`read()` method returns [stdbycfg::R](R) reader structure"]
323impl crate::Readable for STDBYCFG_SPEC {
324    type Reader = R;
325}
326#[doc = "`write(|w| ..)` method takes [stdbycfg::W](W) writer structure"]
327impl crate::Writable for STDBYCFG_SPEC {
328    type Writer = W;
329    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
330    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
331}
332#[doc = "`reset()` method sets STDBYCFG to value 0"]
333impl crate::Resettable for STDBYCFG_SPEC {
334    const RESET_VALUE: Self::Ux = 0;
335}
atsaml21e18a/pm/stdbycfg.rs

atsaml21e18a/pm/
stdbycfg.rs
