[][src]Type Definition atsame70q19b::usbhs::usbhs_deveptidr_iso_mode::W

type W = W<u32, USBHS_DEVEPTIDR_ISO_MODE>;

Writer for register USBHS_DEVEPTIDR_ISO_MODE[%s]

Implementations

impl W[src]

pub fn txinec(&mut self) -> TXINEC_W[src]

Bit 0 - Transmitted IN Interrupt Clear

pub fn rxoutec(&mut self) -> RXOUTEC_W[src]

Bit 1 - Received OUT Data Interrupt Clear

pub fn underfec(&mut self) -> UNDERFEC_W[src]

Bit 2 - Underflow Interrupt Clear

pub fn hbisoinerrec(&mut self) -> HBISOINERREC_W[src]

Bit 3 - High Bandwidth Isochronous IN Underflow Error Interrupt Clear

pub fn hbisoflushec(&mut self) -> HBISOFLUSHEC_W[src]

Bit 4 - High Bandwidth Isochronous IN Flush Interrupt Clear

pub fn overfec(&mut self) -> OVERFEC_W[src]

Bit 5 - Overflow Interrupt Clear

pub fn shortpacketec(&mut self) -> SHORTPACKETEC_W[src]

Bit 7 - Shortpacket Interrupt Clear

pub fn mdataec(&mut self) -> MDATAEC_W[src]

Bit 8 - MData Interrupt Clear

pub fn dataxec(&mut self) -> DATAXEC_W[src]

Bit 9 - DataX Interrupt Clear

pub fn errortransec(&mut self) -> ERRORTRANSEC_W[src]

Bit 10 - Transaction Error Interrupt Clear

pub fn nbusybkec(&mut self) -> NBUSYBKEC_W[src]

Bit 12 - Number of Busy Banks Interrupt Clear

pub fn fifoconc(&mut self) -> FIFOCONC_W[src]

Bit 14 - FIFO Control Clear

pub fn epdishdmac(&mut self) -> EPDISHDMAC_W[src]

Bit 16 - Endpoint Interrupts Disable HDMA Request Clear