Struct atsame70n21b::pwm0::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 45 fields
    pub clk: CLK,
    pub ena: ENA,
    pub dis: DIS,
    pub sr: SR,
    pub ier1: IER1,
    pub idr1: IDR1,
    pub imr1: IMR1,
    pub isr1: ISR1,
    pub scm: SCM,
    pub dmar: DMAR,
    pub scuc: SCUC,
    pub scup: SCUP,
    pub scupupd: SCUPUPD,
    pub ier2: IER2,
    pub idr2: IDR2,
    pub imr2: IMR2,
    pub isr2: ISR2,
    pub oov: OOV,
    pub os: OS,
    pub oss: OSS,
    pub osc: OSC,
    pub ossupd: OSSUPD,
    pub oscupd: OSCUPD,
    pub fmr: FMR,
    pub fsr: FSR,
    pub fcr: FCR,
    pub fpv1: FPV1,
    pub fpe: FPE,
    pub elmr: [ELMR; 2],
    pub sspr: SSPR,
    pub sspup: SSPUP,
    pub smmr: SMMR,
    pub fpv2: FPV2,
    pub wpcr: WPCR,
    pub wpsr: WPSR,
    pub pwm_cmp: [PWM_CMP; 8],
    pub pwm_ch_num: [PWM_CH_NUM; 4],
    pub cmupd0: CMUPD0,
    pub cmupd1: CMUPD1,
    pub etrg1: ETRG1,
    pub lebr1: LEBR1,
    pub cmupd2: CMUPD2,
    pub etrg2: ETRG2,
    pub lebr2: LEBR2,
    pub cmupd3: CMUPD3,
    /* private fields */

}
Expand description

Register block

Fields§

§clk: CLK

0x00 - PWM Clock Register

§ena: ENA

0x04 - PWM Enable Register

§dis: DIS

0x08 - PWM Disable Register

§sr: SR

0x0c - PWM Status Register

§ier1: IER1

0x10 - PWM Interrupt Enable Register 1

§idr1: IDR1

0x14 - PWM Interrupt Disable Register 1

§imr1: IMR1

0x18 - PWM Interrupt Mask Register 1

§isr1: ISR1

0x1c - PWM Interrupt Status Register 1

§scm: SCM

0x20 - PWM Sync Channels Mode Register

§dmar: DMAR

0x24 - PWM DMA Register

§scuc: SCUC

0x28 - PWM Sync Channels Update Control Register

§scup: SCUP

0x2c - PWM Sync Channels Update Period Register

§scupupd: SCUPUPD

0x30 - PWM Sync Channels Update Period Update Register

§ier2: IER2

0x34 - PWM Interrupt Enable Register 2

§idr2: IDR2

0x38 - PWM Interrupt Disable Register 2

§imr2: IMR2

0x3c - PWM Interrupt Mask Register 2

§isr2: ISR2

0x40 - PWM Interrupt Status Register 2

§oov: OOV

0x44 - PWM Output Override Value Register

§os: OS

0x48 - PWM Output Selection Register

§oss: OSS

0x4c - PWM Output Selection Set Register

§osc: OSC

0x50 - PWM Output Selection Clear Register

§ossupd: OSSUPD

0x54 - PWM Output Selection Set Update Register

§oscupd: OSCUPD

0x58 - PWM Output Selection Clear Update Register

§fmr: FMR

0x5c - PWM Fault Mode Register

§fsr: FSR

0x60 - PWM Fault Status Register

§fcr: FCR

0x64 - PWM Fault Clear Register

§fpv1: FPV1

0x68 - PWM Fault Protection Value Register 1

§fpe: FPE

0x6c - PWM Fault Protection Enable Register

§elmr: [ELMR; 2]

0x7c..0x84 - PWM Event Line 0 Mode Register 0

§sspr: SSPR

0xa0 - PWM Spread Spectrum Register

§sspup: SSPUP

0xa4 - PWM Spread Spectrum Update Register

§smmr: SMMR

0xb0 - PWM Stepper Motor Mode Register

§fpv2: FPV2

0xc0 - PWM Fault Protection Value 2 Register

§wpcr: WPCR

0xe4 - PWM Write Protection Control Register

§wpsr: WPSR

0xe8 - PWM Write Protection Status Register

§pwm_cmp: [PWM_CMP; 8]

0x130..0x1b0 - PWM Comparison 0 Value Register

§pwm_ch_num: [PWM_CH_NUM; 4]

0x200..0x280 - PWM Channel Mode Register

§cmupd0: CMUPD0

0x400 - PWM Channel Mode Update Register (ch_num = 0)

§cmupd1: CMUPD1

0x420 - PWM Channel Mode Update Register (ch_num = 1)

§etrg1: ETRG1

0x42c - PWM External Trigger Register (trg_num = 1)

§lebr1: LEBR1

0x430 - PWM Leading-Edge Blanking Register (trg_num = 1)

§cmupd2: CMUPD2

0x440 - PWM Channel Mode Update Register (ch_num = 2)

§etrg2: ETRG2

0x44c - PWM External Trigger Register (trg_num = 2)

§lebr2: LEBR2

0x450 - PWM Leading-Edge Blanking Register (trg_num = 2)

§cmupd3: CMUPD3

0x460 - PWM Channel Mode Update Register (ch_num = 3)

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