atsame70n21/xdmac/xdmac_chid/
xdmac_cc.rs

1#[doc = "Register `XDMAC_CC` reader"]
2pub struct R(crate::R<XDMAC_CC_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<XDMAC_CC_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<XDMAC_CC_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<XDMAC_CC_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `XDMAC_CC` writer"]
17pub struct W(crate::W<XDMAC_CC_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<XDMAC_CC_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<XDMAC_CC_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<XDMAC_CC_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Channel x Transfer Type\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum TYPE_A {
40    #[doc = "0: Self triggered mode (Memory to Memory Transfer)."]
41    MEM_TRAN = 0,
42    #[doc = "1: Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer)."]
43    PER_TRAN = 1,
44}
45impl From<TYPE_A> for bool {
46    #[inline(always)]
47    fn from(variant: TYPE_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `TYPE` reader - Channel x Transfer Type"]
52pub struct TYPE_R(crate::FieldReader<bool, TYPE_A>);
53impl TYPE_R {
54    #[inline(always)]
55    pub(crate) fn new(bits: bool) -> Self {
56        TYPE_R(crate::FieldReader::new(bits))
57    }
58    #[doc = r"Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> TYPE_A {
61        match self.bits {
62            false => TYPE_A::MEM_TRAN,
63            true => TYPE_A::PER_TRAN,
64        }
65    }
66    #[doc = "Checks if the value of the field is `MEM_TRAN`"]
67    #[inline(always)]
68    pub fn is_mem_tran(&self) -> bool {
69        **self == TYPE_A::MEM_TRAN
70    }
71    #[doc = "Checks if the value of the field is `PER_TRAN`"]
72    #[inline(always)]
73    pub fn is_per_tran(&self) -> bool {
74        **self == TYPE_A::PER_TRAN
75    }
76}
77impl core::ops::Deref for TYPE_R {
78    type Target = crate::FieldReader<bool, TYPE_A>;
79    #[inline(always)]
80    fn deref(&self) -> &Self::Target {
81        &self.0
82    }
83}
84#[doc = "Field `TYPE` writer - Channel x Transfer Type"]
85pub struct TYPE_W<'a> {
86    w: &'a mut W,
87}
88impl<'a> TYPE_W<'a> {
89    #[doc = r"Writes `variant` to the field"]
90    #[inline(always)]
91    pub fn variant(self, variant: TYPE_A) -> &'a mut W {
92        self.bit(variant.into())
93    }
94    #[doc = "Self triggered mode (Memory to Memory Transfer)."]
95    #[inline(always)]
96    pub fn mem_tran(self) -> &'a mut W {
97        self.variant(TYPE_A::MEM_TRAN)
98    }
99    #[doc = "Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer)."]
100    #[inline(always)]
101    pub fn per_tran(self) -> &'a mut W {
102        self.variant(TYPE_A::PER_TRAN)
103    }
104    #[doc = r"Sets the field bit"]
105    #[inline(always)]
106    pub fn set_bit(self) -> &'a mut W {
107        self.bit(true)
108    }
109    #[doc = r"Clears the field bit"]
110    #[inline(always)]
111    pub fn clear_bit(self) -> &'a mut W {
112        self.bit(false)
113    }
114    #[doc = r"Writes raw bits to the field"]
115    #[inline(always)]
116    pub fn bit(self, value: bool) -> &'a mut W {
117        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
118        self.w
119    }
120}
121#[doc = "Channel x Memory Burst Size\n\nValue on reset: 0"]
122#[derive(Clone, Copy, Debug, PartialEq)]
123#[repr(u8)]
124pub enum MBSIZE_A {
125    #[doc = "0: The memory burst size is set to one."]
126    SINGLE = 0,
127    #[doc = "1: The memory burst size is set to four."]
128    FOUR = 1,
129    #[doc = "2: The memory burst size is set to eight."]
130    EIGHT = 2,
131    #[doc = "3: The memory burst size is set to sixteen."]
132    SIXTEEN = 3,
133}
134impl From<MBSIZE_A> for u8 {
135    #[inline(always)]
136    fn from(variant: MBSIZE_A) -> Self {
137        variant as _
138    }
139}
140#[doc = "Field `MBSIZE` reader - Channel x Memory Burst Size"]
141pub struct MBSIZE_R(crate::FieldReader<u8, MBSIZE_A>);
142impl MBSIZE_R {
143    #[inline(always)]
144    pub(crate) fn new(bits: u8) -> Self {
145        MBSIZE_R(crate::FieldReader::new(bits))
146    }
147    #[doc = r"Get enumerated values variant"]
148    #[inline(always)]
149    pub fn variant(&self) -> MBSIZE_A {
150        match self.bits {
151            0 => MBSIZE_A::SINGLE,
152            1 => MBSIZE_A::FOUR,
153            2 => MBSIZE_A::EIGHT,
154            3 => MBSIZE_A::SIXTEEN,
155            _ => unreachable!(),
156        }
157    }
158    #[doc = "Checks if the value of the field is `SINGLE`"]
159    #[inline(always)]
160    pub fn is_single(&self) -> bool {
161        **self == MBSIZE_A::SINGLE
162    }
163    #[doc = "Checks if the value of the field is `FOUR`"]
164    #[inline(always)]
165    pub fn is_four(&self) -> bool {
166        **self == MBSIZE_A::FOUR
167    }
168    #[doc = "Checks if the value of the field is `EIGHT`"]
169    #[inline(always)]
170    pub fn is_eight(&self) -> bool {
171        **self == MBSIZE_A::EIGHT
172    }
173    #[doc = "Checks if the value of the field is `SIXTEEN`"]
174    #[inline(always)]
175    pub fn is_sixteen(&self) -> bool {
176        **self == MBSIZE_A::SIXTEEN
177    }
178}
179impl core::ops::Deref for MBSIZE_R {
180    type Target = crate::FieldReader<u8, MBSIZE_A>;
181    #[inline(always)]
182    fn deref(&self) -> &Self::Target {
183        &self.0
184    }
185}
186#[doc = "Field `MBSIZE` writer - Channel x Memory Burst Size"]
187pub struct MBSIZE_W<'a> {
188    w: &'a mut W,
189}
190impl<'a> MBSIZE_W<'a> {
191    #[doc = r"Writes `variant` to the field"]
192    #[inline(always)]
193    pub fn variant(self, variant: MBSIZE_A) -> &'a mut W {
194        self.bits(variant.into())
195    }
196    #[doc = "The memory burst size is set to one."]
197    #[inline(always)]
198    pub fn single(self) -> &'a mut W {
199        self.variant(MBSIZE_A::SINGLE)
200    }
201    #[doc = "The memory burst size is set to four."]
202    #[inline(always)]
203    pub fn four(self) -> &'a mut W {
204        self.variant(MBSIZE_A::FOUR)
205    }
206    #[doc = "The memory burst size is set to eight."]
207    #[inline(always)]
208    pub fn eight(self) -> &'a mut W {
209        self.variant(MBSIZE_A::EIGHT)
210    }
211    #[doc = "The memory burst size is set to sixteen."]
212    #[inline(always)]
213    pub fn sixteen(self) -> &'a mut W {
214        self.variant(MBSIZE_A::SIXTEEN)
215    }
216    #[doc = r"Writes raw bits to the field"]
217    #[inline(always)]
218    pub fn bits(self, value: u8) -> &'a mut W {
219        self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u32 & 0x03) << 1);
220        self.w
221    }
222}
223#[doc = "Channel x Synchronization\n\nValue on reset: 0"]
224#[derive(Clone, Copy, Debug, PartialEq)]
225pub enum DSYNC_A {
226    #[doc = "0: Peripheral to Memory transfer."]
227    PER2MEM = 0,
228    #[doc = "1: Memory to Peripheral transfer."]
229    MEM2PER = 1,
230}
231impl From<DSYNC_A> for bool {
232    #[inline(always)]
233    fn from(variant: DSYNC_A) -> Self {
234        variant as u8 != 0
235    }
236}
237#[doc = "Field `DSYNC` reader - Channel x Synchronization"]
238pub struct DSYNC_R(crate::FieldReader<bool, DSYNC_A>);
239impl DSYNC_R {
240    #[inline(always)]
241    pub(crate) fn new(bits: bool) -> Self {
242        DSYNC_R(crate::FieldReader::new(bits))
243    }
244    #[doc = r"Get enumerated values variant"]
245    #[inline(always)]
246    pub fn variant(&self) -> DSYNC_A {
247        match self.bits {
248            false => DSYNC_A::PER2MEM,
249            true => DSYNC_A::MEM2PER,
250        }
251    }
252    #[doc = "Checks if the value of the field is `PER2MEM`"]
253    #[inline(always)]
254    pub fn is_per2mem(&self) -> bool {
255        **self == DSYNC_A::PER2MEM
256    }
257    #[doc = "Checks if the value of the field is `MEM2PER`"]
258    #[inline(always)]
259    pub fn is_mem2per(&self) -> bool {
260        **self == DSYNC_A::MEM2PER
261    }
262}
263impl core::ops::Deref for DSYNC_R {
264    type Target = crate::FieldReader<bool, DSYNC_A>;
265    #[inline(always)]
266    fn deref(&self) -> &Self::Target {
267        &self.0
268    }
269}
270#[doc = "Field `DSYNC` writer - Channel x Synchronization"]
271pub struct DSYNC_W<'a> {
272    w: &'a mut W,
273}
274impl<'a> DSYNC_W<'a> {
275    #[doc = r"Writes `variant` to the field"]
276    #[inline(always)]
277    pub fn variant(self, variant: DSYNC_A) -> &'a mut W {
278        self.bit(variant.into())
279    }
280    #[doc = "Peripheral to Memory transfer."]
281    #[inline(always)]
282    pub fn per2mem(self) -> &'a mut W {
283        self.variant(DSYNC_A::PER2MEM)
284    }
285    #[doc = "Memory to Peripheral transfer."]
286    #[inline(always)]
287    pub fn mem2per(self) -> &'a mut W {
288        self.variant(DSYNC_A::MEM2PER)
289    }
290    #[doc = r"Sets the field bit"]
291    #[inline(always)]
292    pub fn set_bit(self) -> &'a mut W {
293        self.bit(true)
294    }
295    #[doc = r"Clears the field bit"]
296    #[inline(always)]
297    pub fn clear_bit(self) -> &'a mut W {
298        self.bit(false)
299    }
300    #[doc = r"Writes raw bits to the field"]
301    #[inline(always)]
302    pub fn bit(self, value: bool) -> &'a mut W {
303        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
304        self.w
305    }
306}
307#[doc = "Channel x Software Request Trigger\n\nValue on reset: 0"]
308#[derive(Clone, Copy, Debug, PartialEq)]
309pub enum SWREQ_A {
310    #[doc = "0: Hardware request line is connected to the peripheral request line."]
311    HWR_CONNECTED = 0,
312    #[doc = "1: Software request is connected to the peripheral request line."]
313    SWR_CONNECTED = 1,
314}
315impl From<SWREQ_A> for bool {
316    #[inline(always)]
317    fn from(variant: SWREQ_A) -> Self {
318        variant as u8 != 0
319    }
320}
321#[doc = "Field `SWREQ` reader - Channel x Software Request Trigger"]
322pub struct SWREQ_R(crate::FieldReader<bool, SWREQ_A>);
323impl SWREQ_R {
324    #[inline(always)]
325    pub(crate) fn new(bits: bool) -> Self {
326        SWREQ_R(crate::FieldReader::new(bits))
327    }
328    #[doc = r"Get enumerated values variant"]
329    #[inline(always)]
330    pub fn variant(&self) -> SWREQ_A {
331        match self.bits {
332            false => SWREQ_A::HWR_CONNECTED,
333            true => SWREQ_A::SWR_CONNECTED,
334        }
335    }
336    #[doc = "Checks if the value of the field is `HWR_CONNECTED`"]
337    #[inline(always)]
338    pub fn is_hwr_connected(&self) -> bool {
339        **self == SWREQ_A::HWR_CONNECTED
340    }
341    #[doc = "Checks if the value of the field is `SWR_CONNECTED`"]
342    #[inline(always)]
343    pub fn is_swr_connected(&self) -> bool {
344        **self == SWREQ_A::SWR_CONNECTED
345    }
346}
347impl core::ops::Deref for SWREQ_R {
348    type Target = crate::FieldReader<bool, SWREQ_A>;
349    #[inline(always)]
350    fn deref(&self) -> &Self::Target {
351        &self.0
352    }
353}
354#[doc = "Field `SWREQ` writer - Channel x Software Request Trigger"]
355pub struct SWREQ_W<'a> {
356    w: &'a mut W,
357}
358impl<'a> SWREQ_W<'a> {
359    #[doc = r"Writes `variant` to the field"]
360    #[inline(always)]
361    pub fn variant(self, variant: SWREQ_A) -> &'a mut W {
362        self.bit(variant.into())
363    }
364    #[doc = "Hardware request line is connected to the peripheral request line."]
365    #[inline(always)]
366    pub fn hwr_connected(self) -> &'a mut W {
367        self.variant(SWREQ_A::HWR_CONNECTED)
368    }
369    #[doc = "Software request is connected to the peripheral request line."]
370    #[inline(always)]
371    pub fn swr_connected(self) -> &'a mut W {
372        self.variant(SWREQ_A::SWR_CONNECTED)
373    }
374    #[doc = r"Sets the field bit"]
375    #[inline(always)]
376    pub fn set_bit(self) -> &'a mut W {
377        self.bit(true)
378    }
379    #[doc = r"Clears the field bit"]
380    #[inline(always)]
381    pub fn clear_bit(self) -> &'a mut W {
382        self.bit(false)
383    }
384    #[doc = r"Writes raw bits to the field"]
385    #[inline(always)]
386    pub fn bit(self, value: bool) -> &'a mut W {
387        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
388        self.w
389    }
390}
391#[doc = "Channel x Fill Block of memory\n\nValue on reset: 0"]
392#[derive(Clone, Copy, Debug, PartialEq)]
393pub enum MEMSET_A {
394    #[doc = "0: Memset is not activated."]
395    NORMAL_MODE = 0,
396    #[doc = "1: Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis."]
397    HW_MODE = 1,
398}
399impl From<MEMSET_A> for bool {
400    #[inline(always)]
401    fn from(variant: MEMSET_A) -> Self {
402        variant as u8 != 0
403    }
404}
405#[doc = "Field `MEMSET` reader - Channel x Fill Block of memory"]
406pub struct MEMSET_R(crate::FieldReader<bool, MEMSET_A>);
407impl MEMSET_R {
408    #[inline(always)]
409    pub(crate) fn new(bits: bool) -> Self {
410        MEMSET_R(crate::FieldReader::new(bits))
411    }
412    #[doc = r"Get enumerated values variant"]
413    #[inline(always)]
414    pub fn variant(&self) -> MEMSET_A {
415        match self.bits {
416            false => MEMSET_A::NORMAL_MODE,
417            true => MEMSET_A::HW_MODE,
418        }
419    }
420    #[doc = "Checks if the value of the field is `NORMAL_MODE`"]
421    #[inline(always)]
422    pub fn is_normal_mode(&self) -> bool {
423        **self == MEMSET_A::NORMAL_MODE
424    }
425    #[doc = "Checks if the value of the field is `HW_MODE`"]
426    #[inline(always)]
427    pub fn is_hw_mode(&self) -> bool {
428        **self == MEMSET_A::HW_MODE
429    }
430}
431impl core::ops::Deref for MEMSET_R {
432    type Target = crate::FieldReader<bool, MEMSET_A>;
433    #[inline(always)]
434    fn deref(&self) -> &Self::Target {
435        &self.0
436    }
437}
438#[doc = "Field `MEMSET` writer - Channel x Fill Block of memory"]
439pub struct MEMSET_W<'a> {
440    w: &'a mut W,
441}
442impl<'a> MEMSET_W<'a> {
443    #[doc = r"Writes `variant` to the field"]
444    #[inline(always)]
445    pub fn variant(self, variant: MEMSET_A) -> &'a mut W {
446        self.bit(variant.into())
447    }
448    #[doc = "Memset is not activated."]
449    #[inline(always)]
450    pub fn normal_mode(self) -> &'a mut W {
451        self.variant(MEMSET_A::NORMAL_MODE)
452    }
453    #[doc = "Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis."]
454    #[inline(always)]
455    pub fn hw_mode(self) -> &'a mut W {
456        self.variant(MEMSET_A::HW_MODE)
457    }
458    #[doc = r"Sets the field bit"]
459    #[inline(always)]
460    pub fn set_bit(self) -> &'a mut W {
461        self.bit(true)
462    }
463    #[doc = r"Clears the field bit"]
464    #[inline(always)]
465    pub fn clear_bit(self) -> &'a mut W {
466        self.bit(false)
467    }
468    #[doc = r"Writes raw bits to the field"]
469    #[inline(always)]
470    pub fn bit(self, value: bool) -> &'a mut W {
471        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
472        self.w
473    }
474}
475#[doc = "Channel x Chunk Size\n\nValue on reset: 0"]
476#[derive(Clone, Copy, Debug, PartialEq)]
477#[repr(u8)]
478pub enum CSIZE_A {
479    #[doc = "0: 1 data transferred"]
480    CHK_1 = 0,
481    #[doc = "1: 2 data transferred"]
482    CHK_2 = 1,
483    #[doc = "2: 4 data transferred"]
484    CHK_4 = 2,
485    #[doc = "3: 8 data transferred"]
486    CHK_8 = 3,
487    #[doc = "4: 16 data transferred"]
488    CHK_16 = 4,
489}
490impl From<CSIZE_A> for u8 {
491    #[inline(always)]
492    fn from(variant: CSIZE_A) -> Self {
493        variant as _
494    }
495}
496#[doc = "Field `CSIZE` reader - Channel x Chunk Size"]
497pub struct CSIZE_R(crate::FieldReader<u8, CSIZE_A>);
498impl CSIZE_R {
499    #[inline(always)]
500    pub(crate) fn new(bits: u8) -> Self {
501        CSIZE_R(crate::FieldReader::new(bits))
502    }
503    #[doc = r"Get enumerated values variant"]
504    #[inline(always)]
505    pub fn variant(&self) -> Option<CSIZE_A> {
506        match self.bits {
507            0 => Some(CSIZE_A::CHK_1),
508            1 => Some(CSIZE_A::CHK_2),
509            2 => Some(CSIZE_A::CHK_4),
510            3 => Some(CSIZE_A::CHK_8),
511            4 => Some(CSIZE_A::CHK_16),
512            _ => None,
513        }
514    }
515    #[doc = "Checks if the value of the field is `CHK_1`"]
516    #[inline(always)]
517    pub fn is_chk_1(&self) -> bool {
518        **self == CSIZE_A::CHK_1
519    }
520    #[doc = "Checks if the value of the field is `CHK_2`"]
521    #[inline(always)]
522    pub fn is_chk_2(&self) -> bool {
523        **self == CSIZE_A::CHK_2
524    }
525    #[doc = "Checks if the value of the field is `CHK_4`"]
526    #[inline(always)]
527    pub fn is_chk_4(&self) -> bool {
528        **self == CSIZE_A::CHK_4
529    }
530    #[doc = "Checks if the value of the field is `CHK_8`"]
531    #[inline(always)]
532    pub fn is_chk_8(&self) -> bool {
533        **self == CSIZE_A::CHK_8
534    }
535    #[doc = "Checks if the value of the field is `CHK_16`"]
536    #[inline(always)]
537    pub fn is_chk_16(&self) -> bool {
538        **self == CSIZE_A::CHK_16
539    }
540}
541impl core::ops::Deref for CSIZE_R {
542    type Target = crate::FieldReader<u8, CSIZE_A>;
543    #[inline(always)]
544    fn deref(&self) -> &Self::Target {
545        &self.0
546    }
547}
548#[doc = "Field `CSIZE` writer - Channel x Chunk Size"]
549pub struct CSIZE_W<'a> {
550    w: &'a mut W,
551}
552impl<'a> CSIZE_W<'a> {
553    #[doc = r"Writes `variant` to the field"]
554    #[inline(always)]
555    pub fn variant(self, variant: CSIZE_A) -> &'a mut W {
556        unsafe { self.bits(variant.into()) }
557    }
558    #[doc = "1 data transferred"]
559    #[inline(always)]
560    pub fn chk_1(self) -> &'a mut W {
561        self.variant(CSIZE_A::CHK_1)
562    }
563    #[doc = "2 data transferred"]
564    #[inline(always)]
565    pub fn chk_2(self) -> &'a mut W {
566        self.variant(CSIZE_A::CHK_2)
567    }
568    #[doc = "4 data transferred"]
569    #[inline(always)]
570    pub fn chk_4(self) -> &'a mut W {
571        self.variant(CSIZE_A::CHK_4)
572    }
573    #[doc = "8 data transferred"]
574    #[inline(always)]
575    pub fn chk_8(self) -> &'a mut W {
576        self.variant(CSIZE_A::CHK_8)
577    }
578    #[doc = "16 data transferred"]
579    #[inline(always)]
580    pub fn chk_16(self) -> &'a mut W {
581        self.variant(CSIZE_A::CHK_16)
582    }
583    #[doc = r"Writes raw bits to the field"]
584    #[inline(always)]
585    pub unsafe fn bits(self, value: u8) -> &'a mut W {
586        self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8);
587        self.w
588    }
589}
590#[doc = "Channel x Data Width\n\nValue on reset: 0"]
591#[derive(Clone, Copy, Debug, PartialEq)]
592#[repr(u8)]
593pub enum DWIDTH_A {
594    #[doc = "0: The data size is set to 8 bits"]
595    BYTE = 0,
596    #[doc = "1: The data size is set to 16 bits"]
597    HALFWORD = 1,
598    #[doc = "2: The data size is set to 32 bits"]
599    WORD = 2,
600}
601impl From<DWIDTH_A> for u8 {
602    #[inline(always)]
603    fn from(variant: DWIDTH_A) -> Self {
604        variant as _
605    }
606}
607#[doc = "Field `DWIDTH` reader - Channel x Data Width"]
608pub struct DWIDTH_R(crate::FieldReader<u8, DWIDTH_A>);
609impl DWIDTH_R {
610    #[inline(always)]
611    pub(crate) fn new(bits: u8) -> Self {
612        DWIDTH_R(crate::FieldReader::new(bits))
613    }
614    #[doc = r"Get enumerated values variant"]
615    #[inline(always)]
616    pub fn variant(&self) -> Option<DWIDTH_A> {
617        match self.bits {
618            0 => Some(DWIDTH_A::BYTE),
619            1 => Some(DWIDTH_A::HALFWORD),
620            2 => Some(DWIDTH_A::WORD),
621            _ => None,
622        }
623    }
624    #[doc = "Checks if the value of the field is `BYTE`"]
625    #[inline(always)]
626    pub fn is_byte(&self) -> bool {
627        **self == DWIDTH_A::BYTE
628    }
629    #[doc = "Checks if the value of the field is `HALFWORD`"]
630    #[inline(always)]
631    pub fn is_halfword(&self) -> bool {
632        **self == DWIDTH_A::HALFWORD
633    }
634    #[doc = "Checks if the value of the field is `WORD`"]
635    #[inline(always)]
636    pub fn is_word(&self) -> bool {
637        **self == DWIDTH_A::WORD
638    }
639}
640impl core::ops::Deref for DWIDTH_R {
641    type Target = crate::FieldReader<u8, DWIDTH_A>;
642    #[inline(always)]
643    fn deref(&self) -> &Self::Target {
644        &self.0
645    }
646}
647#[doc = "Field `DWIDTH` writer - Channel x Data Width"]
648pub struct DWIDTH_W<'a> {
649    w: &'a mut W,
650}
651impl<'a> DWIDTH_W<'a> {
652    #[doc = r"Writes `variant` to the field"]
653    #[inline(always)]
654    pub fn variant(self, variant: DWIDTH_A) -> &'a mut W {
655        unsafe { self.bits(variant.into()) }
656    }
657    #[doc = "The data size is set to 8 bits"]
658    #[inline(always)]
659    pub fn byte(self) -> &'a mut W {
660        self.variant(DWIDTH_A::BYTE)
661    }
662    #[doc = "The data size is set to 16 bits"]
663    #[inline(always)]
664    pub fn halfword(self) -> &'a mut W {
665        self.variant(DWIDTH_A::HALFWORD)
666    }
667    #[doc = "The data size is set to 32 bits"]
668    #[inline(always)]
669    pub fn word(self) -> &'a mut W {
670        self.variant(DWIDTH_A::WORD)
671    }
672    #[doc = r"Writes raw bits to the field"]
673    #[inline(always)]
674    pub unsafe fn bits(self, value: u8) -> &'a mut W {
675        self.w.bits = (self.w.bits & !(0x03 << 11)) | ((value as u32 & 0x03) << 11);
676        self.w
677    }
678}
679#[doc = "Channel x Source Interface Identifier\n\nValue on reset: 0"]
680#[derive(Clone, Copy, Debug, PartialEq)]
681pub enum SIF_A {
682    #[doc = "0: The data is read through the system bus interface 0."]
683    AHB_IF0 = 0,
684    #[doc = "1: The data is read through the system bus interface 1."]
685    AHB_IF1 = 1,
686}
687impl From<SIF_A> for bool {
688    #[inline(always)]
689    fn from(variant: SIF_A) -> Self {
690        variant as u8 != 0
691    }
692}
693#[doc = "Field `SIF` reader - Channel x Source Interface Identifier"]
694pub struct SIF_R(crate::FieldReader<bool, SIF_A>);
695impl SIF_R {
696    #[inline(always)]
697    pub(crate) fn new(bits: bool) -> Self {
698        SIF_R(crate::FieldReader::new(bits))
699    }
700    #[doc = r"Get enumerated values variant"]
701    #[inline(always)]
702    pub fn variant(&self) -> SIF_A {
703        match self.bits {
704            false => SIF_A::AHB_IF0,
705            true => SIF_A::AHB_IF1,
706        }
707    }
708    #[doc = "Checks if the value of the field is `AHB_IF0`"]
709    #[inline(always)]
710    pub fn is_ahb_if0(&self) -> bool {
711        **self == SIF_A::AHB_IF0
712    }
713    #[doc = "Checks if the value of the field is `AHB_IF1`"]
714    #[inline(always)]
715    pub fn is_ahb_if1(&self) -> bool {
716        **self == SIF_A::AHB_IF1
717    }
718}
719impl core::ops::Deref for SIF_R {
720    type Target = crate::FieldReader<bool, SIF_A>;
721    #[inline(always)]
722    fn deref(&self) -> &Self::Target {
723        &self.0
724    }
725}
726#[doc = "Field `SIF` writer - Channel x Source Interface Identifier"]
727pub struct SIF_W<'a> {
728    w: &'a mut W,
729}
730impl<'a> SIF_W<'a> {
731    #[doc = r"Writes `variant` to the field"]
732    #[inline(always)]
733    pub fn variant(self, variant: SIF_A) -> &'a mut W {
734        self.bit(variant.into())
735    }
736    #[doc = "The data is read through the system bus interface 0."]
737    #[inline(always)]
738    pub fn ahb_if0(self) -> &'a mut W {
739        self.variant(SIF_A::AHB_IF0)
740    }
741    #[doc = "The data is read through the system bus interface 1."]
742    #[inline(always)]
743    pub fn ahb_if1(self) -> &'a mut W {
744        self.variant(SIF_A::AHB_IF1)
745    }
746    #[doc = r"Sets the field bit"]
747    #[inline(always)]
748    pub fn set_bit(self) -> &'a mut W {
749        self.bit(true)
750    }
751    #[doc = r"Clears the field bit"]
752    #[inline(always)]
753    pub fn clear_bit(self) -> &'a mut W {
754        self.bit(false)
755    }
756    #[doc = r"Writes raw bits to the field"]
757    #[inline(always)]
758    pub fn bit(self, value: bool) -> &'a mut W {
759        self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
760        self.w
761    }
762}
763#[doc = "Channel x Destination Interface Identifier\n\nValue on reset: 0"]
764#[derive(Clone, Copy, Debug, PartialEq)]
765pub enum DIF_A {
766    #[doc = "0: The data is written through the system bus interface 0."]
767    AHB_IF0 = 0,
768    #[doc = "1: The data is written though the system bus interface 1."]
769    AHB_IF1 = 1,
770}
771impl From<DIF_A> for bool {
772    #[inline(always)]
773    fn from(variant: DIF_A) -> Self {
774        variant as u8 != 0
775    }
776}
777#[doc = "Field `DIF` reader - Channel x Destination Interface Identifier"]
778pub struct DIF_R(crate::FieldReader<bool, DIF_A>);
779impl DIF_R {
780    #[inline(always)]
781    pub(crate) fn new(bits: bool) -> Self {
782        DIF_R(crate::FieldReader::new(bits))
783    }
784    #[doc = r"Get enumerated values variant"]
785    #[inline(always)]
786    pub fn variant(&self) -> DIF_A {
787        match self.bits {
788            false => DIF_A::AHB_IF0,
789            true => DIF_A::AHB_IF1,
790        }
791    }
792    #[doc = "Checks if the value of the field is `AHB_IF0`"]
793    #[inline(always)]
794    pub fn is_ahb_if0(&self) -> bool {
795        **self == DIF_A::AHB_IF0
796    }
797    #[doc = "Checks if the value of the field is `AHB_IF1`"]
798    #[inline(always)]
799    pub fn is_ahb_if1(&self) -> bool {
800        **self == DIF_A::AHB_IF1
801    }
802}
803impl core::ops::Deref for DIF_R {
804    type Target = crate::FieldReader<bool, DIF_A>;
805    #[inline(always)]
806    fn deref(&self) -> &Self::Target {
807        &self.0
808    }
809}
810#[doc = "Field `DIF` writer - Channel x Destination Interface Identifier"]
811pub struct DIF_W<'a> {
812    w: &'a mut W,
813}
814impl<'a> DIF_W<'a> {
815    #[doc = r"Writes `variant` to the field"]
816    #[inline(always)]
817    pub fn variant(self, variant: DIF_A) -> &'a mut W {
818        self.bit(variant.into())
819    }
820    #[doc = "The data is written through the system bus interface 0."]
821    #[inline(always)]
822    pub fn ahb_if0(self) -> &'a mut W {
823        self.variant(DIF_A::AHB_IF0)
824    }
825    #[doc = "The data is written though the system bus interface 1."]
826    #[inline(always)]
827    pub fn ahb_if1(self) -> &'a mut W {
828        self.variant(DIF_A::AHB_IF1)
829    }
830    #[doc = r"Sets the field bit"]
831    #[inline(always)]
832    pub fn set_bit(self) -> &'a mut W {
833        self.bit(true)
834    }
835    #[doc = r"Clears the field bit"]
836    #[inline(always)]
837    pub fn clear_bit(self) -> &'a mut W {
838        self.bit(false)
839    }
840    #[doc = r"Writes raw bits to the field"]
841    #[inline(always)]
842    pub fn bit(self, value: bool) -> &'a mut W {
843        self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
844        self.w
845    }
846}
847#[doc = "Channel x Source Addressing Mode\n\nValue on reset: 0"]
848#[derive(Clone, Copy, Debug, PartialEq)]
849#[repr(u8)]
850pub enum SAM_A {
851    #[doc = "0: The address remains unchanged."]
852    FIXED_AM = 0,
853    #[doc = "1: The addressing mode is incremented (the increment size is set to the data size)."]
854    INCREMENTED_AM = 1,
855    #[doc = "2: The microblock stride is added at the microblock boundary."]
856    UBS_AM = 2,
857    #[doc = "3: The microblock stride is added at the microblock boundary, the data stride is added at the data boundary."]
858    UBS_DS_AM = 3,
859}
860impl From<SAM_A> for u8 {
861    #[inline(always)]
862    fn from(variant: SAM_A) -> Self {
863        variant as _
864    }
865}
866#[doc = "Field `SAM` reader - Channel x Source Addressing Mode"]
867pub struct SAM_R(crate::FieldReader<u8, SAM_A>);
868impl SAM_R {
869    #[inline(always)]
870    pub(crate) fn new(bits: u8) -> Self {
871        SAM_R(crate::FieldReader::new(bits))
872    }
873    #[doc = r"Get enumerated values variant"]
874    #[inline(always)]
875    pub fn variant(&self) -> SAM_A {
876        match self.bits {
877            0 => SAM_A::FIXED_AM,
878            1 => SAM_A::INCREMENTED_AM,
879            2 => SAM_A::UBS_AM,
880            3 => SAM_A::UBS_DS_AM,
881            _ => unreachable!(),
882        }
883    }
884    #[doc = "Checks if the value of the field is `FIXED_AM`"]
885    #[inline(always)]
886    pub fn is_fixed_am(&self) -> bool {
887        **self == SAM_A::FIXED_AM
888    }
889    #[doc = "Checks if the value of the field is `INCREMENTED_AM`"]
890    #[inline(always)]
891    pub fn is_incremented_am(&self) -> bool {
892        **self == SAM_A::INCREMENTED_AM
893    }
894    #[doc = "Checks if the value of the field is `UBS_AM`"]
895    #[inline(always)]
896    pub fn is_ubs_am(&self) -> bool {
897        **self == SAM_A::UBS_AM
898    }
899    #[doc = "Checks if the value of the field is `UBS_DS_AM`"]
900    #[inline(always)]
901    pub fn is_ubs_ds_am(&self) -> bool {
902        **self == SAM_A::UBS_DS_AM
903    }
904}
905impl core::ops::Deref for SAM_R {
906    type Target = crate::FieldReader<u8, SAM_A>;
907    #[inline(always)]
908    fn deref(&self) -> &Self::Target {
909        &self.0
910    }
911}
912#[doc = "Field `SAM` writer - Channel x Source Addressing Mode"]
913pub struct SAM_W<'a> {
914    w: &'a mut W,
915}
916impl<'a> SAM_W<'a> {
917    #[doc = r"Writes `variant` to the field"]
918    #[inline(always)]
919    pub fn variant(self, variant: SAM_A) -> &'a mut W {
920        self.bits(variant.into())
921    }
922    #[doc = "The address remains unchanged."]
923    #[inline(always)]
924    pub fn fixed_am(self) -> &'a mut W {
925        self.variant(SAM_A::FIXED_AM)
926    }
927    #[doc = "The addressing mode is incremented (the increment size is set to the data size)."]
928    #[inline(always)]
929    pub fn incremented_am(self) -> &'a mut W {
930        self.variant(SAM_A::INCREMENTED_AM)
931    }
932    #[doc = "The microblock stride is added at the microblock boundary."]
933    #[inline(always)]
934    pub fn ubs_am(self) -> &'a mut W {
935        self.variant(SAM_A::UBS_AM)
936    }
937    #[doc = "The microblock stride is added at the microblock boundary, the data stride is added at the data boundary."]
938    #[inline(always)]
939    pub fn ubs_ds_am(self) -> &'a mut W {
940        self.variant(SAM_A::UBS_DS_AM)
941    }
942    #[doc = r"Writes raw bits to the field"]
943    #[inline(always)]
944    pub fn bits(self, value: u8) -> &'a mut W {
945        self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16);
946        self.w
947    }
948}
949#[doc = "Channel x Destination Addressing Mode\n\nValue on reset: 0"]
950#[derive(Clone, Copy, Debug, PartialEq)]
951#[repr(u8)]
952pub enum DAM_A {
953    #[doc = "0: The address remains unchanged."]
954    FIXED_AM = 0,
955    #[doc = "1: The addressing mode is incremented (the increment size is set to the data size)."]
956    INCREMENTED_AM = 1,
957    #[doc = "2: The microblock stride is added at the microblock boundary."]
958    UBS_AM = 2,
959    #[doc = "3: The microblock stride is added at the microblock boundary, the data stride is added at the data boundary."]
960    UBS_DS_AM = 3,
961}
962impl From<DAM_A> for u8 {
963    #[inline(always)]
964    fn from(variant: DAM_A) -> Self {
965        variant as _
966    }
967}
968#[doc = "Field `DAM` reader - Channel x Destination Addressing Mode"]
969pub struct DAM_R(crate::FieldReader<u8, DAM_A>);
970impl DAM_R {
971    #[inline(always)]
972    pub(crate) fn new(bits: u8) -> Self {
973        DAM_R(crate::FieldReader::new(bits))
974    }
975    #[doc = r"Get enumerated values variant"]
976    #[inline(always)]
977    pub fn variant(&self) -> DAM_A {
978        match self.bits {
979            0 => DAM_A::FIXED_AM,
980            1 => DAM_A::INCREMENTED_AM,
981            2 => DAM_A::UBS_AM,
982            3 => DAM_A::UBS_DS_AM,
983            _ => unreachable!(),
984        }
985    }
986    #[doc = "Checks if the value of the field is `FIXED_AM`"]
987    #[inline(always)]
988    pub fn is_fixed_am(&self) -> bool {
989        **self == DAM_A::FIXED_AM
990    }
991    #[doc = "Checks if the value of the field is `INCREMENTED_AM`"]
992    #[inline(always)]
993    pub fn is_incremented_am(&self) -> bool {
994        **self == DAM_A::INCREMENTED_AM
995    }
996    #[doc = "Checks if the value of the field is `UBS_AM`"]
997    #[inline(always)]
998    pub fn is_ubs_am(&self) -> bool {
999        **self == DAM_A::UBS_AM
1000    }
1001    #[doc = "Checks if the value of the field is `UBS_DS_AM`"]
1002    #[inline(always)]
1003    pub fn is_ubs_ds_am(&self) -> bool {
1004        **self == DAM_A::UBS_DS_AM
1005    }
1006}
1007impl core::ops::Deref for DAM_R {
1008    type Target = crate::FieldReader<u8, DAM_A>;
1009    #[inline(always)]
1010    fn deref(&self) -> &Self::Target {
1011        &self.0
1012    }
1013}
1014#[doc = "Field `DAM` writer - Channel x Destination Addressing Mode"]
1015pub struct DAM_W<'a> {
1016    w: &'a mut W,
1017}
1018impl<'a> DAM_W<'a> {
1019    #[doc = r"Writes `variant` to the field"]
1020    #[inline(always)]
1021    pub fn variant(self, variant: DAM_A) -> &'a mut W {
1022        self.bits(variant.into())
1023    }
1024    #[doc = "The address remains unchanged."]
1025    #[inline(always)]
1026    pub fn fixed_am(self) -> &'a mut W {
1027        self.variant(DAM_A::FIXED_AM)
1028    }
1029    #[doc = "The addressing mode is incremented (the increment size is set to the data size)."]
1030    #[inline(always)]
1031    pub fn incremented_am(self) -> &'a mut W {
1032        self.variant(DAM_A::INCREMENTED_AM)
1033    }
1034    #[doc = "The microblock stride is added at the microblock boundary."]
1035    #[inline(always)]
1036    pub fn ubs_am(self) -> &'a mut W {
1037        self.variant(DAM_A::UBS_AM)
1038    }
1039    #[doc = "The microblock stride is added at the microblock boundary, the data stride is added at the data boundary."]
1040    #[inline(always)]
1041    pub fn ubs_ds_am(self) -> &'a mut W {
1042        self.variant(DAM_A::UBS_DS_AM)
1043    }
1044    #[doc = r"Writes raw bits to the field"]
1045    #[inline(always)]
1046    pub fn bits(self, value: u8) -> &'a mut W {
1047        self.w.bits = (self.w.bits & !(0x03 << 18)) | ((value as u32 & 0x03) << 18);
1048        self.w
1049    }
1050}
1051#[doc = "Channel Initialization Terminated (this bit is read-only)\n\nValue on reset: 0"]
1052#[derive(Clone, Copy, Debug, PartialEq)]
1053pub enum INITD_A {
1054    #[doc = "0: Channel initialization is in progress."]
1055    IN_PROGRESS = 0,
1056    #[doc = "1: Channel initialization is completed."]
1057    TERMINATED = 1,
1058}
1059impl From<INITD_A> for bool {
1060    #[inline(always)]
1061    fn from(variant: INITD_A) -> Self {
1062        variant as u8 != 0
1063    }
1064}
1065#[doc = "Field `INITD` reader - Channel Initialization Terminated (this bit is read-only)"]
1066pub struct INITD_R(crate::FieldReader<bool, INITD_A>);
1067impl INITD_R {
1068    #[inline(always)]
1069    pub(crate) fn new(bits: bool) -> Self {
1070        INITD_R(crate::FieldReader::new(bits))
1071    }
1072    #[doc = r"Get enumerated values variant"]
1073    #[inline(always)]
1074    pub fn variant(&self) -> INITD_A {
1075        match self.bits {
1076            false => INITD_A::IN_PROGRESS,
1077            true => INITD_A::TERMINATED,
1078        }
1079    }
1080    #[doc = "Checks if the value of the field is `IN_PROGRESS`"]
1081    #[inline(always)]
1082    pub fn is_in_progress(&self) -> bool {
1083        **self == INITD_A::IN_PROGRESS
1084    }
1085    #[doc = "Checks if the value of the field is `TERMINATED`"]
1086    #[inline(always)]
1087    pub fn is_terminated(&self) -> bool {
1088        **self == INITD_A::TERMINATED
1089    }
1090}
1091impl core::ops::Deref for INITD_R {
1092    type Target = crate::FieldReader<bool, INITD_A>;
1093    #[inline(always)]
1094    fn deref(&self) -> &Self::Target {
1095        &self.0
1096    }
1097}
1098#[doc = "Field `INITD` writer - Channel Initialization Terminated (this bit is read-only)"]
1099pub struct INITD_W<'a> {
1100    w: &'a mut W,
1101}
1102impl<'a> INITD_W<'a> {
1103    #[doc = r"Writes `variant` to the field"]
1104    #[inline(always)]
1105    pub fn variant(self, variant: INITD_A) -> &'a mut W {
1106        self.bit(variant.into())
1107    }
1108    #[doc = "Channel initialization is in progress."]
1109    #[inline(always)]
1110    pub fn in_progress(self) -> &'a mut W {
1111        self.variant(INITD_A::IN_PROGRESS)
1112    }
1113    #[doc = "Channel initialization is completed."]
1114    #[inline(always)]
1115    pub fn terminated(self) -> &'a mut W {
1116        self.variant(INITD_A::TERMINATED)
1117    }
1118    #[doc = r"Sets the field bit"]
1119    #[inline(always)]
1120    pub fn set_bit(self) -> &'a mut W {
1121        self.bit(true)
1122    }
1123    #[doc = r"Clears the field bit"]
1124    #[inline(always)]
1125    pub fn clear_bit(self) -> &'a mut W {
1126        self.bit(false)
1127    }
1128    #[doc = r"Writes raw bits to the field"]
1129    #[inline(always)]
1130    pub fn bit(self, value: bool) -> &'a mut W {
1131        self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21);
1132        self.w
1133    }
1134}
1135#[doc = "Read in Progress (this bit is read-only)\n\nValue on reset: 0"]
1136#[derive(Clone, Copy, Debug, PartialEq)]
1137pub enum RDIP_A {
1138    #[doc = "0: No Active read transaction on the bus."]
1139    DONE = 0,
1140    #[doc = "1: A read transaction is in progress."]
1141    IN_PROGRESS = 1,
1142}
1143impl From<RDIP_A> for bool {
1144    #[inline(always)]
1145    fn from(variant: RDIP_A) -> Self {
1146        variant as u8 != 0
1147    }
1148}
1149#[doc = "Field `RDIP` reader - Read in Progress (this bit is read-only)"]
1150pub struct RDIP_R(crate::FieldReader<bool, RDIP_A>);
1151impl RDIP_R {
1152    #[inline(always)]
1153    pub(crate) fn new(bits: bool) -> Self {
1154        RDIP_R(crate::FieldReader::new(bits))
1155    }
1156    #[doc = r"Get enumerated values variant"]
1157    #[inline(always)]
1158    pub fn variant(&self) -> RDIP_A {
1159        match self.bits {
1160            false => RDIP_A::DONE,
1161            true => RDIP_A::IN_PROGRESS,
1162        }
1163    }
1164    #[doc = "Checks if the value of the field is `DONE`"]
1165    #[inline(always)]
1166    pub fn is_done(&self) -> bool {
1167        **self == RDIP_A::DONE
1168    }
1169    #[doc = "Checks if the value of the field is `IN_PROGRESS`"]
1170    #[inline(always)]
1171    pub fn is_in_progress(&self) -> bool {
1172        **self == RDIP_A::IN_PROGRESS
1173    }
1174}
1175impl core::ops::Deref for RDIP_R {
1176    type Target = crate::FieldReader<bool, RDIP_A>;
1177    #[inline(always)]
1178    fn deref(&self) -> &Self::Target {
1179        &self.0
1180    }
1181}
1182#[doc = "Field `RDIP` writer - Read in Progress (this bit is read-only)"]
1183pub struct RDIP_W<'a> {
1184    w: &'a mut W,
1185}
1186impl<'a> RDIP_W<'a> {
1187    #[doc = r"Writes `variant` to the field"]
1188    #[inline(always)]
1189    pub fn variant(self, variant: RDIP_A) -> &'a mut W {
1190        self.bit(variant.into())
1191    }
1192    #[doc = "No Active read transaction on the bus."]
1193    #[inline(always)]
1194    pub fn done(self) -> &'a mut W {
1195        self.variant(RDIP_A::DONE)
1196    }
1197    #[doc = "A read transaction is in progress."]
1198    #[inline(always)]
1199    pub fn in_progress(self) -> &'a mut W {
1200        self.variant(RDIP_A::IN_PROGRESS)
1201    }
1202    #[doc = r"Sets the field bit"]
1203    #[inline(always)]
1204    pub fn set_bit(self) -> &'a mut W {
1205        self.bit(true)
1206    }
1207    #[doc = r"Clears the field bit"]
1208    #[inline(always)]
1209    pub fn clear_bit(self) -> &'a mut W {
1210        self.bit(false)
1211    }
1212    #[doc = r"Writes raw bits to the field"]
1213    #[inline(always)]
1214    pub fn bit(self, value: bool) -> &'a mut W {
1215        self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22);
1216        self.w
1217    }
1218}
1219#[doc = "Write in Progress (this bit is read-only)\n\nValue on reset: 0"]
1220#[derive(Clone, Copy, Debug, PartialEq)]
1221pub enum WRIP_A {
1222    #[doc = "0: No Active write transaction on the bus."]
1223    DONE = 0,
1224    #[doc = "1: A Write transaction is in progress."]
1225    IN_PROGRESS = 1,
1226}
1227impl From<WRIP_A> for bool {
1228    #[inline(always)]
1229    fn from(variant: WRIP_A) -> Self {
1230        variant as u8 != 0
1231    }
1232}
1233#[doc = "Field `WRIP` reader - Write in Progress (this bit is read-only)"]
1234pub struct WRIP_R(crate::FieldReader<bool, WRIP_A>);
1235impl WRIP_R {
1236    #[inline(always)]
1237    pub(crate) fn new(bits: bool) -> Self {
1238        WRIP_R(crate::FieldReader::new(bits))
1239    }
1240    #[doc = r"Get enumerated values variant"]
1241    #[inline(always)]
1242    pub fn variant(&self) -> WRIP_A {
1243        match self.bits {
1244            false => WRIP_A::DONE,
1245            true => WRIP_A::IN_PROGRESS,
1246        }
1247    }
1248    #[doc = "Checks if the value of the field is `DONE`"]
1249    #[inline(always)]
1250    pub fn is_done(&self) -> bool {
1251        **self == WRIP_A::DONE
1252    }
1253    #[doc = "Checks if the value of the field is `IN_PROGRESS`"]
1254    #[inline(always)]
1255    pub fn is_in_progress(&self) -> bool {
1256        **self == WRIP_A::IN_PROGRESS
1257    }
1258}
1259impl core::ops::Deref for WRIP_R {
1260    type Target = crate::FieldReader<bool, WRIP_A>;
1261    #[inline(always)]
1262    fn deref(&self) -> &Self::Target {
1263        &self.0
1264    }
1265}
1266#[doc = "Field `WRIP` writer - Write in Progress (this bit is read-only)"]
1267pub struct WRIP_W<'a> {
1268    w: &'a mut W,
1269}
1270impl<'a> WRIP_W<'a> {
1271    #[doc = r"Writes `variant` to the field"]
1272    #[inline(always)]
1273    pub fn variant(self, variant: WRIP_A) -> &'a mut W {
1274        self.bit(variant.into())
1275    }
1276    #[doc = "No Active write transaction on the bus."]
1277    #[inline(always)]
1278    pub fn done(self) -> &'a mut W {
1279        self.variant(WRIP_A::DONE)
1280    }
1281    #[doc = "A Write transaction is in progress."]
1282    #[inline(always)]
1283    pub fn in_progress(self) -> &'a mut W {
1284        self.variant(WRIP_A::IN_PROGRESS)
1285    }
1286    #[doc = r"Sets the field bit"]
1287    #[inline(always)]
1288    pub fn set_bit(self) -> &'a mut W {
1289        self.bit(true)
1290    }
1291    #[doc = r"Clears the field bit"]
1292    #[inline(always)]
1293    pub fn clear_bit(self) -> &'a mut W {
1294        self.bit(false)
1295    }
1296    #[doc = r"Writes raw bits to the field"]
1297    #[inline(always)]
1298    pub fn bit(self, value: bool) -> &'a mut W {
1299        self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23);
1300        self.w
1301    }
1302}
1303#[doc = "Field `PERID` reader - Channel x Peripheral Hardware Request Line Identifier"]
1304pub struct PERID_R(crate::FieldReader<u8, u8>);
1305impl PERID_R {
1306    #[inline(always)]
1307    pub(crate) fn new(bits: u8) -> Self {
1308        PERID_R(crate::FieldReader::new(bits))
1309    }
1310}
1311impl core::ops::Deref for PERID_R {
1312    type Target = crate::FieldReader<u8, u8>;
1313    #[inline(always)]
1314    fn deref(&self) -> &Self::Target {
1315        &self.0
1316    }
1317}
1318#[doc = "Field `PERID` writer - Channel x Peripheral Hardware Request Line Identifier"]
1319pub struct PERID_W<'a> {
1320    w: &'a mut W,
1321}
1322impl<'a> PERID_W<'a> {
1323    #[doc = r"Writes raw bits to the field"]
1324    #[inline(always)]
1325    pub unsafe fn bits(self, value: u8) -> &'a mut W {
1326        self.w.bits = (self.w.bits & !(0x7f << 24)) | ((value as u32 & 0x7f) << 24);
1327        self.w
1328    }
1329}
1330impl R {
1331    #[doc = "Bit 0 - Channel x Transfer Type"]
1332    #[inline(always)]
1333    pub fn type_(&self) -> TYPE_R {
1334        TYPE_R::new((self.bits & 0x01) != 0)
1335    }
1336    #[doc = "Bits 1:2 - Channel x Memory Burst Size"]
1337    #[inline(always)]
1338    pub fn mbsize(&self) -> MBSIZE_R {
1339        MBSIZE_R::new(((self.bits >> 1) & 0x03) as u8)
1340    }
1341    #[doc = "Bit 4 - Channel x Synchronization"]
1342    #[inline(always)]
1343    pub fn dsync(&self) -> DSYNC_R {
1344        DSYNC_R::new(((self.bits >> 4) & 0x01) != 0)
1345    }
1346    #[doc = "Bit 6 - Channel x Software Request Trigger"]
1347    #[inline(always)]
1348    pub fn swreq(&self) -> SWREQ_R {
1349        SWREQ_R::new(((self.bits >> 6) & 0x01) != 0)
1350    }
1351    #[doc = "Bit 7 - Channel x Fill Block of memory"]
1352    #[inline(always)]
1353    pub fn memset(&self) -> MEMSET_R {
1354        MEMSET_R::new(((self.bits >> 7) & 0x01) != 0)
1355    }
1356    #[doc = "Bits 8:10 - Channel x Chunk Size"]
1357    #[inline(always)]
1358    pub fn csize(&self) -> CSIZE_R {
1359        CSIZE_R::new(((self.bits >> 8) & 0x07) as u8)
1360    }
1361    #[doc = "Bits 11:12 - Channel x Data Width"]
1362    #[inline(always)]
1363    pub fn dwidth(&self) -> DWIDTH_R {
1364        DWIDTH_R::new(((self.bits >> 11) & 0x03) as u8)
1365    }
1366    #[doc = "Bit 13 - Channel x Source Interface Identifier"]
1367    #[inline(always)]
1368    pub fn sif(&self) -> SIF_R {
1369        SIF_R::new(((self.bits >> 13) & 0x01) != 0)
1370    }
1371    #[doc = "Bit 14 - Channel x Destination Interface Identifier"]
1372    #[inline(always)]
1373    pub fn dif(&self) -> DIF_R {
1374        DIF_R::new(((self.bits >> 14) & 0x01) != 0)
1375    }
1376    #[doc = "Bits 16:17 - Channel x Source Addressing Mode"]
1377    #[inline(always)]
1378    pub fn sam(&self) -> SAM_R {
1379        SAM_R::new(((self.bits >> 16) & 0x03) as u8)
1380    }
1381    #[doc = "Bits 18:19 - Channel x Destination Addressing Mode"]
1382    #[inline(always)]
1383    pub fn dam(&self) -> DAM_R {
1384        DAM_R::new(((self.bits >> 18) & 0x03) as u8)
1385    }
1386    #[doc = "Bit 21 - Channel Initialization Terminated (this bit is read-only)"]
1387    #[inline(always)]
1388    pub fn initd(&self) -> INITD_R {
1389        INITD_R::new(((self.bits >> 21) & 0x01) != 0)
1390    }
1391    #[doc = "Bit 22 - Read in Progress (this bit is read-only)"]
1392    #[inline(always)]
1393    pub fn rdip(&self) -> RDIP_R {
1394        RDIP_R::new(((self.bits >> 22) & 0x01) != 0)
1395    }
1396    #[doc = "Bit 23 - Write in Progress (this bit is read-only)"]
1397    #[inline(always)]
1398    pub fn wrip(&self) -> WRIP_R {
1399        WRIP_R::new(((self.bits >> 23) & 0x01) != 0)
1400    }
1401    #[doc = "Bits 24:30 - Channel x Peripheral Hardware Request Line Identifier"]
1402    #[inline(always)]
1403    pub fn perid(&self) -> PERID_R {
1404        PERID_R::new(((self.bits >> 24) & 0x7f) as u8)
1405    }
1406}
1407impl W {
1408    #[doc = "Bit 0 - Channel x Transfer Type"]
1409    #[inline(always)]
1410    pub fn type_(&mut self) -> TYPE_W {
1411        TYPE_W { w: self }
1412    }
1413    #[doc = "Bits 1:2 - Channel x Memory Burst Size"]
1414    #[inline(always)]
1415    pub fn mbsize(&mut self) -> MBSIZE_W {
1416        MBSIZE_W { w: self }
1417    }
1418    #[doc = "Bit 4 - Channel x Synchronization"]
1419    #[inline(always)]
1420    pub fn dsync(&mut self) -> DSYNC_W {
1421        DSYNC_W { w: self }
1422    }
1423    #[doc = "Bit 6 - Channel x Software Request Trigger"]
1424    #[inline(always)]
1425    pub fn swreq(&mut self) -> SWREQ_W {
1426        SWREQ_W { w: self }
1427    }
1428    #[doc = "Bit 7 - Channel x Fill Block of memory"]
1429    #[inline(always)]
1430    pub fn memset(&mut self) -> MEMSET_W {
1431        MEMSET_W { w: self }
1432    }
1433    #[doc = "Bits 8:10 - Channel x Chunk Size"]
1434    #[inline(always)]
1435    pub fn csize(&mut self) -> CSIZE_W {
1436        CSIZE_W { w: self }
1437    }
1438    #[doc = "Bits 11:12 - Channel x Data Width"]
1439    #[inline(always)]
1440    pub fn dwidth(&mut self) -> DWIDTH_W {
1441        DWIDTH_W { w: self }
1442    }
1443    #[doc = "Bit 13 - Channel x Source Interface Identifier"]
1444    #[inline(always)]
1445    pub fn sif(&mut self) -> SIF_W {
1446        SIF_W { w: self }
1447    }
1448    #[doc = "Bit 14 - Channel x Destination Interface Identifier"]
1449    #[inline(always)]
1450    pub fn dif(&mut self) -> DIF_W {
1451        DIF_W { w: self }
1452    }
1453    #[doc = "Bits 16:17 - Channel x Source Addressing Mode"]
1454    #[inline(always)]
1455    pub fn sam(&mut self) -> SAM_W {
1456        SAM_W { w: self }
1457    }
1458    #[doc = "Bits 18:19 - Channel x Destination Addressing Mode"]
1459    #[inline(always)]
1460    pub fn dam(&mut self) -> DAM_W {
1461        DAM_W { w: self }
1462    }
1463    #[doc = "Bit 21 - Channel Initialization Terminated (this bit is read-only)"]
1464    #[inline(always)]
1465    pub fn initd(&mut self) -> INITD_W {
1466        INITD_W { w: self }
1467    }
1468    #[doc = "Bit 22 - Read in Progress (this bit is read-only)"]
1469    #[inline(always)]
1470    pub fn rdip(&mut self) -> RDIP_W {
1471        RDIP_W { w: self }
1472    }
1473    #[doc = "Bit 23 - Write in Progress (this bit is read-only)"]
1474    #[inline(always)]
1475    pub fn wrip(&mut self) -> WRIP_W {
1476        WRIP_W { w: self }
1477    }
1478    #[doc = "Bits 24:30 - Channel x Peripheral Hardware Request Line Identifier"]
1479    #[inline(always)]
1480    pub fn perid(&mut self) -> PERID_W {
1481        PERID_W { w: self }
1482    }
1483    #[doc = "Writes raw bits to the register."]
1484    #[inline(always)]
1485    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1486        self.0.bits(bits);
1487        self
1488    }
1489}
1490#[doc = "Channel Configuration Register (chid = 0)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xdmac_cc](index.html) module"]
1491pub struct XDMAC_CC_SPEC;
1492impl crate::RegisterSpec for XDMAC_CC_SPEC {
1493    type Ux = u32;
1494}
1495#[doc = "`read()` method returns [xdmac_cc::R](R) reader structure"]
1496impl crate::Readable for XDMAC_CC_SPEC {
1497    type Reader = R;
1498}
1499#[doc = "`write(|w| ..)` method takes [xdmac_cc::W](W) writer structure"]
1500impl crate::Writable for XDMAC_CC_SPEC {
1501    type Writer = W;
1502}
1503#[doc = "`reset()` method sets XDMAC_CC to value 0"]
1504impl crate::Resettable for XDMAC_CC_SPEC {
1505    #[inline(always)]
1506    fn reset_value() -> Self::Ux {
1507        0
1508    }
1509}
atsame70n21/xdmac/xdmac_chid/xdmac_cc.rs

atsame70n21/xdmac/xdmac_chid/
xdmac_cc.rs
