[][src]Type Definition atsame70n20b::isi::isi_cfg1::R

type R = R<u32, ISI_CFG1>;

Reader of register ISI_CFG1

Implementations

impl R[src]

pub fn hsync_pol(&self) -> HSYNC_POL_R[src]

Bit 2 - Horizontal Synchronization Polarity

pub fn vsync_pol(&self) -> VSYNC_POL_R[src]

Bit 3 - Vertical Synchronization Polarity

pub fn pixclk_pol(&self) -> PIXCLK_POL_R[src]

Bit 4 - Pixel Clock Polarity

pub fn grayle(&self) -> GRAYLE_R[src]

Bit 5 - Grayscale Little Endian

pub fn emb_sync(&self) -> EMB_SYNC_R[src]

Bit 6 - Embedded Synchronization

pub fn crc_sync(&self) -> CRC_SYNC_R[src]

Bit 7 - Embedded Synchronization Correction

pub fn frate(&self) -> FRATE_R[src]

Bits 8:10 - Frame Rate [0..7]

pub fn discr(&self) -> DISCR_R[src]

Bit 11 - Disable Codec Request

pub fn full(&self) -> FULL_R[src]

Bit 12 - Full Mode is Allowed

pub fn thmask(&self) -> THMASK_R[src]

Bits 13:14 - Threshold Mask

pub fn sld(&self) -> SLD_R[src]

Bits 16:23 - Start of Line Delay

pub fn sfd(&self) -> SFD_R[src]

Bits 24:31 - Start of Frame Delay