[−][src]Type Definition atsame70j21b::mcan0::mcan_ir::R
type R = R<u32, MCAN_IR>;
Reader of register MCAN_IR
Implementations
impl R[src]
pub fn rf0n(&self) -> RF0N_R[src]
Bit 0 - Receive FIFO 0 New Message
pub fn rf0w(&self) -> RF0W_R[src]
Bit 1 - Receive FIFO 0 Watermark Reached
pub fn rf0f(&self) -> RF0F_R[src]
Bit 2 - Receive FIFO 0 Full
pub fn rf0l(&self) -> RF0L_R[src]
Bit 3 - Receive FIFO 0 Message Lost
pub fn rf1n(&self) -> RF1N_R[src]
Bit 4 - Receive FIFO 1 New Message
pub fn rf1w(&self) -> RF1W_R[src]
Bit 5 - Receive FIFO 1 Watermark Reached
pub fn rf1f(&self) -> RF1F_R[src]
Bit 6 - Receive FIFO 1 Full
pub fn rf1l(&self) -> RF1L_R[src]
Bit 7 - Receive FIFO 1 Message Lost
pub fn hpm(&self) -> HPM_R[src]
Bit 8 - High Priority Message
pub fn tc(&self) -> TC_R[src]
Bit 9 - Transmission Completed
pub fn tcf(&self) -> TCF_R[src]
Bit 10 - Transmission Cancellation Finished
pub fn tfe(&self) -> TFE_R[src]
Bit 11 - Tx FIFO Empty
pub fn tefn(&self) -> TEFN_R[src]
Bit 12 - Tx Event FIFO New Entry
pub fn tefw(&self) -> TEFW_R[src]
Bit 13 - Tx Event FIFO Watermark Reached
pub fn teff(&self) -> TEFF_R[src]
Bit 14 - Tx Event FIFO Full
pub fn tefl(&self) -> TEFL_R[src]
Bit 15 - Tx Event FIFO Element Lost
pub fn tsw(&self) -> TSW_R[src]
Bit 16 - Timestamp Wraparound
pub fn mraf(&self) -> MRAF_R[src]
Bit 17 - Message RAM Access Failure
pub fn too(&self) -> TOO_R[src]
Bit 18 - Timeout Occurred
pub fn drx(&self) -> DRX_R[src]
Bit 19 - Message stored to Dedicated Receive Buffer
pub fn elo(&self) -> ELO_R[src]
Bit 22 - Error Logging Overflow
pub fn ep(&self) -> EP_R[src]
Bit 23 - Error Passive
pub fn ew(&self) -> EW_R[src]
Bit 24 - Warning Status
pub fn bo(&self) -> BO_R[src]
Bit 25 - Bus_Off Status
pub fn wdi(&self) -> WDI_R[src]
Bit 26 - Watchdog Interrupt
pub fn pea(&self) -> PEA_R[src]
Bit 27 - Protocol Error in Arbitration Phase
pub fn ped(&self) -> PED_R[src]
Bit 28 - Protocol Error in Data Phase
pub fn ara(&self) -> ARA_R[src]
Bit 29 - Access to Reserved Address