Struct atsame70j21b_pac::afec0::RegisterBlock[][src]

#[repr(C)]
pub struct RegisterBlock {
Show 29 fields pub cr: Reg<CR_SPEC>, pub mr: Reg<MR_SPEC>, pub emr: Reg<EMR_SPEC>, pub seq1r: Reg<SEQ1R_SPEC>, pub seq2r: Reg<SEQ2R_SPEC>, pub cher: Reg<CHER_SPEC>, pub chdr: Reg<CHDR_SPEC>, pub chsr: Reg<CHSR_SPEC>, pub lcdr: Reg<LCDR_SPEC>, pub ier: Reg<IER_SPEC>, pub idr: Reg<IDR_SPEC>, pub imr: Reg<IMR_SPEC>, pub isr: Reg<ISR_SPEC>, pub over: Reg<OVER_SPEC>, pub cwr: Reg<CWR_SPEC>, pub cgr: Reg<CGR_SPEC>, pub diffr: Reg<DIFFR_SPEC>, pub cselr: Reg<CSELR_SPEC>, pub cdr: Reg<CDR_SPEC>, pub cocr: Reg<COCR_SPEC>, pub tempmr: Reg<TEMPMR_SPEC>, pub tempcwr: Reg<TEMPCWR_SPEC>, pub acr: Reg<ACR_SPEC>, pub shmr: Reg<SHMR_SPEC>, pub cosr: Reg<COSR_SPEC>, pub cvr: Reg<CVR_SPEC>, pub cecr: Reg<CECR_SPEC>, pub wpmr: Reg<WPMR_SPEC>, pub wpsr: Reg<WPSR_SPEC>, // some fields omitted
}
Expand description

Register block

Fields

cr: Reg<CR_SPEC>

0x00 - AFEC Control Register

mr: Reg<MR_SPEC>

0x04 - AFEC Mode Register

emr: Reg<EMR_SPEC>

0x08 - AFEC Extended Mode Register

seq1r: Reg<SEQ1R_SPEC>

0x0c - AFEC Channel Sequence 1 Register

seq2r: Reg<SEQ2R_SPEC>

0x10 - AFEC Channel Sequence 2 Register

cher: Reg<CHER_SPEC>

0x14 - AFEC Channel Enable Register

chdr: Reg<CHDR_SPEC>

0x18 - AFEC Channel Disable Register

chsr: Reg<CHSR_SPEC>

0x1c - AFEC Channel Status Register

lcdr: Reg<LCDR_SPEC>

0x20 - AFEC Last Converted Data Register

ier: Reg<IER_SPEC>

0x24 - AFEC Interrupt Enable Register

idr: Reg<IDR_SPEC>

0x28 - AFEC Interrupt Disable Register

imr: Reg<IMR_SPEC>

0x2c - AFEC Interrupt Mask Register

isr: Reg<ISR_SPEC>

0x30 - AFEC Interrupt Status Register

over: Reg<OVER_SPEC>

0x4c - AFEC Overrun Status Register

cwr: Reg<CWR_SPEC>

0x50 - AFEC Compare Window Register

cgr: Reg<CGR_SPEC>

0x54 - AFEC Channel Gain Register

diffr: Reg<DIFFR_SPEC>

0x60 - AFEC Channel Differential Register

cselr: Reg<CSELR_SPEC>

0x64 - AFEC Channel Selection Register

cdr: Reg<CDR_SPEC>

0x68 - AFEC Channel Data Register

cocr: Reg<COCR_SPEC>

0x6c - AFEC Channel Offset Compensation Register

tempmr: Reg<TEMPMR_SPEC>

0x70 - AFEC Temperature Sensor Mode Register

tempcwr: Reg<TEMPCWR_SPEC>

0x74 - AFEC Temperature Compare Window Register

acr: Reg<ACR_SPEC>

0x94 - AFEC Analog Control Register

shmr: Reg<SHMR_SPEC>

0xa0 - AFEC Sample & Hold Mode Register

cosr: Reg<COSR_SPEC>

0xd0 - AFEC Correction Select Register

cvr: Reg<CVR_SPEC>

0xd4 - AFEC Correction Values Register

cecr: Reg<CECR_SPEC>

0xd8 - AFEC Channel Error Correction Register

wpmr: Reg<WPMR_SPEC>

0xe4 - AFEC Write Protection Mode Register

wpsr: Reg<WPSR_SPEC>

0xe8 - AFEC Write Protection Status Register

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