Type Definition atsame54n19a_pac::tcc0::ctrla::W[][src]

type W = W<u32, CTRLA>;

Writer for register CTRLA

Implementations

impl W[src]

pub fn swrst(&mut self) -> SWRST_W<'_>[src]

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>[src]

Bit 1 - Enable

pub fn resolution(&mut self) -> RESOLUTION_W<'_>[src]

Bits 5:6 - Enhanced Resolution

pub fn prescaler(&mut self) -> PRESCALER_W<'_>[src]

Bits 8:10 - Prescaler

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>[src]

Bit 11 - Run in Standby

pub fn prescsync(&mut self) -> PRESCSYNC_W<'_>[src]

Bits 12:13 - Prescaler and Counter Synchronization Selection

pub fn alock(&mut self) -> ALOCK_W<'_>[src]

Bit 14 - Auto Lock

pub fn msync(&mut self) -> MSYNC_W<'_>[src]

Bit 15 - Master Synchronization (only for TCC Slave Instance)

pub fn dmaos(&mut self) -> DMAOS_W<'_>[src]

Bit 23 - DMA One-shot Trigger Mode

pub fn cpten0(&mut self) -> CPTEN0_W<'_>[src]

Bit 24 - Capture Channel 0 Enable

pub fn cpten1(&mut self) -> CPTEN1_W<'_>[src]

Bit 25 - Capture Channel 1 Enable

pub fn cpten2(&mut self) -> CPTEN2_W<'_>[src]

Bit 26 - Capture Channel 2 Enable

pub fn cpten3(&mut self) -> CPTEN3_W<'_>[src]

Bit 27 - Capture Channel 3 Enable

pub fn cpten4(&mut self) -> CPTEN4_W<'_>[src]

Bit 28 - Capture Channel 4 Enable

pub fn cpten5(&mut self) -> CPTEN5_W<'_>[src]

Bit 29 - Capture Channel 5 Enable