Type Alias atsame54n::tcc0::ctrla::W

pub type W = W<CTRLA_SPEC>;

Register CTRLA writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn swrst(&mut self) -> SWRST_W<'_, CTRLA_SPEC, 0>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_, CTRLA_SPEC, 1>

Bit 1 - Enable

pub fn resolution(&mut self) -> RESOLUTION_W<'_, CTRLA_SPEC, 5>

Bits 5:6 - Enhanced Resolution

pub fn prescaler(&mut self) -> PRESCALER_W<'_, CTRLA_SPEC, 8>

Bits 8:10 - Prescaler

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_, CTRLA_SPEC, 11>

Bit 11 - Run in Standby

pub fn prescsync(&mut self) -> PRESCSYNC_W<'_, CTRLA_SPEC, 12>

Bits 12:13 - Prescaler and Counter Synchronization Selection

pub fn alock(&mut self) -> ALOCK_W<'_, CTRLA_SPEC, 14>

Bit 14 - Auto Lock

pub fn msync(&mut self) -> MSYNC_W<'_, CTRLA_SPEC, 15>

Bit 15 - Master Synchronization (only for TCC Slave Instance)

pub fn dmaos(&mut self) -> DMAOS_W<'_, CTRLA_SPEC, 23>

Bit 23 - DMA One-shot Trigger Mode

pub fn cpten0(&mut self) -> CPTEN0_W<'_, CTRLA_SPEC, 24>

Bit 24 - Capture Channel 0 Enable

pub fn cpten1(&mut self) -> CPTEN1_W<'_, CTRLA_SPEC, 25>

Bit 25 - Capture Channel 1 Enable

pub fn cpten2(&mut self) -> CPTEN2_W<'_, CTRLA_SPEC, 26>

Bit 26 - Capture Channel 2 Enable

pub fn cpten3(&mut self) -> CPTEN3_W<'_, CTRLA_SPEC, 27>

Bit 27 - Capture Channel 3 Enable

pub fn cpten4(&mut self) -> CPTEN4_W<'_, CTRLA_SPEC, 28>

Bit 28 - Capture Channel 4 Enable

pub fn cpten5(&mut self) -> CPTEN5_W<'_, CTRLA_SPEC, 29>

Bit 29 - Capture Channel 5 Enable

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual