Type Alias atsame54n::can0::ils::W

pub type W = W<ILS_SPEC>;

Register ILS writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn rf0nl(&mut self) -> RF0NL_W<'_, ILS_SPEC, 0>

Bit 0 - Rx FIFO 0 New Message Interrupt Line

pub fn rf0wl(&mut self) -> RF0WL_W<'_, ILS_SPEC, 1>

Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Line

pub fn rf0fl(&mut self) -> RF0FL_W<'_, ILS_SPEC, 2>

Bit 2 - Rx FIFO 0 Full Interrupt Line

pub fn rf0ll(&mut self) -> RF0LL_W<'_, ILS_SPEC, 3>

Bit 3 - Rx FIFO 0 Message Lost Interrupt Line

pub fn rf1nl(&mut self) -> RF1NL_W<'_, ILS_SPEC, 4>

Bit 4 - Rx FIFO 1 New Message Interrupt Line

pub fn rf1wl(&mut self) -> RF1WL_W<'_, ILS_SPEC, 5>

Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Line

pub fn rf1fl(&mut self) -> RF1FL_W<'_, ILS_SPEC, 6>

Bit 6 - Rx FIFO 1 FIFO Full Interrupt Line

pub fn rf1ll(&mut self) -> RF1LL_W<'_, ILS_SPEC, 7>

Bit 7 - Rx FIFO 1 Message Lost Interrupt Line

pub fn hpml(&mut self) -> HPML_W<'_, ILS_SPEC, 8>

Bit 8 - High Priority Message Interrupt Line

pub fn tcl(&mut self) -> TCL_W<'_, ILS_SPEC, 9>

Bit 9 - Timestamp Completed Interrupt Line

pub fn tcfl(&mut self) -> TCFL_W<'_, ILS_SPEC, 10>

Bit 10 - Transmission Cancellation Finished Interrupt Line

pub fn tfel(&mut self) -> TFEL_W<'_, ILS_SPEC, 11>

Bit 11 - Tx FIFO Empty Interrupt Line

pub fn tefnl(&mut self) -> TEFNL_W<'_, ILS_SPEC, 12>

Bit 12 - Tx Event FIFO New Entry Interrupt Line

pub fn tefwl(&mut self) -> TEFWL_W<'_, ILS_SPEC, 13>

Bit 13 - Tx Event FIFO Watermark Reached Interrupt Line

pub fn teffl(&mut self) -> TEFFL_W<'_, ILS_SPEC, 14>

Bit 14 - Tx Event FIFO Full Interrupt Line

pub fn tefll(&mut self) -> TEFLL_W<'_, ILS_SPEC, 15>

Bit 15 - Tx Event FIFO Element Lost Interrupt Line

pub fn tswl(&mut self) -> TSWL_W<'_, ILS_SPEC, 16>

Bit 16 - Timestamp Wraparound Interrupt Line

pub fn mrafl(&mut self) -> MRAFL_W<'_, ILS_SPEC, 17>

Bit 17 - Message RAM Access Failure Interrupt Line

pub fn tool(&mut self) -> TOOL_W<'_, ILS_SPEC, 18>

Bit 18 - Timeout Occurred Interrupt Line

pub fn drxl(&mut self) -> DRXL_W<'_, ILS_SPEC, 19>

Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Line

pub fn becl(&mut self) -> BECL_W<'_, ILS_SPEC, 20>

Bit 20 - Bit Error Corrected Interrupt Line

pub fn beul(&mut self) -> BEUL_W<'_, ILS_SPEC, 21>

Bit 21 - Bit Error Uncorrected Interrupt Line

pub fn elol(&mut self) -> ELOL_W<'_, ILS_SPEC, 22>

Bit 22 - Error Logging Overflow Interrupt Line

pub fn epl(&mut self) -> EPL_W<'_, ILS_SPEC, 23>

Bit 23 - Error Passive Interrupt Line

pub fn ewl(&mut self) -> EWL_W<'_, ILS_SPEC, 24>

Bit 24 - Warning Status Interrupt Line

pub fn bol(&mut self) -> BOL_W<'_, ILS_SPEC, 25>

Bit 25 - Bus_Off Status Interrupt Line

pub fn wdil(&mut self) -> WDIL_W<'_, ILS_SPEC, 26>

Bit 26 - Watchdog Interrupt Interrupt Line

pub fn peal(&mut self) -> PEAL_W<'_, ILS_SPEC, 27>

Bit 27 - Protocol Error in Arbitration Phase Line

pub fn pedl(&mut self) -> PEDL_W<'_, ILS_SPEC, 28>

Bit 28 - Protocol Error in Data Phase Line

pub fn aral(&mut self) -> ARAL_W<'_, ILS_SPEC, 29>

Bit 29 - Access to Reserved Address Line

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual