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#[doc = "Reader of register INTENSET"] pub type R = crate::R<u32, super::INTENSET>; #[doc = "Writer for register INTENSET"] pub type W = crate::W<u32, super::INTENSET>; #[doc = "Register INTENSET `reset()`'s with value 0"] impl crate::ResetValue for super::INTENSET { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `RXC`"] pub type RXC_R = crate::R<bool, bool>; #[doc = "Write proxy for field `RXC`"] pub struct RXC_W<'a> { w: &'a mut W, } impl<'a> RXC_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); self.w } } #[doc = "Reader of field `DRE`"] pub type DRE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DRE`"] pub struct DRE_W<'a> { w: &'a mut W, } impl<'a> DRE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); self.w } } #[doc = "Reader of field `TXC`"] pub type TXC_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TXC`"] pub struct TXC_W<'a> { w: &'a mut W, } impl<'a> TXC_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); self.w } } #[doc = "Reader of field `ERROR`"] pub type ERROR_R = crate::R<bool, bool>; #[doc = "Write proxy for field `ERROR`"] pub struct ERROR_W<'a> { w: &'a mut W, } impl<'a> ERROR_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); self.w } } #[doc = "Reader of field `CSRISE`"] pub type CSRISE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CSRISE`"] pub struct CSRISE_W<'a> { w: &'a mut W, } impl<'a> CSRISE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); self.w } } #[doc = "Reader of field `INSTREND`"] pub type INSTREND_R = crate::R<bool, bool>; #[doc = "Write proxy for field `INSTREND`"] pub struct INSTREND_W<'a> { w: &'a mut W, } impl<'a> INSTREND_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); self.w } } impl R { #[doc = "Bit 0 - Receive Data Register Full Interrupt Enable"] #[inline(always)] pub fn rxc(&self) -> RXC_R { RXC_R::new((self.bits & 0x01) != 0) } #[doc = "Bit 1 - Transmit Data Register Empty Interrupt Enable"] #[inline(always)] pub fn dre(&self) -> DRE_R { DRE_R::new(((self.bits >> 1) & 0x01) != 0) } #[doc = "Bit 2 - Transmission Complete Interrupt Enable"] #[inline(always)] pub fn txc(&self) -> TXC_R { TXC_R::new(((self.bits >> 2) & 0x01) != 0) } #[doc = "Bit 3 - Overrun Error Interrupt Enable"] #[inline(always)] pub fn error(&self) -> ERROR_R { ERROR_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bit 8 - Chip Select Rise Interrupt Enable"] #[inline(always)] pub fn csrise(&self) -> CSRISE_R { CSRISE_R::new(((self.bits >> 8) & 0x01) != 0) } #[doc = "Bit 10 - Instruction End Interrupt Enable"] #[inline(always)] pub fn instrend(&self) -> INSTREND_R { INSTREND_R::new(((self.bits >> 10) & 0x01) != 0) } } impl W { #[doc = "Bit 0 - Receive Data Register Full Interrupt Enable"] #[inline(always)] pub fn rxc(&mut self) -> RXC_W { RXC_W { w: self } } #[doc = "Bit 1 - Transmit Data Register Empty Interrupt Enable"] #[inline(always)] pub fn dre(&mut self) -> DRE_W { DRE_W { w: self } } #[doc = "Bit 2 - Transmission Complete Interrupt Enable"] #[inline(always)] pub fn txc(&mut self) -> TXC_W { TXC_W { w: self } } #[doc = "Bit 3 - Overrun Error Interrupt Enable"] #[inline(always)] pub fn error(&mut self) -> ERROR_W { ERROR_W { w: self } } #[doc = "Bit 8 - Chip Select Rise Interrupt Enable"] #[inline(always)] pub fn csrise(&mut self) -> CSRISE_W { CSRISE_W { w: self } } #[doc = "Bit 10 - Instruction End Interrupt Enable"] #[inline(always)] pub fn instrend(&mut self) -> INSTREND_W { INSTREND_W { w: self } } }