Crate atsame53n19a_pac[][src]

Peripheral access API for ATSAME53N19A microcontrollers (generated using svd2rust v0.17.0 (2bbb605 2020-05-16))

You can find an overview of the generated API here.

API features to be included in the next svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Re-exports

pub use self::Interrupt as interrupt;

Modules

ac

Analog Comparators

adc0

Analog Digital Converter

aes

Advanced Encryption Standard

ccl

Configurable Custom Logic

cmcc

Cortex M Cache Controller

core_debug

Core Debug Register

dac

Digital-to-Analog Converter

dmac

Direct Memory Access Controller

dsu

Device Service Unit

eic

External Interrupt Controller

etm

Embedded Trace Macrocell

evsys

Event System Interface

freqm

Frequency Meter

gclk

Generic Clock Generator

generic

Common register and bit access and modify traits

gmac

Ethernet MAC

hmatrix

HSB Matrix

i2s

Inter-IC Sound Interface

icm

Integrity Check Monitor

mclk

Main Clock

nvmctrl

Non-Volatile Memory Controller

osc32kctrl

32kHz Oscillators Control

oscctrl

Oscillators Control

pac

Peripheral Access Controller

pcc

Parallel Capture Controller

pdec

Quadrature Decodeur

pm

Power Manager

port

Port Module

qspi

Quad SPI interface

ramecc

RAM ECC

rstc

Reset Controller

rtc

Real-Time Counter

sdhc0

SD/MMC Host Controller

sercom0

Serial Communication Interface

supc

Supply Controller

sys_tick

System timer

system_control

System Control Registers

tc0

Basic Timer Counter

tcc0

Timer Counter Control

trng

True Random Generator

usb

Universal Serial Bus

wdt

Watchdog Timer

Structs

AC

Analog Comparators

ADC0

Analog Digital Converter

ADC1

Analog Digital Converter

AES

Advanced Encryption Standard

CBP

Cache and branch predictor maintenance operations

CCL

Configurable Custom Logic

CMCC

Cortex M Cache Controller

COREDEBUG

Core Debug Register

CPUID

CPUID

CorePeripherals

Core peripherals

DAC

Digital-to-Analog Converter

DCB

Debug Control Block

DMAC

Direct Memory Access Controller

DSU

Device Service Unit

DWT

Data Watchpoint and Trace unit

EIC

External Interrupt Controller

ETM

Embedded Trace Macrocell

EVSYS

Event System Interface

FPB

Flash Patch and Breakpoint unit

FPU

Floating Point Unit

FREQM

Frequency Meter

GCLK

Generic Clock Generator

GMAC

Ethernet MAC

HMATRIX

HSB Matrix

I2S

Inter-IC Sound Interface

ICM

Integrity Check Monitor

ITM

Instrumentation Trace Macrocell

MCLK

Main Clock

MPU

Memory Protection Unit

NVIC

Nested Vector Interrupt Controller

NVMCTRL

Non-Volatile Memory Controller

OSC32KCTRL

32kHz Oscillators Control

OSCCTRL

Oscillators Control

PAC

Peripheral Access Controller

PCC

Parallel Capture Controller

PDEC

Quadrature Decodeur

PM

Power Manager

PORT

Port Module

Peripherals

All the peripherals

QSPI

Quad SPI interface

RAMECC

RAM ECC

RSTC

Reset Controller

RTC

Real-Time Counter

SCB

System Control Block

SDHC0

SD/MMC Host Controller

SDHC1

SD/MMC Host Controller

SERCOM0

Serial Communication Interface

SERCOM1

Serial Communication Interface

SERCOM2

Serial Communication Interface

SERCOM3

Serial Communication Interface

SERCOM4

Serial Communication Interface

SERCOM5

Serial Communication Interface

SERCOM6

Serial Communication Interface

SERCOM7

Serial Communication Interface

SUPC

Supply Controller

SYST

SysTick: System Timer

SYSTEMCONTROL

System Control Registers

SYSTICK

System timer

TC0

Basic Timer Counter

TC1

Basic Timer Counter

TC2

Basic Timer Counter

TC3

Basic Timer Counter

TC4

Basic Timer Counter

TC5

Basic Timer Counter

TC6

Basic Timer Counter

TC7

Basic Timer Counter

TCC0

Timer Counter Control

TCC1

Timer Counter Control

TCC2

Timer Counter Control

TCC3

Timer Counter Control

TCC4

Timer Counter Control

TPIU

Trace Port Interface Unit

TRNG

True Random Generator

USB

Universal Serial Bus

WDT

Watchdog Timer

Enums

Interrupt

Enumeration of all the interrupts

Constants

NVIC_PRIO_BITS

Number available in the NVIC for configuring priority

Attribute Macros

interrupt

Attribute to declare an interrupt (AKA device-specific exception) handler