Type Alias atsamd51p::i2s::clkctrl::W

pub type W = W<CLKCTRL_SPEC>;

Register CLKCTRL[%s] writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn slotsize(&mut self) -> SLOTSIZE_W<'_, CLKCTRL_SPEC, 0>

Bits 0:1 - Slot Size

pub fn nbslots(&mut self) -> NBSLOTS_W<'_, CLKCTRL_SPEC, 2>

Bits 2:4 - Number of Slots in Frame

pub fn fswidth(&mut self) -> FSWIDTH_W<'_, CLKCTRL_SPEC, 5>

Bits 5:6 - Frame Sync Width

pub fn bitdelay(&mut self) -> BITDELAY_W<'_, CLKCTRL_SPEC, 7>

Bit 7 - Data Delay from Frame Sync

pub fn fssel(&mut self) -> FSSEL_W<'_, CLKCTRL_SPEC, 8>

Bit 8 - Frame Sync Select

pub fn fsinv(&mut self) -> FSINV_W<'_, CLKCTRL_SPEC, 9>

Bit 9 - Frame Sync Invert

pub fn fsoutinv(&mut self) -> FSOUTINV_W<'_, CLKCTRL_SPEC, 10>

Bit 10 - Frame Sync Output Invert

pub fn scksel(&mut self) -> SCKSEL_W<'_, CLKCTRL_SPEC, 11>

Bit 11 - Serial Clock Select

pub fn sckoutinv(&mut self) -> SCKOUTINV_W<'_, CLKCTRL_SPEC, 12>

Bit 12 - Serial Clock Output Invert

pub fn mcksel(&mut self) -> MCKSEL_W<'_, CLKCTRL_SPEC, 13>

Bit 13 - Master Clock Select

pub fn mcken(&mut self) -> MCKEN_W<'_, CLKCTRL_SPEC, 14>

Bit 14 - Master Clock Enable

pub fn mckoutinv(&mut self) -> MCKOUTINV_W<'_, CLKCTRL_SPEC, 15>

Bit 15 - Master Clock Output Invert

pub fn mckdiv(&mut self) -> MCKDIV_W<'_, CLKCTRL_SPEC, 16>

Bits 16:21 - Master Clock Division Factor

pub fn mckoutdiv(&mut self) -> MCKOUTDIV_W<'_, CLKCTRL_SPEC, 24>

Bits 24:29 - Master Clock Output Division Factor

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual