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#[doc = "Reader of register CTRLA"] pub type R = crate::R<u8, super::CTRLA>; #[doc = "Writer for register CTRLA"] pub type W = crate::W<u8, super::CTRLA>; #[doc = "Register CTRLA `reset()`'s with value 0"] impl crate::ResetValue for super::CTRLA { type Type = u8; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `SWRST`"] pub type SWRST_R = crate::R<bool, bool>; #[doc = "Write proxy for field `SWRST`"] pub struct SWRST_W<'a> { w: &'a mut W, } impl<'a> SWRST_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u8) & 0x01); self.w } } #[doc = "Reader of field `ENABLE`"] pub type ENABLE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `ENABLE`"] pub struct ENABLE_W<'a> { w: &'a mut W, } impl<'a> ENABLE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u8) & 0x01) << 1); self.w } } #[doc = "Clock Selection\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CKSEL_A { #[doc = "0: Clocked by GCLK"] CLK_GCLK = 0, #[doc = "1: Clocked by ULP32K"] CLK_ULP32K = 1, } impl From<CKSEL_A> for bool { #[inline(always)] fn from(variant: CKSEL_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `CKSEL`"] pub type CKSEL_R = crate::R<bool, CKSEL_A>; impl CKSEL_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> CKSEL_A { match self.bits { false => CKSEL_A::CLK_GCLK, true => CKSEL_A::CLK_ULP32K, } } #[doc = "Checks if the value of the field is `CLK_GCLK`"] #[inline(always)] pub fn is_clk_gclk(&self) -> bool { *self == CKSEL_A::CLK_GCLK } #[doc = "Checks if the value of the field is `CLK_ULP32K`"] #[inline(always)] pub fn is_clk_ulp32k(&self) -> bool { *self == CKSEL_A::CLK_ULP32K } } #[doc = "Write proxy for field `CKSEL`"] pub struct CKSEL_W<'a> { w: &'a mut W, } impl<'a> CKSEL_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: CKSEL_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Clocked by GCLK"] #[inline(always)] pub fn clk_gclk(self) -> &'a mut W { self.variant(CKSEL_A::CLK_GCLK) } #[doc = "Clocked by ULP32K"] #[inline(always)] pub fn clk_ulp32k(self) -> &'a mut W { self.variant(CKSEL_A::CLK_ULP32K) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u8) & 0x01) << 4); self.w } } impl R { #[doc = "Bit 0 - Software Reset"] #[inline(always)] pub fn swrst(&self) -> SWRST_R { SWRST_R::new((self.bits & 0x01) != 0) } #[doc = "Bit 1 - Enable"] #[inline(always)] pub fn enable(&self) -> ENABLE_R { ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) } #[doc = "Bit 4 - Clock Selection"] #[inline(always)] pub fn cksel(&self) -> CKSEL_R { CKSEL_R::new(((self.bits >> 4) & 0x01) != 0) } } impl W { #[doc = "Bit 0 - Software Reset"] #[inline(always)] pub fn swrst(&mut self) -> SWRST_W { SWRST_W { w: self } } #[doc = "Bit 1 - Enable"] #[inline(always)] pub fn enable(&mut self) -> ENABLE_W { ENABLE_W { w: self } } #[doc = "Bit 4 - Clock Selection"] #[inline(always)] pub fn cksel(&mut self) -> CKSEL_W { CKSEL_W { w: self } } }