atsamd51j19a/tc0/count32/
intenset.rs

1#[doc = "Reader of register INTENSET"]
2pub type R = crate::R<u8, super::INTENSET>;
3#[doc = "Writer for register INTENSET"]
4pub type W = crate::W<u8, super::INTENSET>;
5#[doc = "Register INTENSET `reset()`'s with value 0"]
6impl crate::ResetValue for super::INTENSET {
7    type Type = u8;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `OVF`"]
14pub type OVF_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `OVF`"]
16pub struct OVF_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> OVF_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u8) & 0x01);
34        self.w
35    }
36}
37#[doc = "Reader of field `ERR`"]
38pub type ERR_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `ERR`"]
40pub struct ERR_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> ERR_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u8) & 0x01) << 1);
58        self.w
59    }
60}
61#[doc = "Reader of field `MC0`"]
62pub type MC0_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `MC0`"]
64pub struct MC0_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> MC0_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u8) & 0x01) << 4);
82        self.w
83    }
84}
85#[doc = "Reader of field `MC1`"]
86pub type MC1_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `MC1`"]
88pub struct MC1_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> MC1_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u8) & 0x01) << 5);
106        self.w
107    }
108}
109impl R {
110    #[doc = "Bit 0 - OVF Interrupt Enable"]
111    #[inline(always)]
112    pub fn ovf(&self) -> OVF_R {
113        OVF_R::new((self.bits & 0x01) != 0)
114    }
115    #[doc = "Bit 1 - ERR Interrupt Enable"]
116    #[inline(always)]
117    pub fn err(&self) -> ERR_R {
118        ERR_R::new(((self.bits >> 1) & 0x01) != 0)
119    }
120    #[doc = "Bit 4 - MC Interrupt Enable 0"]
121    #[inline(always)]
122    pub fn mc0(&self) -> MC0_R {
123        MC0_R::new(((self.bits >> 4) & 0x01) != 0)
124    }
125    #[doc = "Bit 5 - MC Interrupt Enable 1"]
126    #[inline(always)]
127    pub fn mc1(&self) -> MC1_R {
128        MC1_R::new(((self.bits >> 5) & 0x01) != 0)
129    }
130}
131impl W {
132    #[doc = "Bit 0 - OVF Interrupt Enable"]
133    #[inline(always)]
134    pub fn ovf(&mut self) -> OVF_W {
135        OVF_W { w: self }
136    }
137    #[doc = "Bit 1 - ERR Interrupt Enable"]
138    #[inline(always)]
139    pub fn err(&mut self) -> ERR_W {
140        ERR_W { w: self }
141    }
142    #[doc = "Bit 4 - MC Interrupt Enable 0"]
143    #[inline(always)]
144    pub fn mc0(&mut self) -> MC0_W {
145        MC0_W { w: self }
146    }
147    #[doc = "Bit 5 - MC Interrupt Enable 1"]
148    #[inline(always)]
149    pub fn mc1(&mut self) -> MC1_W {
150        MC1_W { w: self }
151    }
152}
atsamd51j19a/tc0/count32/intenset.rs

atsamd51j19a/tc0/count32/
intenset.rs
