atsamd21e18a/port/
dirclr.rs

1#[doc = "Reader of register DIRCLR%s"]
2pub type R = crate::R<u32, super::DIRCLR>;
3#[doc = "Writer for register DIRCLR%s"]
4pub type W = crate::W<u32, super::DIRCLR>;
5#[doc = "Register DIRCLR%s `reset()`'s with value 0"]
6impl crate::ResetValue for super::DIRCLR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `DIRCLR`"]
14pub type DIRCLR_R = crate::R<u32, u32>;
15#[doc = "Write proxy for field `DIRCLR`"]
16pub struct DIRCLR_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> DIRCLR_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u32) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
24        self.w
25    }
26}
27impl R {
28    #[doc = "Bits 0:31 - Port Data Direction Clear"]
29    #[inline(always)]
30    pub fn dirclr(&self) -> DIRCLR_R {
31        DIRCLR_R::new((self.bits & 0xffff_ffff) as u32)
32    }
33}
34impl W {
35    #[doc = "Bits 0:31 - Port Data Direction Clear"]
36    #[inline(always)]
37    pub fn dirclr(&mut self) -> DIRCLR_W {
38        DIRCLR_W { w: self }
39    }
40}
atsamd21e18a/port/dirclr.rs

atsamd21e18a/port/
dirclr.rs
