atsamd11c14a/rtc/mode2/
ctrl.rs

1#[doc = "Reader of register CTRL"]
2pub type R = crate::R<u16, super::CTRL>;
3#[doc = "Writer for register CTRL"]
4pub type W = crate::W<u16, super::CTRL>;
5#[doc = "Register CTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::CTRL {
7    type Type = u16;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Write proxy for field `SWRST`"]
14pub struct SWRST_W<'a> {
15    w: &'a mut W,
16}
17impl<'a> SWRST_W<'a> {
18    #[doc = r"Sets the field bit"]
19    #[inline(always)]
20    pub fn set_bit(self) -> &'a mut W {
21        self.bit(true)
22    }
23    #[doc = r"Clears the field bit"]
24    #[inline(always)]
25    pub fn clear_bit(self) -> &'a mut W {
26        self.bit(false)
27    }
28    #[doc = r"Writes raw bits to the field"]
29    #[inline(always)]
30    pub fn bit(self, value: bool) -> &'a mut W {
31        self.w.bits = (self.w.bits & !0x01) | ((value as u16) & 0x01);
32        self.w
33    }
34}
35#[doc = "Reader of field `ENABLE`"]
36pub type ENABLE_R = crate::R<bool, bool>;
37#[doc = "Write proxy for field `ENABLE`"]
38pub struct ENABLE_W<'a> {
39    w: &'a mut W,
40}
41impl<'a> ENABLE_W<'a> {
42    #[doc = r"Sets the field bit"]
43    #[inline(always)]
44    pub fn set_bit(self) -> &'a mut W {
45        self.bit(true)
46    }
47    #[doc = r"Clears the field bit"]
48    #[inline(always)]
49    pub fn clear_bit(self) -> &'a mut W {
50        self.bit(false)
51    }
52    #[doc = r"Writes raw bits to the field"]
53    #[inline(always)]
54    pub fn bit(self, value: bool) -> &'a mut W {
55        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u16) & 0x01) << 1);
56        self.w
57    }
58}
59#[doc = "Operating Mode\n\nValue on reset: 0"]
60#[derive(Clone, Copy, Debug, PartialEq)]
61#[repr(u8)]
62pub enum MODE_A {
63    #[doc = "0: Mode 0: 32-bit Counter"]
64    COUNT32 = 0,
65    #[doc = "1: Mode 1: 16-bit Counter"]
66    COUNT16 = 1,
67    #[doc = "2: Mode 2: Clock/Calendar"]
68    CLOCK = 2,
69}
70impl From<MODE_A> for u8 {
71    #[inline(always)]
72    fn from(variant: MODE_A) -> Self {
73        variant as _
74    }
75}
76#[doc = "Reader of field `MODE`"]
77pub type MODE_R = crate::R<u8, MODE_A>;
78impl MODE_R {
79    #[doc = r"Get enumerated values variant"]
80    #[inline(always)]
81    pub fn variant(&self) -> crate::Variant<u8, MODE_A> {
82        use crate::Variant::*;
83        match self.bits {
84            0 => Val(MODE_A::COUNT32),
85            1 => Val(MODE_A::COUNT16),
86            2 => Val(MODE_A::CLOCK),
87            i => Res(i),
88        }
89    }
90    #[doc = "Checks if the value of the field is `COUNT32`"]
91    #[inline(always)]
92    pub fn is_count32(&self) -> bool {
93        *self == MODE_A::COUNT32
94    }
95    #[doc = "Checks if the value of the field is `COUNT16`"]
96    #[inline(always)]
97    pub fn is_count16(&self) -> bool {
98        *self == MODE_A::COUNT16
99    }
100    #[doc = "Checks if the value of the field is `CLOCK`"]
101    #[inline(always)]
102    pub fn is_clock(&self) -> bool {
103        *self == MODE_A::CLOCK
104    }
105}
106#[doc = "Write proxy for field `MODE`"]
107pub struct MODE_W<'a> {
108    w: &'a mut W,
109}
110impl<'a> MODE_W<'a> {
111    #[doc = r"Writes `variant` to the field"]
112    #[inline(always)]
113    pub fn variant(self, variant: MODE_A) -> &'a mut W {
114        unsafe { self.bits(variant.into()) }
115    }
116    #[doc = "Mode 0: 32-bit Counter"]
117    #[inline(always)]
118    pub fn count32(self) -> &'a mut W {
119        self.variant(MODE_A::COUNT32)
120    }
121    #[doc = "Mode 1: 16-bit Counter"]
122    #[inline(always)]
123    pub fn count16(self) -> &'a mut W {
124        self.variant(MODE_A::COUNT16)
125    }
126    #[doc = "Mode 2: Clock/Calendar"]
127    #[inline(always)]
128    pub fn clock(self) -> &'a mut W {
129        self.variant(MODE_A::CLOCK)
130    }
131    #[doc = r"Writes raw bits to the field"]
132    #[inline(always)]
133    pub unsafe fn bits(self, value: u8) -> &'a mut W {
134        self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u16) & 0x03) << 2);
135        self.w
136    }
137}
138#[doc = "Reader of field `CLKREP`"]
139pub type CLKREP_R = crate::R<bool, bool>;
140#[doc = "Write proxy for field `CLKREP`"]
141pub struct CLKREP_W<'a> {
142    w: &'a mut W,
143}
144impl<'a> CLKREP_W<'a> {
145    #[doc = r"Sets the field bit"]
146    #[inline(always)]
147    pub fn set_bit(self) -> &'a mut W {
148        self.bit(true)
149    }
150    #[doc = r"Clears the field bit"]
151    #[inline(always)]
152    pub fn clear_bit(self) -> &'a mut W {
153        self.bit(false)
154    }
155    #[doc = r"Writes raw bits to the field"]
156    #[inline(always)]
157    pub fn bit(self, value: bool) -> &'a mut W {
158        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u16) & 0x01) << 6);
159        self.w
160    }
161}
162#[doc = "Reader of field `MATCHCLR`"]
163pub type MATCHCLR_R = crate::R<bool, bool>;
164#[doc = "Write proxy for field `MATCHCLR`"]
165pub struct MATCHCLR_W<'a> {
166    w: &'a mut W,
167}
168impl<'a> MATCHCLR_W<'a> {
169    #[doc = r"Sets the field bit"]
170    #[inline(always)]
171    pub fn set_bit(self) -> &'a mut W {
172        self.bit(true)
173    }
174    #[doc = r"Clears the field bit"]
175    #[inline(always)]
176    pub fn clear_bit(self) -> &'a mut W {
177        self.bit(false)
178    }
179    #[doc = r"Writes raw bits to the field"]
180    #[inline(always)]
181    pub fn bit(self, value: bool) -> &'a mut W {
182        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u16) & 0x01) << 7);
183        self.w
184    }
185}
186#[doc = "Prescaler\n\nValue on reset: 0"]
187#[derive(Clone, Copy, Debug, PartialEq)]
188#[repr(u8)]
189pub enum PRESCALER_A {
190    #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"]
191    DIV1 = 0,
192    #[doc = "1: CLK_RTC_CNT = GCLK_RTC/2"]
193    DIV2 = 1,
194    #[doc = "2: CLK_RTC_CNT = GCLK_RTC/4"]
195    DIV4 = 2,
196    #[doc = "3: CLK_RTC_CNT = GCLK_RTC/8"]
197    DIV8 = 3,
198    #[doc = "4: CLK_RTC_CNT = GCLK_RTC/16"]
199    DIV16 = 4,
200    #[doc = "5: CLK_RTC_CNT = GCLK_RTC/32"]
201    DIV32 = 5,
202    #[doc = "6: CLK_RTC_CNT = GCLK_RTC/64"]
203    DIV64 = 6,
204    #[doc = "7: CLK_RTC_CNT = GCLK_RTC/128"]
205    DIV128 = 7,
206    #[doc = "8: CLK_RTC_CNT = GCLK_RTC/256"]
207    DIV256 = 8,
208    #[doc = "9: CLK_RTC_CNT = GCLK_RTC/512"]
209    DIV512 = 9,
210    #[doc = "10: CLK_RTC_CNT = GCLK_RTC/1024"]
211    DIV1024 = 10,
212}
213impl From<PRESCALER_A> for u8 {
214    #[inline(always)]
215    fn from(variant: PRESCALER_A) -> Self {
216        variant as _
217    }
218}
219#[doc = "Reader of field `PRESCALER`"]
220pub type PRESCALER_R = crate::R<u8, PRESCALER_A>;
221impl PRESCALER_R {
222    #[doc = r"Get enumerated values variant"]
223    #[inline(always)]
224    pub fn variant(&self) -> crate::Variant<u8, PRESCALER_A> {
225        use crate::Variant::*;
226        match self.bits {
227            0 => Val(PRESCALER_A::DIV1),
228            1 => Val(PRESCALER_A::DIV2),
229            2 => Val(PRESCALER_A::DIV4),
230            3 => Val(PRESCALER_A::DIV8),
231            4 => Val(PRESCALER_A::DIV16),
232            5 => Val(PRESCALER_A::DIV32),
233            6 => Val(PRESCALER_A::DIV64),
234            7 => Val(PRESCALER_A::DIV128),
235            8 => Val(PRESCALER_A::DIV256),
236            9 => Val(PRESCALER_A::DIV512),
237            10 => Val(PRESCALER_A::DIV1024),
238            i => Res(i),
239        }
240    }
241    #[doc = "Checks if the value of the field is `DIV1`"]
242    #[inline(always)]
243    pub fn is_div1(&self) -> bool {
244        *self == PRESCALER_A::DIV1
245    }
246    #[doc = "Checks if the value of the field is `DIV2`"]
247    #[inline(always)]
248    pub fn is_div2(&self) -> bool {
249        *self == PRESCALER_A::DIV2
250    }
251    #[doc = "Checks if the value of the field is `DIV4`"]
252    #[inline(always)]
253    pub fn is_div4(&self) -> bool {
254        *self == PRESCALER_A::DIV4
255    }
256    #[doc = "Checks if the value of the field is `DIV8`"]
257    #[inline(always)]
258    pub fn is_div8(&self) -> bool {
259        *self == PRESCALER_A::DIV8
260    }
261    #[doc = "Checks if the value of the field is `DIV16`"]
262    #[inline(always)]
263    pub fn is_div16(&self) -> bool {
264        *self == PRESCALER_A::DIV16
265    }
266    #[doc = "Checks if the value of the field is `DIV32`"]
267    #[inline(always)]
268    pub fn is_div32(&self) -> bool {
269        *self == PRESCALER_A::DIV32
270    }
271    #[doc = "Checks if the value of the field is `DIV64`"]
272    #[inline(always)]
273    pub fn is_div64(&self) -> bool {
274        *self == PRESCALER_A::DIV64
275    }
276    #[doc = "Checks if the value of the field is `DIV128`"]
277    #[inline(always)]
278    pub fn is_div128(&self) -> bool {
279        *self == PRESCALER_A::DIV128
280    }
281    #[doc = "Checks if the value of the field is `DIV256`"]
282    #[inline(always)]
283    pub fn is_div256(&self) -> bool {
284        *self == PRESCALER_A::DIV256
285    }
286    #[doc = "Checks if the value of the field is `DIV512`"]
287    #[inline(always)]
288    pub fn is_div512(&self) -> bool {
289        *self == PRESCALER_A::DIV512
290    }
291    #[doc = "Checks if the value of the field is `DIV1024`"]
292    #[inline(always)]
293    pub fn is_div1024(&self) -> bool {
294        *self == PRESCALER_A::DIV1024
295    }
296}
297#[doc = "Write proxy for field `PRESCALER`"]
298pub struct PRESCALER_W<'a> {
299    w: &'a mut W,
300}
301impl<'a> PRESCALER_W<'a> {
302    #[doc = r"Writes `variant` to the field"]
303    #[inline(always)]
304    pub fn variant(self, variant: PRESCALER_A) -> &'a mut W {
305        unsafe { self.bits(variant.into()) }
306    }
307    #[doc = "CLK_RTC_CNT = GCLK_RTC/1"]
308    #[inline(always)]
309    pub fn div1(self) -> &'a mut W {
310        self.variant(PRESCALER_A::DIV1)
311    }
312    #[doc = "CLK_RTC_CNT = GCLK_RTC/2"]
313    #[inline(always)]
314    pub fn div2(self) -> &'a mut W {
315        self.variant(PRESCALER_A::DIV2)
316    }
317    #[doc = "CLK_RTC_CNT = GCLK_RTC/4"]
318    #[inline(always)]
319    pub fn div4(self) -> &'a mut W {
320        self.variant(PRESCALER_A::DIV4)
321    }
322    #[doc = "CLK_RTC_CNT = GCLK_RTC/8"]
323    #[inline(always)]
324    pub fn div8(self) -> &'a mut W {
325        self.variant(PRESCALER_A::DIV8)
326    }
327    #[doc = "CLK_RTC_CNT = GCLK_RTC/16"]
328    #[inline(always)]
329    pub fn div16(self) -> &'a mut W {
330        self.variant(PRESCALER_A::DIV16)
331    }
332    #[doc = "CLK_RTC_CNT = GCLK_RTC/32"]
333    #[inline(always)]
334    pub fn div32(self) -> &'a mut W {
335        self.variant(PRESCALER_A::DIV32)
336    }
337    #[doc = "CLK_RTC_CNT = GCLK_RTC/64"]
338    #[inline(always)]
339    pub fn div64(self) -> &'a mut W {
340        self.variant(PRESCALER_A::DIV64)
341    }
342    #[doc = "CLK_RTC_CNT = GCLK_RTC/128"]
343    #[inline(always)]
344    pub fn div128(self) -> &'a mut W {
345        self.variant(PRESCALER_A::DIV128)
346    }
347    #[doc = "CLK_RTC_CNT = GCLK_RTC/256"]
348    #[inline(always)]
349    pub fn div256(self) -> &'a mut W {
350        self.variant(PRESCALER_A::DIV256)
351    }
352    #[doc = "CLK_RTC_CNT = GCLK_RTC/512"]
353    #[inline(always)]
354    pub fn div512(self) -> &'a mut W {
355        self.variant(PRESCALER_A::DIV512)
356    }
357    #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"]
358    #[inline(always)]
359    pub fn div1024(self) -> &'a mut W {
360        self.variant(PRESCALER_A::DIV1024)
361    }
362    #[doc = r"Writes raw bits to the field"]
363    #[inline(always)]
364    pub unsafe fn bits(self, value: u8) -> &'a mut W {
365        self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u16) & 0x0f) << 8);
366        self.w
367    }
368}
369impl R {
370    #[doc = "Bit 1 - Enable"]
371    #[inline(always)]
372    pub fn enable(&self) -> ENABLE_R {
373        ENABLE_R::new(((self.bits >> 1) & 0x01) != 0)
374    }
375    #[doc = "Bits 2:3 - Operating Mode"]
376    #[inline(always)]
377    pub fn mode(&self) -> MODE_R {
378        MODE_R::new(((self.bits >> 2) & 0x03) as u8)
379    }
380    #[doc = "Bit 6 - Clock Representation"]
381    #[inline(always)]
382    pub fn clkrep(&self) -> CLKREP_R {
383        CLKREP_R::new(((self.bits >> 6) & 0x01) != 0)
384    }
385    #[doc = "Bit 7 - Clear on Match"]
386    #[inline(always)]
387    pub fn matchclr(&self) -> MATCHCLR_R {
388        MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0)
389    }
390    #[doc = "Bits 8:11 - Prescaler"]
391    #[inline(always)]
392    pub fn prescaler(&self) -> PRESCALER_R {
393        PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8)
394    }
395}
396impl W {
397    #[doc = "Bit 0 - Software Reset"]
398    #[inline(always)]
399    pub fn swrst(&mut self) -> SWRST_W {
400        SWRST_W { w: self }
401    }
402    #[doc = "Bit 1 - Enable"]
403    #[inline(always)]
404    pub fn enable(&mut self) -> ENABLE_W {
405        ENABLE_W { w: self }
406    }
407    #[doc = "Bits 2:3 - Operating Mode"]
408    #[inline(always)]
409    pub fn mode(&mut self) -> MODE_W {
410        MODE_W { w: self }
411    }
412    #[doc = "Bit 6 - Clock Representation"]
413    #[inline(always)]
414    pub fn clkrep(&mut self) -> CLKREP_W {
415        CLKREP_W { w: self }
416    }
417    #[doc = "Bit 7 - Clear on Match"]
418    #[inline(always)]
419    pub fn matchclr(&mut self) -> MATCHCLR_W {
420        MATCHCLR_W { w: self }
421    }
422    #[doc = "Bits 8:11 - Prescaler"]
423    #[inline(always)]
424    pub fn prescaler(&mut self) -> PRESCALER_W {
425        PRESCALER_W { w: self }
426    }
427}
atsamd11c14a/rtc/mode2/ctrl.rs

atsamd11c14a/rtc/mode2/
ctrl.rs
