atsamd11c14a/dmac/
prictrl0.rs

1#[doc = "Reader of register PRICTRL0"]
2pub type R = crate::R<u32, super::PRICTRL0>;
3#[doc = "Writer for register PRICTRL0"]
4pub type W = crate::W<u32, super::PRICTRL0>;
5#[doc = "Register PRICTRL0 `reset()`'s with value 0"]
6impl crate::ResetValue for super::PRICTRL0 {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `LVLPRI0`"]
14pub type LVLPRI0_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `LVLPRI0`"]
16pub struct LVLPRI0_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> LVLPRI0_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
24        self.w
25    }
26}
27#[doc = "Reader of field `RRLVLEN0`"]
28pub type RRLVLEN0_R = crate::R<bool, bool>;
29#[doc = "Write proxy for field `RRLVLEN0`"]
30pub struct RRLVLEN0_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> RRLVLEN0_W<'a> {
34    #[doc = r"Sets the field bit"]
35    #[inline(always)]
36    pub fn set_bit(self) -> &'a mut W {
37        self.bit(true)
38    }
39    #[doc = r"Clears the field bit"]
40    #[inline(always)]
41    pub fn clear_bit(self) -> &'a mut W {
42        self.bit(false)
43    }
44    #[doc = r"Writes raw bits to the field"]
45    #[inline(always)]
46    pub fn bit(self, value: bool) -> &'a mut W {
47        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
48        self.w
49    }
50}
51#[doc = "Reader of field `LVLPRI1`"]
52pub type LVLPRI1_R = crate::R<u8, u8>;
53#[doc = "Write proxy for field `LVLPRI1`"]
54pub struct LVLPRI1_W<'a> {
55    w: &'a mut W,
56}
57impl<'a> LVLPRI1_W<'a> {
58    #[doc = r"Writes raw bits to the field"]
59    #[inline(always)]
60    pub unsafe fn bits(self, value: u8) -> &'a mut W {
61        self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u32) & 0x07) << 8);
62        self.w
63    }
64}
65#[doc = "Reader of field `RRLVLEN1`"]
66pub type RRLVLEN1_R = crate::R<bool, bool>;
67#[doc = "Write proxy for field `RRLVLEN1`"]
68pub struct RRLVLEN1_W<'a> {
69    w: &'a mut W,
70}
71impl<'a> RRLVLEN1_W<'a> {
72    #[doc = r"Sets the field bit"]
73    #[inline(always)]
74    pub fn set_bit(self) -> &'a mut W {
75        self.bit(true)
76    }
77    #[doc = r"Clears the field bit"]
78    #[inline(always)]
79    pub fn clear_bit(self) -> &'a mut W {
80        self.bit(false)
81    }
82    #[doc = r"Writes raw bits to the field"]
83    #[inline(always)]
84    pub fn bit(self, value: bool) -> &'a mut W {
85        self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
86        self.w
87    }
88}
89#[doc = "Reader of field `LVLPRI2`"]
90pub type LVLPRI2_R = crate::R<u8, u8>;
91#[doc = "Write proxy for field `LVLPRI2`"]
92pub struct LVLPRI2_W<'a> {
93    w: &'a mut W,
94}
95impl<'a> LVLPRI2_W<'a> {
96    #[doc = r"Writes raw bits to the field"]
97    #[inline(always)]
98    pub unsafe fn bits(self, value: u8) -> &'a mut W {
99        self.w.bits = (self.w.bits & !(0x07 << 16)) | (((value as u32) & 0x07) << 16);
100        self.w
101    }
102}
103#[doc = "Reader of field `RRLVLEN2`"]
104pub type RRLVLEN2_R = crate::R<bool, bool>;
105#[doc = "Write proxy for field `RRLVLEN2`"]
106pub struct RRLVLEN2_W<'a> {
107    w: &'a mut W,
108}
109impl<'a> RRLVLEN2_W<'a> {
110    #[doc = r"Sets the field bit"]
111    #[inline(always)]
112    pub fn set_bit(self) -> &'a mut W {
113        self.bit(true)
114    }
115    #[doc = r"Clears the field bit"]
116    #[inline(always)]
117    pub fn clear_bit(self) -> &'a mut W {
118        self.bit(false)
119    }
120    #[doc = r"Writes raw bits to the field"]
121    #[inline(always)]
122    pub fn bit(self, value: bool) -> &'a mut W {
123        self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
124        self.w
125    }
126}
127#[doc = "Reader of field `LVLPRI3`"]
128pub type LVLPRI3_R = crate::R<u8, u8>;
129#[doc = "Write proxy for field `LVLPRI3`"]
130pub struct LVLPRI3_W<'a> {
131    w: &'a mut W,
132}
133impl<'a> LVLPRI3_W<'a> {
134    #[doc = r"Writes raw bits to the field"]
135    #[inline(always)]
136    pub unsafe fn bits(self, value: u8) -> &'a mut W {
137        self.w.bits = (self.w.bits & !(0x07 << 24)) | (((value as u32) & 0x07) << 24);
138        self.w
139    }
140}
141#[doc = "Reader of field `RRLVLEN3`"]
142pub type RRLVLEN3_R = crate::R<bool, bool>;
143#[doc = "Write proxy for field `RRLVLEN3`"]
144pub struct RRLVLEN3_W<'a> {
145    w: &'a mut W,
146}
147impl<'a> RRLVLEN3_W<'a> {
148    #[doc = r"Sets the field bit"]
149    #[inline(always)]
150    pub fn set_bit(self) -> &'a mut W {
151        self.bit(true)
152    }
153    #[doc = r"Clears the field bit"]
154    #[inline(always)]
155    pub fn clear_bit(self) -> &'a mut W {
156        self.bit(false)
157    }
158    #[doc = r"Writes raw bits to the field"]
159    #[inline(always)]
160    pub fn bit(self, value: bool) -> &'a mut W {
161        self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
162        self.w
163    }
164}
165impl R {
166    #[doc = "Bits 0:2 - Level 0 Channel Priority Number"]
167    #[inline(always)]
168    pub fn lvlpri0(&self) -> LVLPRI0_R {
169        LVLPRI0_R::new((self.bits & 0x07) as u8)
170    }
171    #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"]
172    #[inline(always)]
173    pub fn rrlvlen0(&self) -> RRLVLEN0_R {
174        RRLVLEN0_R::new(((self.bits >> 7) & 0x01) != 0)
175    }
176    #[doc = "Bits 8:10 - Level 1 Channel Priority Number"]
177    #[inline(always)]
178    pub fn lvlpri1(&self) -> LVLPRI1_R {
179        LVLPRI1_R::new(((self.bits >> 8) & 0x07) as u8)
180    }
181    #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"]
182    #[inline(always)]
183    pub fn rrlvlen1(&self) -> RRLVLEN1_R {
184        RRLVLEN1_R::new(((self.bits >> 15) & 0x01) != 0)
185    }
186    #[doc = "Bits 16:18 - Level 2 Channel Priority Number"]
187    #[inline(always)]
188    pub fn lvlpri2(&self) -> LVLPRI2_R {
189        LVLPRI2_R::new(((self.bits >> 16) & 0x07) as u8)
190    }
191    #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"]
192    #[inline(always)]
193    pub fn rrlvlen2(&self) -> RRLVLEN2_R {
194        RRLVLEN2_R::new(((self.bits >> 23) & 0x01) != 0)
195    }
196    #[doc = "Bits 24:26 - Level 3 Channel Priority Number"]
197    #[inline(always)]
198    pub fn lvlpri3(&self) -> LVLPRI3_R {
199        LVLPRI3_R::new(((self.bits >> 24) & 0x07) as u8)
200    }
201    #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"]
202    #[inline(always)]
203    pub fn rrlvlen3(&self) -> RRLVLEN3_R {
204        RRLVLEN3_R::new(((self.bits >> 31) & 0x01) != 0)
205    }
206}
207impl W {
208    #[doc = "Bits 0:2 - Level 0 Channel Priority Number"]
209    #[inline(always)]
210    pub fn lvlpri0(&mut self) -> LVLPRI0_W {
211        LVLPRI0_W { w: self }
212    }
213    #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"]
214    #[inline(always)]
215    pub fn rrlvlen0(&mut self) -> RRLVLEN0_W {
216        RRLVLEN0_W { w: self }
217    }
218    #[doc = "Bits 8:10 - Level 1 Channel Priority Number"]
219    #[inline(always)]
220    pub fn lvlpri1(&mut self) -> LVLPRI1_W {
221        LVLPRI1_W { w: self }
222    }
223    #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"]
224    #[inline(always)]
225    pub fn rrlvlen1(&mut self) -> RRLVLEN1_W {
226        RRLVLEN1_W { w: self }
227    }
228    #[doc = "Bits 16:18 - Level 2 Channel Priority Number"]
229    #[inline(always)]
230    pub fn lvlpri2(&mut self) -> LVLPRI2_W {
231        LVLPRI2_W { w: self }
232    }
233    #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"]
234    #[inline(always)]
235    pub fn rrlvlen2(&mut self) -> RRLVLEN2_W {
236        RRLVLEN2_W { w: self }
237    }
238    #[doc = "Bits 24:26 - Level 3 Channel Priority Number"]
239    #[inline(always)]
240    pub fn lvlpri3(&mut self) -> LVLPRI3_W {
241        LVLPRI3_W { w: self }
242    }
243    #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"]
244    #[inline(always)]
245    pub fn rrlvlen3(&mut self) -> RRLVLEN3_W {
246        RRLVLEN3_W { w: self }
247    }
248}
atsamd11c14a/dmac/prictrl0.rs

atsamd11c14a/dmac/
prictrl0.rs
