atsam4sp32a_pac/ssc/
rcmr.rs

1#[doc = "Register `RCMR` reader"]
2pub struct R(crate::R<RCMR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<RCMR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<RCMR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<RCMR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `RCMR` writer"]
17pub struct W(crate::W<RCMR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<RCMR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<RCMR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<RCMR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CKS` reader - Receive Clock Selection"]
38pub type CKS_R = crate::FieldReader<u8, CKS_A>;
39#[doc = "Receive Clock Selection\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CKS_A {
43    #[doc = "0: Divided Clock"]
44    MCK = 0,
45    #[doc = "1: TK Clock signal"]
46    TK = 1,
47    #[doc = "2: RK pin"]
48    RK = 2,
49}
50impl From<CKS_A> for u8 {
51    #[inline(always)]
52    fn from(variant: CKS_A) -> Self {
53        variant as _
54    }
55}
56impl CKS_R {
57    #[doc = "Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> Option<CKS_A> {
60        match self.bits {
61            0 => Some(CKS_A::MCK),
62            1 => Some(CKS_A::TK),
63            2 => Some(CKS_A::RK),
64            _ => None,
65        }
66    }
67    #[doc = "Checks if the value of the field is `MCK`"]
68    #[inline(always)]
69    pub fn is_mck(&self) -> bool {
70        *self == CKS_A::MCK
71    }
72    #[doc = "Checks if the value of the field is `TK`"]
73    #[inline(always)]
74    pub fn is_tk(&self) -> bool {
75        *self == CKS_A::TK
76    }
77    #[doc = "Checks if the value of the field is `RK`"]
78    #[inline(always)]
79    pub fn is_rk(&self) -> bool {
80        *self == CKS_A::RK
81    }
82}
83#[doc = "Field `CKS` writer - Receive Clock Selection"]
84pub type CKS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RCMR_SPEC, u8, CKS_A, 2, O>;
85impl<'a, const O: u8> CKS_W<'a, O> {
86    #[doc = "Divided Clock"]
87    #[inline(always)]
88    pub fn mck(self) -> &'a mut W {
89        self.variant(CKS_A::MCK)
90    }
91    #[doc = "TK Clock signal"]
92    #[inline(always)]
93    pub fn tk(self) -> &'a mut W {
94        self.variant(CKS_A::TK)
95    }
96    #[doc = "RK pin"]
97    #[inline(always)]
98    pub fn rk(self) -> &'a mut W {
99        self.variant(CKS_A::RK)
100    }
101}
102#[doc = "Field `CKO` reader - Receive Clock Output Mode Selection"]
103pub type CKO_R = crate::FieldReader<u8, CKO_A>;
104#[doc = "Receive Clock Output Mode Selection\n\nValue on reset: 0"]
105#[derive(Clone, Copy, Debug, PartialEq, Eq)]
106#[repr(u8)]
107pub enum CKO_A {
108    #[doc = "0: None, RK pin is an input"]
109    NONE = 0,
110    #[doc = "1: Continuous Receive Clock, RK pin is an output"]
111    CONTINUOUS = 1,
112    #[doc = "2: Receive Clock only during data transfers, RK pin is an output"]
113    TRANSFER = 2,
114}
115impl From<CKO_A> for u8 {
116    #[inline(always)]
117    fn from(variant: CKO_A) -> Self {
118        variant as _
119    }
120}
121impl CKO_R {
122    #[doc = "Get enumerated values variant"]
123    #[inline(always)]
124    pub fn variant(&self) -> Option<CKO_A> {
125        match self.bits {
126            0 => Some(CKO_A::NONE),
127            1 => Some(CKO_A::CONTINUOUS),
128            2 => Some(CKO_A::TRANSFER),
129            _ => None,
130        }
131    }
132    #[doc = "Checks if the value of the field is `NONE`"]
133    #[inline(always)]
134    pub fn is_none(&self) -> bool {
135        *self == CKO_A::NONE
136    }
137    #[doc = "Checks if the value of the field is `CONTINUOUS`"]
138    #[inline(always)]
139    pub fn is_continuous(&self) -> bool {
140        *self == CKO_A::CONTINUOUS
141    }
142    #[doc = "Checks if the value of the field is `TRANSFER`"]
143    #[inline(always)]
144    pub fn is_transfer(&self) -> bool {
145        *self == CKO_A::TRANSFER
146    }
147}
148#[doc = "Field `CKO` writer - Receive Clock Output Mode Selection"]
149pub type CKO_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RCMR_SPEC, u8, CKO_A, 3, O>;
150impl<'a, const O: u8> CKO_W<'a, O> {
151    #[doc = "None, RK pin is an input"]
152    #[inline(always)]
153    pub fn none(self) -> &'a mut W {
154        self.variant(CKO_A::NONE)
155    }
156    #[doc = "Continuous Receive Clock, RK pin is an output"]
157    #[inline(always)]
158    pub fn continuous(self) -> &'a mut W {
159        self.variant(CKO_A::CONTINUOUS)
160    }
161    #[doc = "Receive Clock only during data transfers, RK pin is an output"]
162    #[inline(always)]
163    pub fn transfer(self) -> &'a mut W {
164        self.variant(CKO_A::TRANSFER)
165    }
166}
167#[doc = "Field `CKI` reader - Receive Clock Inversion"]
168pub type CKI_R = crate::BitReader<bool>;
169#[doc = "Field `CKI` writer - Receive Clock Inversion"]
170pub type CKI_W<'a, const O: u8> = crate::BitWriter<'a, u32, RCMR_SPEC, bool, O>;
171#[doc = "Field `CKG` reader - Receive Clock Gating Selection"]
172pub type CKG_R = crate::FieldReader<u8, CKG_A>;
173#[doc = "Receive Clock Gating Selection\n\nValue on reset: 0"]
174#[derive(Clone, Copy, Debug, PartialEq, Eq)]
175#[repr(u8)]
176pub enum CKG_A {
177    #[doc = "0: None"]
178    CONTINUOUS = 0,
179    #[doc = "1: Receive Clock enabled only if RF Pin is Low"]
180    EN_RF_LOW = 1,
181    #[doc = "2: Receive Clock enabled only if RF Pin is High"]
182    EN_RF_HIGH = 2,
183}
184impl From<CKG_A> for u8 {
185    #[inline(always)]
186    fn from(variant: CKG_A) -> Self {
187        variant as _
188    }
189}
190impl CKG_R {
191    #[doc = "Get enumerated values variant"]
192    #[inline(always)]
193    pub fn variant(&self) -> Option<CKG_A> {
194        match self.bits {
195            0 => Some(CKG_A::CONTINUOUS),
196            1 => Some(CKG_A::EN_RF_LOW),
197            2 => Some(CKG_A::EN_RF_HIGH),
198            _ => None,
199        }
200    }
201    #[doc = "Checks if the value of the field is `CONTINUOUS`"]
202    #[inline(always)]
203    pub fn is_continuous(&self) -> bool {
204        *self == CKG_A::CONTINUOUS
205    }
206    #[doc = "Checks if the value of the field is `EN_RF_LOW`"]
207    #[inline(always)]
208    pub fn is_en_rf_low(&self) -> bool {
209        *self == CKG_A::EN_RF_LOW
210    }
211    #[doc = "Checks if the value of the field is `EN_RF_HIGH`"]
212    #[inline(always)]
213    pub fn is_en_rf_high(&self) -> bool {
214        *self == CKG_A::EN_RF_HIGH
215    }
216}
217#[doc = "Field `CKG` writer - Receive Clock Gating Selection"]
218pub type CKG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RCMR_SPEC, u8, CKG_A, 2, O>;
219impl<'a, const O: u8> CKG_W<'a, O> {
220    #[doc = "None"]
221    #[inline(always)]
222    pub fn continuous(self) -> &'a mut W {
223        self.variant(CKG_A::CONTINUOUS)
224    }
225    #[doc = "Receive Clock enabled only if RF Pin is Low"]
226    #[inline(always)]
227    pub fn en_rf_low(self) -> &'a mut W {
228        self.variant(CKG_A::EN_RF_LOW)
229    }
230    #[doc = "Receive Clock enabled only if RF Pin is High"]
231    #[inline(always)]
232    pub fn en_rf_high(self) -> &'a mut W {
233        self.variant(CKG_A::EN_RF_HIGH)
234    }
235}
236#[doc = "Field `START` reader - Receive Start Selection"]
237pub type START_R = crate::FieldReader<u8, START_A>;
238#[doc = "Receive Start Selection\n\nValue on reset: 0"]
239#[derive(Clone, Copy, Debug, PartialEq, Eq)]
240#[repr(u8)]
241pub enum START_A {
242    #[doc = "0: Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data."]
243    CONTINUOUS = 0,
244    #[doc = "1: Transmit start"]
245    TRANSMIT = 1,
246    #[doc = "2: Detection of a low level on RF signal"]
247    RF_LOW = 2,
248    #[doc = "3: Detection of a high level on RF signal"]
249    RF_HIGH = 3,
250    #[doc = "4: Detection of a falling edge on RF signal"]
251    RF_FALLING = 4,
252    #[doc = "5: Detection of a rising edge on RF signal"]
253    RF_RISING = 5,
254    #[doc = "6: Detection of any level change on RF signal"]
255    RF_LEVEL = 6,
256    #[doc = "7: Detection of any edge on RF signal"]
257    RF_EDGE = 7,
258    #[doc = "8: Compare 0"]
259    CMP_0 = 8,
260}
261impl From<START_A> for u8 {
262    #[inline(always)]
263    fn from(variant: START_A) -> Self {
264        variant as _
265    }
266}
267impl START_R {
268    #[doc = "Get enumerated values variant"]
269    #[inline(always)]
270    pub fn variant(&self) -> Option<START_A> {
271        match self.bits {
272            0 => Some(START_A::CONTINUOUS),
273            1 => Some(START_A::TRANSMIT),
274            2 => Some(START_A::RF_LOW),
275            3 => Some(START_A::RF_HIGH),
276            4 => Some(START_A::RF_FALLING),
277            5 => Some(START_A::RF_RISING),
278            6 => Some(START_A::RF_LEVEL),
279            7 => Some(START_A::RF_EDGE),
280            8 => Some(START_A::CMP_0),
281            _ => None,
282        }
283    }
284    #[doc = "Checks if the value of the field is `CONTINUOUS`"]
285    #[inline(always)]
286    pub fn is_continuous(&self) -> bool {
287        *self == START_A::CONTINUOUS
288    }
289    #[doc = "Checks if the value of the field is `TRANSMIT`"]
290    #[inline(always)]
291    pub fn is_transmit(&self) -> bool {
292        *self == START_A::TRANSMIT
293    }
294    #[doc = "Checks if the value of the field is `RF_LOW`"]
295    #[inline(always)]
296    pub fn is_rf_low(&self) -> bool {
297        *self == START_A::RF_LOW
298    }
299    #[doc = "Checks if the value of the field is `RF_HIGH`"]
300    #[inline(always)]
301    pub fn is_rf_high(&self) -> bool {
302        *self == START_A::RF_HIGH
303    }
304    #[doc = "Checks if the value of the field is `RF_FALLING`"]
305    #[inline(always)]
306    pub fn is_rf_falling(&self) -> bool {
307        *self == START_A::RF_FALLING
308    }
309    #[doc = "Checks if the value of the field is `RF_RISING`"]
310    #[inline(always)]
311    pub fn is_rf_rising(&self) -> bool {
312        *self == START_A::RF_RISING
313    }
314    #[doc = "Checks if the value of the field is `RF_LEVEL`"]
315    #[inline(always)]
316    pub fn is_rf_level(&self) -> bool {
317        *self == START_A::RF_LEVEL
318    }
319    #[doc = "Checks if the value of the field is `RF_EDGE`"]
320    #[inline(always)]
321    pub fn is_rf_edge(&self) -> bool {
322        *self == START_A::RF_EDGE
323    }
324    #[doc = "Checks if the value of the field is `CMP_0`"]
325    #[inline(always)]
326    pub fn is_cmp_0(&self) -> bool {
327        *self == START_A::CMP_0
328    }
329}
330#[doc = "Field `START` writer - Receive Start Selection"]
331pub type START_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RCMR_SPEC, u8, START_A, 4, O>;
332impl<'a, const O: u8> START_W<'a, O> {
333    #[doc = "Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data."]
334    #[inline(always)]
335    pub fn continuous(self) -> &'a mut W {
336        self.variant(START_A::CONTINUOUS)
337    }
338    #[doc = "Transmit start"]
339    #[inline(always)]
340    pub fn transmit(self) -> &'a mut W {
341        self.variant(START_A::TRANSMIT)
342    }
343    #[doc = "Detection of a low level on RF signal"]
344    #[inline(always)]
345    pub fn rf_low(self) -> &'a mut W {
346        self.variant(START_A::RF_LOW)
347    }
348    #[doc = "Detection of a high level on RF signal"]
349    #[inline(always)]
350    pub fn rf_high(self) -> &'a mut W {
351        self.variant(START_A::RF_HIGH)
352    }
353    #[doc = "Detection of a falling edge on RF signal"]
354    #[inline(always)]
355    pub fn rf_falling(self) -> &'a mut W {
356        self.variant(START_A::RF_FALLING)
357    }
358    #[doc = "Detection of a rising edge on RF signal"]
359    #[inline(always)]
360    pub fn rf_rising(self) -> &'a mut W {
361        self.variant(START_A::RF_RISING)
362    }
363    #[doc = "Detection of any level change on RF signal"]
364    #[inline(always)]
365    pub fn rf_level(self) -> &'a mut W {
366        self.variant(START_A::RF_LEVEL)
367    }
368    #[doc = "Detection of any edge on RF signal"]
369    #[inline(always)]
370    pub fn rf_edge(self) -> &'a mut W {
371        self.variant(START_A::RF_EDGE)
372    }
373    #[doc = "Compare 0"]
374    #[inline(always)]
375    pub fn cmp_0(self) -> &'a mut W {
376        self.variant(START_A::CMP_0)
377    }
378}
379#[doc = "Field `STOP` reader - Receive Stop Selection"]
380pub type STOP_R = crate::BitReader<bool>;
381#[doc = "Field `STOP` writer - Receive Stop Selection"]
382pub type STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, RCMR_SPEC, bool, O>;
383#[doc = "Field `STTDLY` reader - Receive Start Delay"]
384pub type STTDLY_R = crate::FieldReader<u8, u8>;
385#[doc = "Field `STTDLY` writer - Receive Start Delay"]
386pub type STTDLY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RCMR_SPEC, u8, u8, 8, O>;
387#[doc = "Field `PERIOD` reader - Receive Period Divider Selection"]
388pub type PERIOD_R = crate::FieldReader<u8, u8>;
389#[doc = "Field `PERIOD` writer - Receive Period Divider Selection"]
390pub type PERIOD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RCMR_SPEC, u8, u8, 8, O>;
391impl R {
392    #[doc = "Bits 0:1 - Receive Clock Selection"]
393    #[inline(always)]
394    pub fn cks(&self) -> CKS_R {
395        CKS_R::new((self.bits & 3) as u8)
396    }
397    #[doc = "Bits 2:4 - Receive Clock Output Mode Selection"]
398    #[inline(always)]
399    pub fn cko(&self) -> CKO_R {
400        CKO_R::new(((self.bits >> 2) & 7) as u8)
401    }
402    #[doc = "Bit 5 - Receive Clock Inversion"]
403    #[inline(always)]
404    pub fn cki(&self) -> CKI_R {
405        CKI_R::new(((self.bits >> 5) & 1) != 0)
406    }
407    #[doc = "Bits 6:7 - Receive Clock Gating Selection"]
408    #[inline(always)]
409    pub fn ckg(&self) -> CKG_R {
410        CKG_R::new(((self.bits >> 6) & 3) as u8)
411    }
412    #[doc = "Bits 8:11 - Receive Start Selection"]
413    #[inline(always)]
414    pub fn start(&self) -> START_R {
415        START_R::new(((self.bits >> 8) & 0x0f) as u8)
416    }
417    #[doc = "Bit 12 - Receive Stop Selection"]
418    #[inline(always)]
419    pub fn stop(&self) -> STOP_R {
420        STOP_R::new(((self.bits >> 12) & 1) != 0)
421    }
422    #[doc = "Bits 16:23 - Receive Start Delay"]
423    #[inline(always)]
424    pub fn sttdly(&self) -> STTDLY_R {
425        STTDLY_R::new(((self.bits >> 16) & 0xff) as u8)
426    }
427    #[doc = "Bits 24:31 - Receive Period Divider Selection"]
428    #[inline(always)]
429    pub fn period(&self) -> PERIOD_R {
430        PERIOD_R::new(((self.bits >> 24) & 0xff) as u8)
431    }
432}
433impl W {
434    #[doc = "Bits 0:1 - Receive Clock Selection"]
435    #[inline(always)]
436    #[must_use]
437    pub fn cks(&mut self) -> CKS_W<0> {
438        CKS_W::new(self)
439    }
440    #[doc = "Bits 2:4 - Receive Clock Output Mode Selection"]
441    #[inline(always)]
442    #[must_use]
443    pub fn cko(&mut self) -> CKO_W<2> {
444        CKO_W::new(self)
445    }
446    #[doc = "Bit 5 - Receive Clock Inversion"]
447    #[inline(always)]
448    #[must_use]
449    pub fn cki(&mut self) -> CKI_W<5> {
450        CKI_W::new(self)
451    }
452    #[doc = "Bits 6:7 - Receive Clock Gating Selection"]
453    #[inline(always)]
454    #[must_use]
455    pub fn ckg(&mut self) -> CKG_W<6> {
456        CKG_W::new(self)
457    }
458    #[doc = "Bits 8:11 - Receive Start Selection"]
459    #[inline(always)]
460    #[must_use]
461    pub fn start(&mut self) -> START_W<8> {
462        START_W::new(self)
463    }
464    #[doc = "Bit 12 - Receive Stop Selection"]
465    #[inline(always)]
466    #[must_use]
467    pub fn stop(&mut self) -> STOP_W<12> {
468        STOP_W::new(self)
469    }
470    #[doc = "Bits 16:23 - Receive Start Delay"]
471    #[inline(always)]
472    #[must_use]
473    pub fn sttdly(&mut self) -> STTDLY_W<16> {
474        STTDLY_W::new(self)
475    }
476    #[doc = "Bits 24:31 - Receive Period Divider Selection"]
477    #[inline(always)]
478    #[must_use]
479    pub fn period(&mut self) -> PERIOD_W<24> {
480        PERIOD_W::new(self)
481    }
482    #[doc = "Writes raw bits to the register."]
483    #[inline(always)]
484    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
485        self.0.bits(bits);
486        self
487    }
488}
489#[doc = "Receive Clock Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcmr](index.html) module"]
490pub struct RCMR_SPEC;
491impl crate::RegisterSpec for RCMR_SPEC {
492    type Ux = u32;
493}
494#[doc = "`read()` method returns [rcmr::R](R) reader structure"]
495impl crate::Readable for RCMR_SPEC {
496    type Reader = R;
497}
498#[doc = "`write(|w| ..)` method takes [rcmr::W](W) writer structure"]
499impl crate::Writable for RCMR_SPEC {
500    type Writer = W;
501    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
502    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
503}
504#[doc = "`reset()` method sets RCMR to value 0"]
505impl crate::Resettable for RCMR_SPEC {
506    const RESET_VALUE: Self::Ux = 0;
507}
atsam4sp32a_pac/ssc/rcmr.rs

atsam4sp32a_pac/ssc/
rcmr.rs
