atsam4sd32c_pac/adc/
idr.rs

1#[doc = "Register `IDR` writer"]
2pub struct W(crate::W<IDR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<IDR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<IDR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<IDR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `EOC0` writer - End of Conversion Interrupt Disable 0"]
23pub type EOC0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
24#[doc = "Field `EOC1` writer - End of Conversion Interrupt Disable 1"]
25pub type EOC1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
26#[doc = "Field `EOC2` writer - End of Conversion Interrupt Disable 2"]
27pub type EOC2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
28#[doc = "Field `EOC3` writer - End of Conversion Interrupt Disable 3"]
29pub type EOC3_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
30#[doc = "Field `EOC4` writer - End of Conversion Interrupt Disable 4"]
31pub type EOC4_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
32#[doc = "Field `EOC5` writer - End of Conversion Interrupt Disable 5"]
33pub type EOC5_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
34#[doc = "Field `EOC6` writer - End of Conversion Interrupt Disable 6"]
35pub type EOC6_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
36#[doc = "Field `EOC7` writer - End of Conversion Interrupt Disable 7"]
37pub type EOC7_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
38#[doc = "Field `EOC8` writer - End of Conversion Interrupt Disable 8"]
39pub type EOC8_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
40#[doc = "Field `EOC9` writer - End of Conversion Interrupt Disable 9"]
41pub type EOC9_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
42#[doc = "Field `EOC10` writer - End of Conversion Interrupt Disable 10"]
43pub type EOC10_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
44#[doc = "Field `EOC11` writer - End of Conversion Interrupt Disable 11"]
45pub type EOC11_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
46#[doc = "Field `EOC12` writer - End of Conversion Interrupt Disable 12"]
47pub type EOC12_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
48#[doc = "Field `EOC13` writer - End of Conversion Interrupt Disable 13"]
49pub type EOC13_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
50#[doc = "Field `EOC14` writer - End of Conversion Interrupt Disable 14"]
51pub type EOC14_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
52#[doc = "Field `EOC15` writer - End of Conversion Interrupt Disable 15"]
53pub type EOC15_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
54#[doc = "Field `EOCAL` writer - End of Calibration Sequence"]
55pub type EOCAL_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
56#[doc = "Field `DRDY` writer - Data Ready Interrupt Disable"]
57pub type DRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
58#[doc = "Field `GOVRE` writer - General Overrun Error Interrupt Disable"]
59pub type GOVRE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
60#[doc = "Field `COMPE` writer - Comparison Event Interrupt Disable"]
61pub type COMPE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
62#[doc = "Field `ENDRX` writer - End of Receive Buffer Interrupt Disable"]
63pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
64#[doc = "Field `RXBUFF` writer - Receive Buffer Full Interrupt Disable"]
65pub type RXBUFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
66impl W {
67    #[doc = "Bit 0 - End of Conversion Interrupt Disable 0"]
68    #[inline(always)]
69    #[must_use]
70    pub fn eoc0(&mut self) -> EOC0_W<0> {
71        EOC0_W::new(self)
72    }
73    #[doc = "Bit 1 - End of Conversion Interrupt Disable 1"]
74    #[inline(always)]
75    #[must_use]
76    pub fn eoc1(&mut self) -> EOC1_W<1> {
77        EOC1_W::new(self)
78    }
79    #[doc = "Bit 2 - End of Conversion Interrupt Disable 2"]
80    #[inline(always)]
81    #[must_use]
82    pub fn eoc2(&mut self) -> EOC2_W<2> {
83        EOC2_W::new(self)
84    }
85    #[doc = "Bit 3 - End of Conversion Interrupt Disable 3"]
86    #[inline(always)]
87    #[must_use]
88    pub fn eoc3(&mut self) -> EOC3_W<3> {
89        EOC3_W::new(self)
90    }
91    #[doc = "Bit 4 - End of Conversion Interrupt Disable 4"]
92    #[inline(always)]
93    #[must_use]
94    pub fn eoc4(&mut self) -> EOC4_W<4> {
95        EOC4_W::new(self)
96    }
97    #[doc = "Bit 5 - End of Conversion Interrupt Disable 5"]
98    #[inline(always)]
99    #[must_use]
100    pub fn eoc5(&mut self) -> EOC5_W<5> {
101        EOC5_W::new(self)
102    }
103    #[doc = "Bit 6 - End of Conversion Interrupt Disable 6"]
104    #[inline(always)]
105    #[must_use]
106    pub fn eoc6(&mut self) -> EOC6_W<6> {
107        EOC6_W::new(self)
108    }
109    #[doc = "Bit 7 - End of Conversion Interrupt Disable 7"]
110    #[inline(always)]
111    #[must_use]
112    pub fn eoc7(&mut self) -> EOC7_W<7> {
113        EOC7_W::new(self)
114    }
115    #[doc = "Bit 8 - End of Conversion Interrupt Disable 8"]
116    #[inline(always)]
117    #[must_use]
118    pub fn eoc8(&mut self) -> EOC8_W<8> {
119        EOC8_W::new(self)
120    }
121    #[doc = "Bit 9 - End of Conversion Interrupt Disable 9"]
122    #[inline(always)]
123    #[must_use]
124    pub fn eoc9(&mut self) -> EOC9_W<9> {
125        EOC9_W::new(self)
126    }
127    #[doc = "Bit 10 - End of Conversion Interrupt Disable 10"]
128    #[inline(always)]
129    #[must_use]
130    pub fn eoc10(&mut self) -> EOC10_W<10> {
131        EOC10_W::new(self)
132    }
133    #[doc = "Bit 11 - End of Conversion Interrupt Disable 11"]
134    #[inline(always)]
135    #[must_use]
136    pub fn eoc11(&mut self) -> EOC11_W<11> {
137        EOC11_W::new(self)
138    }
139    #[doc = "Bit 12 - End of Conversion Interrupt Disable 12"]
140    #[inline(always)]
141    #[must_use]
142    pub fn eoc12(&mut self) -> EOC12_W<12> {
143        EOC12_W::new(self)
144    }
145    #[doc = "Bit 13 - End of Conversion Interrupt Disable 13"]
146    #[inline(always)]
147    #[must_use]
148    pub fn eoc13(&mut self) -> EOC13_W<13> {
149        EOC13_W::new(self)
150    }
151    #[doc = "Bit 14 - End of Conversion Interrupt Disable 14"]
152    #[inline(always)]
153    #[must_use]
154    pub fn eoc14(&mut self) -> EOC14_W<14> {
155        EOC14_W::new(self)
156    }
157    #[doc = "Bit 15 - End of Conversion Interrupt Disable 15"]
158    #[inline(always)]
159    #[must_use]
160    pub fn eoc15(&mut self) -> EOC15_W<15> {
161        EOC15_W::new(self)
162    }
163    #[doc = "Bit 23 - End of Calibration Sequence"]
164    #[inline(always)]
165    #[must_use]
166    pub fn eocal(&mut self) -> EOCAL_W<23> {
167        EOCAL_W::new(self)
168    }
169    #[doc = "Bit 24 - Data Ready Interrupt Disable"]
170    #[inline(always)]
171    #[must_use]
172    pub fn drdy(&mut self) -> DRDY_W<24> {
173        DRDY_W::new(self)
174    }
175    #[doc = "Bit 25 - General Overrun Error Interrupt Disable"]
176    #[inline(always)]
177    #[must_use]
178    pub fn govre(&mut self) -> GOVRE_W<25> {
179        GOVRE_W::new(self)
180    }
181    #[doc = "Bit 26 - Comparison Event Interrupt Disable"]
182    #[inline(always)]
183    #[must_use]
184    pub fn compe(&mut self) -> COMPE_W<26> {
185        COMPE_W::new(self)
186    }
187    #[doc = "Bit 27 - End of Receive Buffer Interrupt Disable"]
188    #[inline(always)]
189    #[must_use]
190    pub fn endrx(&mut self) -> ENDRX_W<27> {
191        ENDRX_W::new(self)
192    }
193    #[doc = "Bit 28 - Receive Buffer Full Interrupt Disable"]
194    #[inline(always)]
195    #[must_use]
196    pub fn rxbuff(&mut self) -> RXBUFF_W<28> {
197        RXBUFF_W::new(self)
198    }
199    #[doc = "Writes raw bits to the register."]
200    #[inline(always)]
201    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
202        self.0.bits(bits);
203        self
204    }
205}
206#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"]
207pub struct IDR_SPEC;
208impl crate::RegisterSpec for IDR_SPEC {
209    type Ux = u32;
210}
211#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"]
212impl crate::Writable for IDR_SPEC {
213    type Writer = W;
214    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
215    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
216}