Struct atsam4sd32b_pac::generic::W [−][src]
Register writer.
Used as an argument to the closures in the write and modify methods of the register.
Implementations
impl<U, REG> W<U, REG>[src]
impl W<u32, Reg<u32, _CR>>[src]
pub fn mcien(&mut self) -> MCIEN_W<'_>[src]
Bit 0 - Multi-Media Interface Enable
pub fn mcidis(&mut self) -> MCIDIS_W<'_>[src]
Bit 1 - Multi-Media Interface Disable
pub fn pwsen(&mut self) -> PWSEN_W<'_>[src]
Bit 2 - Power Save Mode Enable
pub fn pwsdis(&mut self) -> PWSDIS_W<'_>[src]
Bit 3 - Power Save Mode Disable
pub fn swrst(&mut self) -> SWRST_W<'_>[src]
Bit 7 - Software Reset
impl W<u32, Reg<u32, _MR>>[src]
pub fn clkdiv(&mut self) -> CLKDIV_W<'_>[src]
Bits 0:7 - Clock Divider
pub fn pwsdiv(&mut self) -> PWSDIV_W<'_>[src]
Bits 8:10 - Power Saving Divider
pub fn rdproof(&mut self) -> RDPROOF_W<'_>[src]
Bit 11 - Read Proof Enable
pub fn wrproof(&mut self) -> WRPROOF_W<'_>[src]
Bit 12 - Write Proof Enable
pub fn fbyte(&mut self) -> FBYTE_W<'_>[src]
Bit 13 - Force Byte Transfer
pub fn padv(&mut self) -> PADV_W<'_>[src]
Bit 14 - Padding Value
pub fn pdcmode(&mut self) -> PDCMODE_W<'_>[src]
Bit 15 - PDC-oriented Mode
impl W<u32, Reg<u32, _DTOR>>[src]
pub fn dtocyc(&mut self) -> DTOCYC_W<'_>[src]
Bits 0:3 - Data Timeout Cycle Number
pub fn dtomul(&mut self) -> DTOMUL_W<'_>[src]
Bits 4:6 - Data Timeout Multiplier
impl W<u32, Reg<u32, _SDCR>>[src]
pub fn sdcsel(&mut self) -> SDCSEL_W<'_>[src]
Bits 0:1 - SDCard/SDIO Slot
pub fn sdcbus(&mut self) -> SDCBUS_W<'_>[src]
Bits 6:7 - SDCard/SDIO Bus Width
impl W<u32, Reg<u32, _ARGR>>[src]
impl W<u32, Reg<u32, _CMDR>>[src]
pub fn cmdnb(&mut self) -> CMDNB_W<'_>[src]
Bits 0:5 - Command Number
pub fn rsptyp(&mut self) -> RSPTYP_W<'_>[src]
Bits 6:7 - Response Type
pub fn spcmd(&mut self) -> SPCMD_W<'_>[src]
Bits 8:10 - Special Command
pub fn opdcmd(&mut self) -> OPDCMD_W<'_>[src]
Bit 11 - Open Drain Command
pub fn maxlat(&mut self) -> MAXLAT_W<'_>[src]
Bit 12 - Max Latency for Command to Response
pub fn trcmd(&mut self) -> TRCMD_W<'_>[src]
Bits 16:17 - Transfer Command
pub fn trdir(&mut self) -> TRDIR_W<'_>[src]
Bit 18 - Transfer Direction
pub fn trtyp(&mut self) -> TRTYP_W<'_>[src]
Bits 19:21 - Transfer Type
pub fn iospcmd(&mut self) -> IOSPCMD_W<'_>[src]
Bits 24:25 - SDIO Special Command
pub fn atacs(&mut self) -> ATACS_W<'_>[src]
Bit 26 - ATA with Command Completion Signal
pub fn boot_ack(&mut self) -> BOOT_ACK_W<'_>[src]
Bit 27 - Boot Operation Acknowledge
impl W<u32, Reg<u32, _BLKR>>[src]
pub fn bcnt(&mut self) -> BCNT_W<'_>[src]
Bits 0:15 - MMC/SDIO Block Count - SDIO Byte Count
pub fn blklen(&mut self) -> BLKLEN_W<'_>[src]
Bits 16:31 - Data Block Length
impl W<u32, Reg<u32, _CSTOR>>[src]
pub fn cstocyc(&mut self) -> CSTOCYC_W<'_>[src]
Bits 0:3 - Completion Signal Timeout Cycle Number
pub fn cstomul(&mut self) -> CSTOMUL_W<'_>[src]
Bits 4:6 - Completion Signal Timeout Multiplier
impl W<u32, Reg<u32, _TDR>>[src]
impl W<u32, Reg<u32, _IER>>[src]
pub fn cmdrdy(&mut self) -> CMDRDY_W<'_>[src]
Bit 0 - Command Ready Interrupt Enable
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 1 - Receiver Ready Interrupt Enable
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 2 - Transmit Ready Interrupt Enable
pub fn blke(&mut self) -> BLKE_W<'_>[src]
Bit 3 - Data Block Ended Interrupt Enable
pub fn dtip(&mut self) -> DTIP_W<'_>[src]
Bit 4 - Data Transfer in Progress Interrupt Enable
pub fn notbusy(&mut self) -> NOTBUSY_W<'_>[src]
Bit 5 - Data Not Busy Interrupt Enable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 6 - End of Receive Buffer Interrupt Enable
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 7 - End of Transmit Buffer Interrupt Enable
pub fn sdioirqa(&mut self) -> SDIOIRQA_W<'_>[src]
Bit 8 - SDIO Interrupt for Slot A Interrupt Enable
pub fn sdiowait(&mut self) -> SDIOWAIT_W<'_>[src]
Bit 12 - SDIO Read Wait Operation Status Interrupt Enable
pub fn csrcv(&mut self) -> CSRCV_W<'_>[src]
Bit 13 - Completion Signal Received Interrupt Enable
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 14 - Receive Buffer Full Interrupt Enable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 15 - Transmit Buffer Empty Interrupt Enable
pub fn rinde(&mut self) -> RINDE_W<'_>[src]
Bit 16 - Response Index Error Interrupt Enable
pub fn rdire(&mut self) -> RDIRE_W<'_>[src]
Bit 17 - Response Direction Error Interrupt Enable
pub fn rcrce(&mut self) -> RCRCE_W<'_>[src]
Bit 18 - Response CRC Error Interrupt Enable
pub fn rende(&mut self) -> RENDE_W<'_>[src]
Bit 19 - Response End Bit Error Interrupt Enable
pub fn rtoe(&mut self) -> RTOE_W<'_>[src]
Bit 20 - Response Time-out Error Interrupt Enable
pub fn dcrce(&mut self) -> DCRCE_W<'_>[src]
Bit 21 - Data CRC Error Interrupt Enable
pub fn dtoe(&mut self) -> DTOE_W<'_>[src]
Bit 22 - Data Time-out Error Interrupt Enable
pub fn cstoe(&mut self) -> CSTOE_W<'_>[src]
Bit 23 - Completion Signal Timeout Error Interrupt Enable
pub fn fifoempty(&mut self) -> FIFOEMPTY_W<'_>[src]
Bit 26 - FIFO empty Interrupt enable
pub fn xfrdone(&mut self) -> XFRDONE_W<'_>[src]
Bit 27 - Transfer Done Interrupt enable
pub fn ackrcv(&mut self) -> ACKRCV_W<'_>[src]
Bit 28 - Boot Acknowledge Interrupt Enable
pub fn ackrcve(&mut self) -> ACKRCVE_W<'_>[src]
Bit 29 - Boot Acknowledge Error Interrupt Enable
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 30 - Overrun Interrupt Enable
pub fn unre(&mut self) -> UNRE_W<'_>[src]
Bit 31 - Underrun Interrupt Enable
impl W<u32, Reg<u32, _IDR>>[src]
pub fn cmdrdy(&mut self) -> CMDRDY_W<'_>[src]
Bit 0 - Command Ready Interrupt Disable
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 1 - Receiver Ready Interrupt Disable
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 2 - Transmit Ready Interrupt Disable
pub fn blke(&mut self) -> BLKE_W<'_>[src]
Bit 3 - Data Block Ended Interrupt Disable
pub fn dtip(&mut self) -> DTIP_W<'_>[src]
Bit 4 - Data Transfer in Progress Interrupt Disable
pub fn notbusy(&mut self) -> NOTBUSY_W<'_>[src]
Bit 5 - Data Not Busy Interrupt Disable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 6 - End of Receive Buffer Interrupt Disable
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 7 - End of Transmit Buffer Interrupt Disable
pub fn sdioirqa(&mut self) -> SDIOIRQA_W<'_>[src]
Bit 8 - SDIO Interrupt for Slot A Interrupt Disable
pub fn sdiowait(&mut self) -> SDIOWAIT_W<'_>[src]
Bit 12 - SDIO Read Wait Operation Status Interrupt Disable
pub fn csrcv(&mut self) -> CSRCV_W<'_>[src]
Bit 13 - Completion Signal received interrupt Disable
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 14 - Receive Buffer Full Interrupt Disable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 15 - Transmit Buffer Empty Interrupt Disable
pub fn rinde(&mut self) -> RINDE_W<'_>[src]
Bit 16 - Response Index Error Interrupt Disable
pub fn rdire(&mut self) -> RDIRE_W<'_>[src]
Bit 17 - Response Direction Error Interrupt Disable
pub fn rcrce(&mut self) -> RCRCE_W<'_>[src]
Bit 18 - Response CRC Error Interrupt Disable
pub fn rende(&mut self) -> RENDE_W<'_>[src]
Bit 19 - Response End Bit Error Interrupt Disable
pub fn rtoe(&mut self) -> RTOE_W<'_>[src]
Bit 20 - Response Time-out Error Interrupt Disable
pub fn dcrce(&mut self) -> DCRCE_W<'_>[src]
Bit 21 - Data CRC Error Interrupt Disable
pub fn dtoe(&mut self) -> DTOE_W<'_>[src]
Bit 22 - Data Time-out Error Interrupt Disable
pub fn cstoe(&mut self) -> CSTOE_W<'_>[src]
Bit 23 - Completion Signal Time out Error Interrupt Disable
pub fn fifoempty(&mut self) -> FIFOEMPTY_W<'_>[src]
Bit 26 - FIFO empty Interrupt Disable
pub fn xfrdone(&mut self) -> XFRDONE_W<'_>[src]
Bit 27 - Transfer Done Interrupt Disable
pub fn ackrcv(&mut self) -> ACKRCV_W<'_>[src]
Bit 28 - Boot Acknowledge Interrupt Disable
pub fn ackrcve(&mut self) -> ACKRCVE_W<'_>[src]
Bit 29 - Boot Acknowledge Error Interrupt Disable
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 30 - Overrun Interrupt Disable
pub fn unre(&mut self) -> UNRE_W<'_>[src]
Bit 31 - Underrun Interrupt Disable
impl W<u32, Reg<u32, _CFG>>[src]
pub fn fifomode(&mut self) -> FIFOMODE_W<'_>[src]
Bit 0 - HSMCI Internal FIFO control mode
pub fn ferrctrl(&mut self) -> FERRCTRL_W<'_>[src]
Bit 4 - Flow Error flag reset control mode
pub fn hsmode(&mut self) -> HSMODE_W<'_>[src]
Bit 8 - High Speed Mode
pub fn lsync(&mut self) -> LSYNC_W<'_>[src]
Bit 12 - Synchronize on the last block
impl W<u32, Reg<u32, _WPMR>>[src]
pub fn wpen(&mut self) -> WPEN_W<'_>[src]
Bit 0 - Write Protect Enable
pub fn wpkey(&mut self) -> WPKEY_W<'_>[src]
Bits 8:31 - Write Protect Key
impl W<u32, Reg<u32, _RPR>>[src]
impl W<u32, Reg<u32, _RCR>>[src]
impl W<u32, Reg<u32, _TPR>>[src]
impl W<u32, Reg<u32, _TCR>>[src]
impl W<u32, Reg<u32, _RNPR>>[src]
impl W<u32, Reg<u32, _RNCR>>[src]
impl W<u32, Reg<u32, _TNPR>>[src]
impl W<u32, Reg<u32, _TNCR>>[src]
impl W<u32, Reg<u32, _PTCR>>[src]
pub fn rxten(&mut self) -> RXTEN_W<'_>[src]
Bit 0 - Receiver Transfer Enable
pub fn rxtdis(&mut self) -> RXTDIS_W<'_>[src]
Bit 1 - Receiver Transfer Disable
pub fn txten(&mut self) -> TXTEN_W<'_>[src]
Bit 8 - Transmitter Transfer Enable
pub fn txtdis(&mut self) -> TXTDIS_W<'_>[src]
Bit 9 - Transmitter Transfer Disable
impl W<u32, Reg<u32, _CR>>[src]
pub fn rxen(&mut self) -> RXEN_W<'_>[src]
Bit 0 - Receive Enable
pub fn rxdis(&mut self) -> RXDIS_W<'_>[src]
Bit 1 - Receive Disable
pub fn txen(&mut self) -> TXEN_W<'_>[src]
Bit 8 - Transmit Enable
pub fn txdis(&mut self) -> TXDIS_W<'_>[src]
Bit 9 - Transmit Disable
pub fn swrst(&mut self) -> SWRST_W<'_>[src]
Bit 15 - Software Reset
impl W<u32, Reg<u32, _CMR>>[src]
impl W<u32, Reg<u32, _RCMR>>[src]
pub fn cks(&mut self) -> CKS_W<'_>[src]
Bits 0:1 - Receive Clock Selection
pub fn cko(&mut self) -> CKO_W<'_>[src]
Bits 2:4 - Receive Clock Output Mode Selection
pub fn cki(&mut self) -> CKI_W<'_>[src]
Bit 5 - Receive Clock Inversion
pub fn ckg(&mut self) -> CKG_W<'_>[src]
Bits 6:7 - Receive Clock Gating Selection
pub fn start(&mut self) -> START_W<'_>[src]
Bits 8:11 - Receive Start Selection
pub fn stop(&mut self) -> STOP_W<'_>[src]
Bit 12 - Receive Stop Selection
pub fn sttdly(&mut self) -> STTDLY_W<'_>[src]
Bits 16:23 - Receive Start Delay
pub fn period(&mut self) -> PERIOD_W<'_>[src]
Bits 24:31 - Receive Period Divider Selection
impl W<u32, Reg<u32, _RFMR>>[src]
pub fn datlen(&mut self) -> DATLEN_W<'_>[src]
Bits 0:4 - Data Length
pub fn loop_(&mut self) -> LOOP_W<'_>[src]
Bit 5 - Loop Mode
pub fn msbf(&mut self) -> MSBF_W<'_>[src]
Bit 7 - Most Significant Bit First
pub fn datnb(&mut self) -> DATNB_W<'_>[src]
Bits 8:11 - Data Number per Frame
pub fn fslen(&mut self) -> FSLEN_W<'_>[src]
Bits 16:19 - Receive Frame Sync Length
pub fn fsos(&mut self) -> FSOS_W<'_>[src]
Bits 20:22 - Receive Frame Sync Output Selection
pub fn fsedge(&mut self) -> FSEDGE_W<'_>[src]
Bit 24 - Frame Sync Edge Detection
pub fn fslen_ext(&mut self) -> FSLEN_EXT_W<'_>[src]
Bits 28:31 - FSLEN Field Extension
impl W<u32, Reg<u32, _TCMR>>[src]
pub fn cks(&mut self) -> CKS_W<'_>[src]
Bits 0:1 - Transmit Clock Selection
pub fn cko(&mut self) -> CKO_W<'_>[src]
Bits 2:4 - Transmit Clock Output Mode Selection
pub fn cki(&mut self) -> CKI_W<'_>[src]
Bit 5 - Transmit Clock Inversion
pub fn ckg(&mut self) -> CKG_W<'_>[src]
Bits 6:7 - Transmit Clock Gating Selection
pub fn start(&mut self) -> START_W<'_>[src]
Bits 8:11 - Transmit Start Selection
pub fn sttdly(&mut self) -> STTDLY_W<'_>[src]
Bits 16:23 - Transmit Start Delay
pub fn period(&mut self) -> PERIOD_W<'_>[src]
Bits 24:31 - Transmit Period Divider Selection
impl W<u32, Reg<u32, _TFMR>>[src]
pub fn datlen(&mut self) -> DATLEN_W<'_>[src]
Bits 0:4 - Data Length
pub fn datdef(&mut self) -> DATDEF_W<'_>[src]
Bit 5 - Data Default Value
pub fn msbf(&mut self) -> MSBF_W<'_>[src]
Bit 7 - Most Significant Bit First
pub fn datnb(&mut self) -> DATNB_W<'_>[src]
Bits 8:11 - Data Number per frame
pub fn fslen(&mut self) -> FSLEN_W<'_>[src]
Bits 16:19 - Transmit Frame Sync Length
pub fn fsos(&mut self) -> FSOS_W<'_>[src]
Bits 20:22 - Transmit Frame Sync Output Selection
pub fn fsden(&mut self) -> FSDEN_W<'_>[src]
Bit 23 - Frame Sync Data Enable
pub fn fsedge(&mut self) -> FSEDGE_W<'_>[src]
Bit 24 - Frame Sync Edge Detection
pub fn fslen_ext(&mut self) -> FSLEN_EXT_W<'_>[src]
Bits 28:31 - FSLEN Field Extension
impl W<u32, Reg<u32, _THR>>[src]
impl W<u32, Reg<u32, _TSHR>>[src]
impl W<u32, Reg<u32, _RC0R>>[src]
impl W<u32, Reg<u32, _RC1R>>[src]
impl W<u32, Reg<u32, _IER>>[src]
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 0 - Transmit Ready Interrupt Enable
pub fn txempty(&mut self) -> TXEMPTY_W<'_>[src]
Bit 1 - Transmit Empty Interrupt Enable
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 2 - End of Transmission Interrupt Enable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 3
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 4 - Receive Ready Interrupt Enable
pub fn ovrun(&mut self) -> OVRUN_W<'_>[src]
Bit 5 - Receive Overrun Interrupt Enable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 6 - End of Reception Interrupt Enable
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 7
pub fn cp0(&mut self) -> CP0_W<'_>[src]
Bit 8 - Compare 0 Interrupt Enable
pub fn cp1(&mut self) -> CP1_W<'_>[src]
Bit 9 - Compare 1 Interrupt Enable
pub fn txsyn(&mut self) -> TXSYN_W<'_>[src]
Bit 10 - Tx Sync Interrupt Enable
pub fn rxsyn(&mut self) -> RXSYN_W<'_>[src]
Bit 11 - Rx Sync Interrupt Enable
impl W<u32, Reg<u32, _IDR>>[src]
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 0 - Transmit Ready Interrupt Disable
pub fn txempty(&mut self) -> TXEMPTY_W<'_>[src]
Bit 1 - Transmit Empty Interrupt Disable
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 2 - End of Transmission Interrupt Disable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 3
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 4 - Receive Ready Interrupt Disable
pub fn ovrun(&mut self) -> OVRUN_W<'_>[src]
Bit 5 - Receive Overrun Interrupt Disable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 6 - End of Reception Interrupt Disable
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 7
pub fn cp0(&mut self) -> CP0_W<'_>[src]
Bit 8 - Compare 0 Interrupt Disable
pub fn cp1(&mut self) -> CP1_W<'_>[src]
Bit 9 - Compare 1 Interrupt Disable
pub fn txsyn(&mut self) -> TXSYN_W<'_>[src]
Bit 10 - Tx Sync Interrupt Enable
pub fn rxsyn(&mut self) -> RXSYN_W<'_>[src]
Bit 11 - Rx Sync Interrupt Enable
impl W<u32, Reg<u32, _WPMR>>[src]
pub fn wpen(&mut self) -> WPEN_W<'_>[src]
Bit 0 - Write Protect Enable
pub fn wpkey(&mut self) -> WPKEY_W<'_>[src]
Bits 8:31 - Write Protect KEY
impl W<u32, Reg<u32, _RPR>>[src]
impl W<u32, Reg<u32, _RCR>>[src]
impl W<u32, Reg<u32, _TPR>>[src]
impl W<u32, Reg<u32, _TCR>>[src]
impl W<u32, Reg<u32, _RNPR>>[src]
impl W<u32, Reg<u32, _RNCR>>[src]
impl W<u32, Reg<u32, _TNPR>>[src]
impl W<u32, Reg<u32, _TNCR>>[src]
impl W<u32, Reg<u32, _PTCR>>[src]
pub fn rxten(&mut self) -> RXTEN_W<'_>[src]
Bit 0 - Receiver Transfer Enable
pub fn rxtdis(&mut self) -> RXTDIS_W<'_>[src]
Bit 1 - Receiver Transfer Disable
pub fn txten(&mut self) -> TXTEN_W<'_>[src]
Bit 8 - Transmitter Transfer Enable
pub fn txtdis(&mut self) -> TXTDIS_W<'_>[src]
Bit 9 - Transmitter Transfer Disable
impl W<u32, Reg<u32, _CR>>[src]
pub fn spien(&mut self) -> SPIEN_W<'_>[src]
Bit 0 - SPI Enable
pub fn spidis(&mut self) -> SPIDIS_W<'_>[src]
Bit 1 - SPI Disable
pub fn swrst(&mut self) -> SWRST_W<'_>[src]
Bit 7 - SPI Software Reset
pub fn lastxfer(&mut self) -> LASTXFER_W<'_>[src]
Bit 24 - Last Transfer
impl W<u32, Reg<u32, _MR>>[src]
pub fn mstr(&mut self) -> MSTR_W<'_>[src]
Bit 0 - Master/Slave Mode
pub fn ps(&mut self) -> PS_W<'_>[src]
Bit 1 - Peripheral Select
pub fn pcsdec(&mut self) -> PCSDEC_W<'_>[src]
Bit 2 - Chip Select Decode
pub fn modfdis(&mut self) -> MODFDIS_W<'_>[src]
Bit 4 - Mode Fault Detection
pub fn wdrbt(&mut self) -> WDRBT_W<'_>[src]
Bit 5 - Wait Data Read Before Transfer
pub fn llb(&mut self) -> LLB_W<'_>[src]
Bit 7 - Local Loopback Enable
pub fn pcs(&mut self) -> PCS_W<'_>[src]
Bits 16:19 - Peripheral Chip Select
pub fn dlybcs(&mut self) -> DLYBCS_W<'_>[src]
Bits 24:31 - Delay Between Chip Selects
impl W<u32, Reg<u32, _TDR>>[src]
pub fn td(&mut self) -> TD_W<'_>[src]
Bits 0:15 - Transmit Data
pub fn pcs(&mut self) -> PCS_W<'_>[src]
Bits 16:19 - Peripheral Chip Select
pub fn lastxfer(&mut self) -> LASTXFER_W<'_>[src]
Bit 24 - Last Transfer
impl W<u32, Reg<u32, _IER>>[src]
pub fn rdrf(&mut self) -> RDRF_W<'_>[src]
Bit 0 - Receive Data Register Full Interrupt Enable
pub fn tdre(&mut self) -> TDRE_W<'_>[src]
Bit 1 - SPI Transmit Data Register Empty Interrupt Enable
pub fn modf(&mut self) -> MODF_W<'_>[src]
Bit 2 - Mode Fault Error Interrupt Enable
pub fn ovres(&mut self) -> OVRES_W<'_>[src]
Bit 3 - Overrun Error Interrupt Enable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 4 - End of Receive Buffer Interrupt Enable
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 5 - End of Transmit Buffer Interrupt Enable
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 6 - Receive Buffer Full Interrupt Enable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 7 - Transmit Buffer Empty Interrupt Enable
pub fn nssr(&mut self) -> NSSR_W<'_>[src]
Bit 8 - NSS Rising Interrupt Enable
pub fn txempty(&mut self) -> TXEMPTY_W<'_>[src]
Bit 9 - Transmission Registers Empty Enable
pub fn undes(&mut self) -> UNDES_W<'_>[src]
Bit 10 - Underrun Error Interrupt Enable
impl W<u32, Reg<u32, _IDR>>[src]
pub fn rdrf(&mut self) -> RDRF_W<'_>[src]
Bit 0 - Receive Data Register Full Interrupt Disable
pub fn tdre(&mut self) -> TDRE_W<'_>[src]
Bit 1 - SPI Transmit Data Register Empty Interrupt Disable
pub fn modf(&mut self) -> MODF_W<'_>[src]
Bit 2 - Mode Fault Error Interrupt Disable
pub fn ovres(&mut self) -> OVRES_W<'_>[src]
Bit 3 - Overrun Error Interrupt Disable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 4 - End of Receive Buffer Interrupt Disable
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 5 - End of Transmit Buffer Interrupt Disable
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 6 - Receive Buffer Full Interrupt Disable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 7 - Transmit Buffer Empty Interrupt Disable
pub fn nssr(&mut self) -> NSSR_W<'_>[src]
Bit 8 - NSS Rising Interrupt Disable
pub fn txempty(&mut self) -> TXEMPTY_W<'_>[src]
Bit 9 - Transmission Registers Empty Disable
pub fn undes(&mut self) -> UNDES_W<'_>[src]
Bit 10 - Underrun Error Interrupt Disable
impl W<u32, Reg<u32, _CSR>>[src]
pub fn cpol(&mut self) -> CPOL_W<'_>[src]
Bit 0 - Clock Polarity
pub fn ncpha(&mut self) -> NCPHA_W<'_>[src]
Bit 1 - Clock Phase
pub fn csnaat(&mut self) -> CSNAAT_W<'_>[src]
Bit 2 - Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
pub fn csaat(&mut self) -> CSAAT_W<'_>[src]
Bit 3 - Chip Select Active After Transfer
pub fn bits_(&mut self) -> BITS_W<'_>[src]
Bits 4:7 - Bits Per Transfer
pub fn scbr(&mut self) -> SCBR_W<'_>[src]
Bits 8:15 - Serial Clock Baud Rate
pub fn dlybs(&mut self) -> DLYBS_W<'_>[src]
Bits 16:23 - Delay Before SPCK
pub fn dlybct(&mut self) -> DLYBCT_W<'_>[src]
Bits 24:31 - Delay Between Consecutive Transfers
impl W<u32, Reg<u32, _WPMR>>[src]
pub fn wpen(&mut self) -> WPEN_W<'_>[src]
Bit 0 - Write Protection Enable
pub fn wpkey(&mut self) -> WPKEY_W<'_>[src]
Bits 8:31 - Write Protect Key
impl W<u32, Reg<u32, _RPR>>[src]
impl W<u32, Reg<u32, _RCR>>[src]
impl W<u32, Reg<u32, _TPR>>[src]
impl W<u32, Reg<u32, _TCR>>[src]
impl W<u32, Reg<u32, _RNPR>>[src]
impl W<u32, Reg<u32, _RNCR>>[src]
impl W<u32, Reg<u32, _TNPR>>[src]
impl W<u32, Reg<u32, _TNCR>>[src]
impl W<u32, Reg<u32, _PTCR>>[src]
pub fn rxten(&mut self) -> RXTEN_W<'_>[src]
Bit 0 - Receiver Transfer Enable
pub fn rxtdis(&mut self) -> RXTDIS_W<'_>[src]
Bit 1 - Receiver Transfer Disable
pub fn txten(&mut self) -> TXTEN_W<'_>[src]
Bit 8 - Transmitter Transfer Enable
pub fn txtdis(&mut self) -> TXTDIS_W<'_>[src]
Bit 9 - Transmitter Transfer Disable
impl W<u32, Reg<u32, _CCR0>>[src]
pub fn clken(&mut self) -> CLKEN_W<'_>[src]
Bit 0 - Counter Clock Enable Command
pub fn clkdis(&mut self) -> CLKDIS_W<'_>[src]
Bit 1 - Counter Clock Disable Command
pub fn swtrg(&mut self) -> SWTRG_W<'_>[src]
Bit 2 - Software Trigger Command
impl W<u32, Reg<u32, _CMR0>>[src]
pub fn tcclks(&mut self) -> TCCLKS_W<'_>[src]
Bits 0:2 - Clock Selection
pub fn clki(&mut self) -> CLKI_W<'_>[src]
Bit 3 - Clock Invert
pub fn burst(&mut self) -> BURST_W<'_>[src]
Bits 4:5 - Burst Signal Selection
pub fn ldbstop(&mut self) -> LDBSTOP_W<'_>[src]
Bit 6 - Counter Clock Stopped with RB Loading
pub fn ldbdis(&mut self) -> LDBDIS_W<'_>[src]
Bit 7 - Counter Clock Disable with RB Loading
pub fn etrgedg(&mut self) -> ETRGEDG_W<'_>[src]
Bits 8:9 - External Trigger Edge Selection
pub fn abetrg(&mut self) -> ABETRG_W<'_>[src]
Bit 10 - TIOA or TIOB External Trigger Selection
pub fn cpctrg(&mut self) -> CPCTRG_W<'_>[src]
Bit 14 - RC Compare Trigger Enable
pub fn wave(&mut self) -> WAVE_W<'_>[src]
Bit 15 - Waveform Mode
pub fn ldra(&mut self) -> LDRA_W<'_>[src]
Bits 16:17 - RA Loading Edge Selection
pub fn ldrb(&mut self) -> LDRB_W<'_>[src]
Bits 18:19 - RB Loading Edge Selection
impl W<u32, Reg<u32, _CMR0_WAVE_EQ_1>>[src]
pub fn tcclks(&mut self) -> TCCLKS_W<'_>[src]
Bits 0:2 - Clock Selection
pub fn clki(&mut self) -> CLKI_W<'_>[src]
Bit 3 - Clock Invert
pub fn burst(&mut self) -> BURST_W<'_>[src]
Bits 4:5 - Burst Signal Selection
pub fn cpcstop(&mut self) -> CPCSTOP_W<'_>[src]
Bit 6 - Counter Clock Stopped with RC Compare
pub fn cpcdis(&mut self) -> CPCDIS_W<'_>[src]
Bit 7 - Counter Clock Disable with RC Compare
pub fn eevtedg(&mut self) -> EEVTEDG_W<'_>[src]
Bits 8:9 - External Event Edge Selection
pub fn eevt(&mut self) -> EEVT_W<'_>[src]
Bits 10:11 - External Event Selection
pub fn enetrg(&mut self) -> ENETRG_W<'_>[src]
Bit 12 - External Event Trigger Enable
pub fn wavsel(&mut self) -> WAVSEL_W<'_>[src]
Bits 13:14 - Waveform Selection
pub fn wave(&mut self) -> WAVE_W<'_>[src]
Bit 15 - Waveform Mode
pub fn acpa(&mut self) -> ACPA_W<'_>[src]
Bits 16:17 - RA Compare Effect on TIOA
pub fn acpc(&mut self) -> ACPC_W<'_>[src]
Bits 18:19 - RC Compare Effect on TIOA
pub fn aeevt(&mut self) -> AEEVT_W<'_>[src]
Bits 20:21 - External Event Effect on TIOA
pub fn aswtrg(&mut self) -> ASWTRG_W<'_>[src]
Bits 22:23 - Software Trigger Effect on TIOA
pub fn bcpb(&mut self) -> BCPB_W<'_>[src]
Bits 24:25 - RB Compare Effect on TIOB
pub fn bcpc(&mut self) -> BCPC_W<'_>[src]
Bits 26:27 - RC Compare Effect on TIOB
pub fn beevt(&mut self) -> BEEVT_W<'_>[src]
Bits 28:29 - External Event Effect on TIOB
pub fn bswtrg(&mut self) -> BSWTRG_W<'_>[src]
Bits 30:31 - Software Trigger Effect on TIOB
impl W<u32, Reg<u32, _SMMR0>>[src]
pub fn gcen(&mut self) -> GCEN_W<'_>[src]
Bit 0 - Gray Count Enable
pub fn down(&mut self) -> DOWN_W<'_>[src]
Bit 1 - DOWN Count
impl W<u32, Reg<u32, _RA0>>[src]
impl W<u32, Reg<u32, _RB0>>[src]
impl W<u32, Reg<u32, _RC0>>[src]
impl W<u32, Reg<u32, _IER0>>[src]
pub fn covfs(&mut self) -> COVFS_W<'_>[src]
Bit 0 - Counter Overflow
pub fn lovrs(&mut self) -> LOVRS_W<'_>[src]
Bit 1 - Load Overrun
pub fn cpas(&mut self) -> CPAS_W<'_>[src]
Bit 2 - RA Compare
pub fn cpbs(&mut self) -> CPBS_W<'_>[src]
Bit 3 - RB Compare
pub fn cpcs(&mut self) -> CPCS_W<'_>[src]
Bit 4 - RC Compare
pub fn ldras(&mut self) -> LDRAS_W<'_>[src]
Bit 5 - RA Loading
pub fn ldrbs(&mut self) -> LDRBS_W<'_>[src]
Bit 6 - RB Loading
pub fn etrgs(&mut self) -> ETRGS_W<'_>[src]
Bit 7 - External Trigger
impl W<u32, Reg<u32, _IDR0>>[src]
pub fn covfs(&mut self) -> COVFS_W<'_>[src]
Bit 0 - Counter Overflow
pub fn lovrs(&mut self) -> LOVRS_W<'_>[src]
Bit 1 - Load Overrun
pub fn cpas(&mut self) -> CPAS_W<'_>[src]
Bit 2 - RA Compare
pub fn cpbs(&mut self) -> CPBS_W<'_>[src]
Bit 3 - RB Compare
pub fn cpcs(&mut self) -> CPCS_W<'_>[src]
Bit 4 - RC Compare
pub fn ldras(&mut self) -> LDRAS_W<'_>[src]
Bit 5 - RA Loading
pub fn ldrbs(&mut self) -> LDRBS_W<'_>[src]
Bit 6 - RB Loading
pub fn etrgs(&mut self) -> ETRGS_W<'_>[src]
Bit 7 - External Trigger
impl W<u32, Reg<u32, _CCR1>>[src]
pub fn clken(&mut self) -> CLKEN_W<'_>[src]
Bit 0 - Counter Clock Enable Command
pub fn clkdis(&mut self) -> CLKDIS_W<'_>[src]
Bit 1 - Counter Clock Disable Command
pub fn swtrg(&mut self) -> SWTRG_W<'_>[src]
Bit 2 - Software Trigger Command
impl W<u32, Reg<u32, _CMR1>>[src]
pub fn tcclks(&mut self) -> TCCLKS_W<'_>[src]
Bits 0:2 - Clock Selection
pub fn clki(&mut self) -> CLKI_W<'_>[src]
Bit 3 - Clock Invert
pub fn burst(&mut self) -> BURST_W<'_>[src]
Bits 4:5 - Burst Signal Selection
pub fn ldbstop(&mut self) -> LDBSTOP_W<'_>[src]
Bit 6 - Counter Clock Stopped with RB Loading
pub fn ldbdis(&mut self) -> LDBDIS_W<'_>[src]
Bit 7 - Counter Clock Disable with RB Loading
pub fn etrgedg(&mut self) -> ETRGEDG_W<'_>[src]
Bits 8:9 - External Trigger Edge Selection
pub fn abetrg(&mut self) -> ABETRG_W<'_>[src]
Bit 10 - TIOA or TIOB External Trigger Selection
pub fn cpctrg(&mut self) -> CPCTRG_W<'_>[src]
Bit 14 - RC Compare Trigger Enable
pub fn wave(&mut self) -> WAVE_W<'_>[src]
Bit 15 - Waveform Mode
pub fn ldra(&mut self) -> LDRA_W<'_>[src]
Bits 16:17 - RA Loading Edge Selection
pub fn ldrb(&mut self) -> LDRB_W<'_>[src]
Bits 18:19 - RB Loading Edge Selection
impl W<u32, Reg<u32, _CMR1_WAVE_EQ_1>>[src]
pub fn tcclks(&mut self) -> TCCLKS_W<'_>[src]
Bits 0:2 - Clock Selection
pub fn clki(&mut self) -> CLKI_W<'_>[src]
Bit 3 - Clock Invert
pub fn burst(&mut self) -> BURST_W<'_>[src]
Bits 4:5 - Burst Signal Selection
pub fn cpcstop(&mut self) -> CPCSTOP_W<'_>[src]
Bit 6 - Counter Clock Stopped with RC Compare
pub fn cpcdis(&mut self) -> CPCDIS_W<'_>[src]
Bit 7 - Counter Clock Disable with RC Compare
pub fn eevtedg(&mut self) -> EEVTEDG_W<'_>[src]
Bits 8:9 - External Event Edge Selection
pub fn eevt(&mut self) -> EEVT_W<'_>[src]
Bits 10:11 - External Event Selection
pub fn enetrg(&mut self) -> ENETRG_W<'_>[src]
Bit 12 - External Event Trigger Enable
pub fn wavsel(&mut self) -> WAVSEL_W<'_>[src]
Bits 13:14 - Waveform Selection
pub fn wave(&mut self) -> WAVE_W<'_>[src]
Bit 15 - Waveform Mode
pub fn acpa(&mut self) -> ACPA_W<'_>[src]
Bits 16:17 - RA Compare Effect on TIOA
pub fn acpc(&mut self) -> ACPC_W<'_>[src]
Bits 18:19 - RC Compare Effect on TIOA
pub fn aeevt(&mut self) -> AEEVT_W<'_>[src]
Bits 20:21 - External Event Effect on TIOA
pub fn aswtrg(&mut self) -> ASWTRG_W<'_>[src]
Bits 22:23 - Software Trigger Effect on TIOA
pub fn bcpb(&mut self) -> BCPB_W<'_>[src]
Bits 24:25 - RB Compare Effect on TIOB
pub fn bcpc(&mut self) -> BCPC_W<'_>[src]
Bits 26:27 - RC Compare Effect on TIOB
pub fn beevt(&mut self) -> BEEVT_W<'_>[src]
Bits 28:29 - External Event Effect on TIOB
pub fn bswtrg(&mut self) -> BSWTRG_W<'_>[src]
Bits 30:31 - Software Trigger Effect on TIOB
impl W<u32, Reg<u32, _SMMR1>>[src]
pub fn gcen(&mut self) -> GCEN_W<'_>[src]
Bit 0 - Gray Count Enable
pub fn down(&mut self) -> DOWN_W<'_>[src]
Bit 1 - DOWN Count
impl W<u32, Reg<u32, _RA1>>[src]
impl W<u32, Reg<u32, _RB1>>[src]
impl W<u32, Reg<u32, _RC1>>[src]
impl W<u32, Reg<u32, _IER1>>[src]
pub fn covfs(&mut self) -> COVFS_W<'_>[src]
Bit 0 - Counter Overflow
pub fn lovrs(&mut self) -> LOVRS_W<'_>[src]
Bit 1 - Load Overrun
pub fn cpas(&mut self) -> CPAS_W<'_>[src]
Bit 2 - RA Compare
pub fn cpbs(&mut self) -> CPBS_W<'_>[src]
Bit 3 - RB Compare
pub fn cpcs(&mut self) -> CPCS_W<'_>[src]
Bit 4 - RC Compare
pub fn ldras(&mut self) -> LDRAS_W<'_>[src]
Bit 5 - RA Loading
pub fn ldrbs(&mut self) -> LDRBS_W<'_>[src]
Bit 6 - RB Loading
pub fn etrgs(&mut self) -> ETRGS_W<'_>[src]
Bit 7 - External Trigger
impl W<u32, Reg<u32, _IDR1>>[src]
pub fn covfs(&mut self) -> COVFS_W<'_>[src]
Bit 0 - Counter Overflow
pub fn lovrs(&mut self) -> LOVRS_W<'_>[src]
Bit 1 - Load Overrun
pub fn cpas(&mut self) -> CPAS_W<'_>[src]
Bit 2 - RA Compare
pub fn cpbs(&mut self) -> CPBS_W<'_>[src]
Bit 3 - RB Compare
pub fn cpcs(&mut self) -> CPCS_W<'_>[src]
Bit 4 - RC Compare
pub fn ldras(&mut self) -> LDRAS_W<'_>[src]
Bit 5 - RA Loading
pub fn ldrbs(&mut self) -> LDRBS_W<'_>[src]
Bit 6 - RB Loading
pub fn etrgs(&mut self) -> ETRGS_W<'_>[src]
Bit 7 - External Trigger
impl W<u32, Reg<u32, _CCR2>>[src]
pub fn clken(&mut self) -> CLKEN_W<'_>[src]
Bit 0 - Counter Clock Enable Command
pub fn clkdis(&mut self) -> CLKDIS_W<'_>[src]
Bit 1 - Counter Clock Disable Command
pub fn swtrg(&mut self) -> SWTRG_W<'_>[src]
Bit 2 - Software Trigger Command
impl W<u32, Reg<u32, _CMR2>>[src]
pub fn tcclks(&mut self) -> TCCLKS_W<'_>[src]
Bits 0:2 - Clock Selection
pub fn clki(&mut self) -> CLKI_W<'_>[src]
Bit 3 - Clock Invert
pub fn burst(&mut self) -> BURST_W<'_>[src]
Bits 4:5 - Burst Signal Selection
pub fn ldbstop(&mut self) -> LDBSTOP_W<'_>[src]
Bit 6 - Counter Clock Stopped with RB Loading
pub fn ldbdis(&mut self) -> LDBDIS_W<'_>[src]
Bit 7 - Counter Clock Disable with RB Loading
pub fn etrgedg(&mut self) -> ETRGEDG_W<'_>[src]
Bits 8:9 - External Trigger Edge Selection
pub fn abetrg(&mut self) -> ABETRG_W<'_>[src]
Bit 10 - TIOA or TIOB External Trigger Selection
pub fn cpctrg(&mut self) -> CPCTRG_W<'_>[src]
Bit 14 - RC Compare Trigger Enable
pub fn wave(&mut self) -> WAVE_W<'_>[src]
Bit 15 - Waveform Mode
pub fn ldra(&mut self) -> LDRA_W<'_>[src]
Bits 16:17 - RA Loading Edge Selection
pub fn ldrb(&mut self) -> LDRB_W<'_>[src]
Bits 18:19 - RB Loading Edge Selection
impl W<u32, Reg<u32, _CMR2_WAVE_EQ_1>>[src]
pub fn tcclks(&mut self) -> TCCLKS_W<'_>[src]
Bits 0:2 - Clock Selection
pub fn clki(&mut self) -> CLKI_W<'_>[src]
Bit 3 - Clock Invert
pub fn burst(&mut self) -> BURST_W<'_>[src]
Bits 4:5 - Burst Signal Selection
pub fn cpcstop(&mut self) -> CPCSTOP_W<'_>[src]
Bit 6 - Counter Clock Stopped with RC Compare
pub fn cpcdis(&mut self) -> CPCDIS_W<'_>[src]
Bit 7 - Counter Clock Disable with RC Compare
pub fn eevtedg(&mut self) -> EEVTEDG_W<'_>[src]
Bits 8:9 - External Event Edge Selection
pub fn eevt(&mut self) -> EEVT_W<'_>[src]
Bits 10:11 - External Event Selection
pub fn enetrg(&mut self) -> ENETRG_W<'_>[src]
Bit 12 - External Event Trigger Enable
pub fn wavsel(&mut self) -> WAVSEL_W<'_>[src]
Bits 13:14 - Waveform Selection
pub fn wave(&mut self) -> WAVE_W<'_>[src]
Bit 15 - Waveform Mode
pub fn acpa(&mut self) -> ACPA_W<'_>[src]
Bits 16:17 - RA Compare Effect on TIOA
pub fn acpc(&mut self) -> ACPC_W<'_>[src]
Bits 18:19 - RC Compare Effect on TIOA
pub fn aeevt(&mut self) -> AEEVT_W<'_>[src]
Bits 20:21 - External Event Effect on TIOA
pub fn aswtrg(&mut self) -> ASWTRG_W<'_>[src]
Bits 22:23 - Software Trigger Effect on TIOA
pub fn bcpb(&mut self) -> BCPB_W<'_>[src]
Bits 24:25 - RB Compare Effect on TIOB
pub fn bcpc(&mut self) -> BCPC_W<'_>[src]
Bits 26:27 - RC Compare Effect on TIOB
pub fn beevt(&mut self) -> BEEVT_W<'_>[src]
Bits 28:29 - External Event Effect on TIOB
pub fn bswtrg(&mut self) -> BSWTRG_W<'_>[src]
Bits 30:31 - Software Trigger Effect on TIOB
impl W<u32, Reg<u32, _SMMR2>>[src]
pub fn gcen(&mut self) -> GCEN_W<'_>[src]
Bit 0 - Gray Count Enable
pub fn down(&mut self) -> DOWN_W<'_>[src]
Bit 1 - DOWN Count
impl W<u32, Reg<u32, _RA2>>[src]
impl W<u32, Reg<u32, _RB2>>[src]
impl W<u32, Reg<u32, _RC2>>[src]
impl W<u32, Reg<u32, _IER2>>[src]
pub fn covfs(&mut self) -> COVFS_W<'_>[src]
Bit 0 - Counter Overflow
pub fn lovrs(&mut self) -> LOVRS_W<'_>[src]
Bit 1 - Load Overrun
pub fn cpas(&mut self) -> CPAS_W<'_>[src]
Bit 2 - RA Compare
pub fn cpbs(&mut self) -> CPBS_W<'_>[src]
Bit 3 - RB Compare
pub fn cpcs(&mut self) -> CPCS_W<'_>[src]
Bit 4 - RC Compare
pub fn ldras(&mut self) -> LDRAS_W<'_>[src]
Bit 5 - RA Loading
pub fn ldrbs(&mut self) -> LDRBS_W<'_>[src]
Bit 6 - RB Loading
pub fn etrgs(&mut self) -> ETRGS_W<'_>[src]
Bit 7 - External Trigger
impl W<u32, Reg<u32, _IDR2>>[src]
pub fn covfs(&mut self) -> COVFS_W<'_>[src]
Bit 0 - Counter Overflow
pub fn lovrs(&mut self) -> LOVRS_W<'_>[src]
Bit 1 - Load Overrun
pub fn cpas(&mut self) -> CPAS_W<'_>[src]
Bit 2 - RA Compare
pub fn cpbs(&mut self) -> CPBS_W<'_>[src]
Bit 3 - RB Compare
pub fn cpcs(&mut self) -> CPCS_W<'_>[src]
Bit 4 - RC Compare
pub fn ldras(&mut self) -> LDRAS_W<'_>[src]
Bit 5 - RA Loading
pub fn ldrbs(&mut self) -> LDRBS_W<'_>[src]
Bit 6 - RB Loading
pub fn etrgs(&mut self) -> ETRGS_W<'_>[src]
Bit 7 - External Trigger
impl W<u32, Reg<u32, _BCR>>[src]
impl W<u32, Reg<u32, _BMR>>[src]
pub fn tc0xc0s(&mut self) -> TC0XC0S_W<'_>[src]
Bits 0:1 - External Clock Signal 0 Selection
pub fn tc1xc1s(&mut self) -> TC1XC1S_W<'_>[src]
Bits 2:3 - External Clock Signal 1 Selection
pub fn tc2xc2s(&mut self) -> TC2XC2S_W<'_>[src]
Bits 4:5 - External Clock Signal 2 Selection
pub fn qden(&mut self) -> QDEN_W<'_>[src]
Bit 8 - Quadrature Decoder ENabled
pub fn posen(&mut self) -> POSEN_W<'_>[src]
Bit 9 - POSition ENabled
pub fn speeden(&mut self) -> SPEEDEN_W<'_>[src]
Bit 10 - SPEED ENabled
pub fn qdtrans(&mut self) -> QDTRANS_W<'_>[src]
Bit 11 - Quadrature Decoding TRANSparent
pub fn edgpha(&mut self) -> EDGPHA_W<'_>[src]
Bit 12 - EDGe on PHA count mode
pub fn inva(&mut self) -> INVA_W<'_>[src]
Bit 13 - INVerted phA
pub fn invb(&mut self) -> INVB_W<'_>[src]
Bit 14 - INVerted phB
pub fn invidx(&mut self) -> INVIDX_W<'_>[src]
Bit 15 - INVerted InDeX
pub fn swap(&mut self) -> SWAP_W<'_>[src]
Bit 16 - SWAP PHA and PHB
pub fn idxphb(&mut self) -> IDXPHB_W<'_>[src]
Bit 17 - InDeX pin is PHB pin
pub fn filter(&mut self) -> FILTER_W<'_>[src]
Bit 19 - Glitch Filter
pub fn maxfilt(&mut self) -> MAXFILT_W<'_>[src]
Bits 20:25 - MAXimum FILTer
impl W<u32, Reg<u32, _QIER>>[src]
pub fn idx(&mut self) -> IDX_W<'_>[src]
Bit 0 - InDeX
pub fn dirchg(&mut self) -> DIRCHG_W<'_>[src]
Bit 1 - DIRection CHanGe
pub fn qerr(&mut self) -> QERR_W<'_>[src]
Bit 2 - Quadrature ERRor
impl W<u32, Reg<u32, _QIDR>>[src]
pub fn idx(&mut self) -> IDX_W<'_>[src]
Bit 0 - InDeX
pub fn dirchg(&mut self) -> DIRCHG_W<'_>[src]
Bit 1 - DIRection CHanGe
pub fn qerr(&mut self) -> QERR_W<'_>[src]
Bit 2 - Quadrature ERRor
impl W<u32, Reg<u32, _FMR>>[src]
pub fn encf0(&mut self) -> ENCF0_W<'_>[src]
Bit 0 - ENable Compare Fault Channel 0
pub fn encf1(&mut self) -> ENCF1_W<'_>[src]
Bit 1 - ENable Compare Fault Channel 1
impl W<u32, Reg<u32, _WPMR>>[src]
pub fn wpen(&mut self) -> WPEN_W<'_>[src]
Bit 0 - Write Protect Enable
pub fn wpkey(&mut self) -> WPKEY_W<'_>[src]
Bits 8:31 - Write Protect KEY
impl W<u32, Reg<u32, _CR>>[src]
pub fn start(&mut self) -> START_W<'_>[src]
Bit 0 - Send a START Condition
pub fn stop(&mut self) -> STOP_W<'_>[src]
Bit 1 - Send a STOP Condition
pub fn msen(&mut self) -> MSEN_W<'_>[src]
Bit 2 - TWI Master Mode Enabled
pub fn msdis(&mut self) -> MSDIS_W<'_>[src]
Bit 3 - TWI Master Mode Disabled
pub fn sven(&mut self) -> SVEN_W<'_>[src]
Bit 4 - TWI Slave Mode Enabled
pub fn svdis(&mut self) -> SVDIS_W<'_>[src]
Bit 5 - TWI Slave Mode Disabled
pub fn quick(&mut self) -> QUICK_W<'_>[src]
Bit 6 - SMBUS Quick Command
pub fn swrst(&mut self) -> SWRST_W<'_>[src]
Bit 7 - Software Reset
impl W<u32, Reg<u32, _MMR>>[src]
pub fn iadrsz(&mut self) -> IADRSZ_W<'_>[src]
Bits 8:9 - Internal Device Address Size
pub fn mread(&mut self) -> MREAD_W<'_>[src]
Bit 12 - Master Read Direction
pub fn dadr(&mut self) -> DADR_W<'_>[src]
Bits 16:22 - Device Address
impl W<u32, Reg<u32, _SMR>>[src]
impl W<u32, Reg<u32, _IADR>>[src]
impl W<u32, Reg<u32, _CWGR>>[src]
pub fn cldiv(&mut self) -> CLDIV_W<'_>[src]
Bits 0:7 - Clock Low Divider
pub fn chdiv(&mut self) -> CHDIV_W<'_>[src]
Bits 8:15 - Clock High Divider
pub fn ckdiv(&mut self) -> CKDIV_W<'_>[src]
Bits 16:18 - Clock Divider
impl W<u32, Reg<u32, _IER>>[src]
pub fn txcomp(&mut self) -> TXCOMP_W<'_>[src]
Bit 0 - Transmission Completed Interrupt Enable
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 1 - Receive Holding Register Ready Interrupt Enable
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 2 - Transmit Holding Register Ready Interrupt Enable
pub fn svacc(&mut self) -> SVACC_W<'_>[src]
Bit 4 - Slave Access Interrupt Enable
pub fn gacc(&mut self) -> GACC_W<'_>[src]
Bit 5 - General Call Access Interrupt Enable
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 6 - Overrun Error Interrupt Enable
pub fn nack(&mut self) -> NACK_W<'_>[src]
Bit 8 - Not Acknowledge Interrupt Enable
pub fn arblst(&mut self) -> ARBLST_W<'_>[src]
Bit 9 - Arbitration Lost Interrupt Enable
pub fn scl_ws(&mut self) -> SCL_WS_W<'_>[src]
Bit 10 - Clock Wait State Interrupt Enable
pub fn eosacc(&mut self) -> EOSACC_W<'_>[src]
Bit 11 - End Of Slave Access Interrupt Enable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 12 - End of Receive Buffer Interrupt Enable
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 13 - End of Transmit Buffer Interrupt Enable
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 14 - Receive Buffer Full Interrupt Enable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 15 - Transmit Buffer Empty Interrupt Enable
impl W<u32, Reg<u32, _IDR>>[src]
pub fn txcomp(&mut self) -> TXCOMP_W<'_>[src]
Bit 0 - Transmission Completed Interrupt Disable
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 1 - Receive Holding Register Ready Interrupt Disable
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 2 - Transmit Holding Register Ready Interrupt Disable
pub fn svacc(&mut self) -> SVACC_W<'_>[src]
Bit 4 - Slave Access Interrupt Disable
pub fn gacc(&mut self) -> GACC_W<'_>[src]
Bit 5 - General Call Access Interrupt Disable
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 6 - Overrun Error Interrupt Disable
pub fn nack(&mut self) -> NACK_W<'_>[src]
Bit 8 - Not Acknowledge Interrupt Disable
pub fn arblst(&mut self) -> ARBLST_W<'_>[src]
Bit 9 - Arbitration Lost Interrupt Disable
pub fn scl_ws(&mut self) -> SCL_WS_W<'_>[src]
Bit 10 - Clock Wait State Interrupt Disable
pub fn eosacc(&mut self) -> EOSACC_W<'_>[src]
Bit 11 - End Of Slave Access Interrupt Disable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 12 - End of Receive Buffer Interrupt Disable
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 13 - End of Transmit Buffer Interrupt Disable
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 14 - Receive Buffer Full Interrupt Disable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 15 - Transmit Buffer Empty Interrupt Disable
impl W<u32, Reg<u32, _THR>>[src]
impl W<u32, Reg<u32, _RPR>>[src]
impl W<u32, Reg<u32, _RCR>>[src]
impl W<u32, Reg<u32, _TPR>>[src]
impl W<u32, Reg<u32, _TCR>>[src]
impl W<u32, Reg<u32, _RNPR>>[src]
impl W<u32, Reg<u32, _RNCR>>[src]
impl W<u32, Reg<u32, _TNPR>>[src]
impl W<u32, Reg<u32, _TNCR>>[src]
impl W<u32, Reg<u32, _PTCR>>[src]
pub fn rxten(&mut self) -> RXTEN_W<'_>[src]
Bit 0 - Receiver Transfer Enable
pub fn rxtdis(&mut self) -> RXTDIS_W<'_>[src]
Bit 1 - Receiver Transfer Disable
pub fn txten(&mut self) -> TXTEN_W<'_>[src]
Bit 8 - Transmitter Transfer Enable
pub fn txtdis(&mut self) -> TXTDIS_W<'_>[src]
Bit 9 - Transmitter Transfer Disable
impl W<u32, Reg<u32, _CR>>[src]
pub fn start(&mut self) -> START_W<'_>[src]
Bit 0 - Send a START Condition
pub fn stop(&mut self) -> STOP_W<'_>[src]
Bit 1 - Send a STOP Condition
pub fn msen(&mut self) -> MSEN_W<'_>[src]
Bit 2 - TWI Master Mode Enabled
pub fn msdis(&mut self) -> MSDIS_W<'_>[src]
Bit 3 - TWI Master Mode Disabled
pub fn sven(&mut self) -> SVEN_W<'_>[src]
Bit 4 - TWI Slave Mode Enabled
pub fn svdis(&mut self) -> SVDIS_W<'_>[src]
Bit 5 - TWI Slave Mode Disabled
pub fn quick(&mut self) -> QUICK_W<'_>[src]
Bit 6 - SMBUS Quick Command
pub fn swrst(&mut self) -> SWRST_W<'_>[src]
Bit 7 - Software Reset
impl W<u32, Reg<u32, _MMR>>[src]
pub fn iadrsz(&mut self) -> IADRSZ_W<'_>[src]
Bits 8:9 - Internal Device Address Size
pub fn mread(&mut self) -> MREAD_W<'_>[src]
Bit 12 - Master Read Direction
pub fn dadr(&mut self) -> DADR_W<'_>[src]
Bits 16:22 - Device Address
impl W<u32, Reg<u32, _SMR>>[src]
impl W<u32, Reg<u32, _IADR>>[src]
impl W<u32, Reg<u32, _CWGR>>[src]
pub fn cldiv(&mut self) -> CLDIV_W<'_>[src]
Bits 0:7 - Clock Low Divider
pub fn chdiv(&mut self) -> CHDIV_W<'_>[src]
Bits 8:15 - Clock High Divider
pub fn ckdiv(&mut self) -> CKDIV_W<'_>[src]
Bits 16:18 - Clock Divider
impl W<u32, Reg<u32, _IER>>[src]
pub fn txcomp(&mut self) -> TXCOMP_W<'_>[src]
Bit 0 - Transmission Completed Interrupt Enable
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 1 - Receive Holding Register Ready Interrupt Enable
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 2 - Transmit Holding Register Ready Interrupt Enable
pub fn svacc(&mut self) -> SVACC_W<'_>[src]
Bit 4 - Slave Access Interrupt Enable
pub fn gacc(&mut self) -> GACC_W<'_>[src]
Bit 5 - General Call Access Interrupt Enable
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 6 - Overrun Error Interrupt Enable
pub fn nack(&mut self) -> NACK_W<'_>[src]
Bit 8 - Not Acknowledge Interrupt Enable
pub fn arblst(&mut self) -> ARBLST_W<'_>[src]
Bit 9 - Arbitration Lost Interrupt Enable
pub fn scl_ws(&mut self) -> SCL_WS_W<'_>[src]
Bit 10 - Clock Wait State Interrupt Enable
pub fn eosacc(&mut self) -> EOSACC_W<'_>[src]
Bit 11 - End Of Slave Access Interrupt Enable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 12 - End of Receive Buffer Interrupt Enable
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 13 - End of Transmit Buffer Interrupt Enable
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 14 - Receive Buffer Full Interrupt Enable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 15 - Transmit Buffer Empty Interrupt Enable
impl W<u32, Reg<u32, _IDR>>[src]
pub fn txcomp(&mut self) -> TXCOMP_W<'_>[src]
Bit 0 - Transmission Completed Interrupt Disable
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 1 - Receive Holding Register Ready Interrupt Disable
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 2 - Transmit Holding Register Ready Interrupt Disable
pub fn svacc(&mut self) -> SVACC_W<'_>[src]
Bit 4 - Slave Access Interrupt Disable
pub fn gacc(&mut self) -> GACC_W<'_>[src]
Bit 5 - General Call Access Interrupt Disable
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 6 - Overrun Error Interrupt Disable
pub fn nack(&mut self) -> NACK_W<'_>[src]
Bit 8 - Not Acknowledge Interrupt Disable
pub fn arblst(&mut self) -> ARBLST_W<'_>[src]
Bit 9 - Arbitration Lost Interrupt Disable
pub fn scl_ws(&mut self) -> SCL_WS_W<'_>[src]
Bit 10 - Clock Wait State Interrupt Disable
pub fn eosacc(&mut self) -> EOSACC_W<'_>[src]
Bit 11 - End Of Slave Access Interrupt Disable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 12 - End of Receive Buffer Interrupt Disable
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 13 - End of Transmit Buffer Interrupt Disable
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 14 - Receive Buffer Full Interrupt Disable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 15 - Transmit Buffer Empty Interrupt Disable
impl W<u32, Reg<u32, _THR>>[src]
impl W<u32, Reg<u32, _RPR>>[src]
impl W<u32, Reg<u32, _RCR>>[src]
impl W<u32, Reg<u32, _TPR>>[src]
impl W<u32, Reg<u32, _TCR>>[src]
impl W<u32, Reg<u32, _RNPR>>[src]
impl W<u32, Reg<u32, _RNCR>>[src]
impl W<u32, Reg<u32, _TNPR>>[src]
impl W<u32, Reg<u32, _TNCR>>[src]
impl W<u32, Reg<u32, _PTCR>>[src]
pub fn rxten(&mut self) -> RXTEN_W<'_>[src]
Bit 0 - Receiver Transfer Enable
pub fn rxtdis(&mut self) -> RXTDIS_W<'_>[src]
Bit 1 - Receiver Transfer Disable
pub fn txten(&mut self) -> TXTEN_W<'_>[src]
Bit 8 - Transmitter Transfer Enable
pub fn txtdis(&mut self) -> TXTDIS_W<'_>[src]
Bit 9 - Transmitter Transfer Disable
impl W<u32, Reg<u32, _CLK>>[src]
pub fn diva(&mut self) -> DIVA_W<'_>[src]
Bits 0:7 - CLKA, CLKB Divide Factor
pub fn prea(&mut self) -> PREA_W<'_>[src]
Bits 8:11 - CLKA, CLKB Source Clock Selection
pub fn divb(&mut self) -> DIVB_W<'_>[src]
Bits 16:23 - CLKA, CLKB Divide Factor
pub fn preb(&mut self) -> PREB_W<'_>[src]
Bits 24:27 - CLKA, CLKB Source Clock Selection
impl W<u32, Reg<u32, _ENA>>[src]
pub fn chid0(&mut self) -> CHID0_W<'_>[src]
Bit 0 - Channel ID
pub fn chid1(&mut self) -> CHID1_W<'_>[src]
Bit 1 - Channel ID
pub fn chid2(&mut self) -> CHID2_W<'_>[src]
Bit 2 - Channel ID
pub fn chid3(&mut self) -> CHID3_W<'_>[src]
Bit 3 - Channel ID
impl W<u32, Reg<u32, _DIS>>[src]
pub fn chid0(&mut self) -> CHID0_W<'_>[src]
Bit 0 - Channel ID
pub fn chid1(&mut self) -> CHID1_W<'_>[src]
Bit 1 - Channel ID
pub fn chid2(&mut self) -> CHID2_W<'_>[src]
Bit 2 - Channel ID
pub fn chid3(&mut self) -> CHID3_W<'_>[src]
Bit 3 - Channel ID
impl W<u32, Reg<u32, _IER1>>[src]
pub fn chid0(&mut self) -> CHID0_W<'_>[src]
Bit 0 - Counter Event on Channel 0 Interrupt Enable
pub fn chid1(&mut self) -> CHID1_W<'_>[src]
Bit 1 - Counter Event on Channel 1 Interrupt Enable
pub fn chid2(&mut self) -> CHID2_W<'_>[src]
Bit 2 - Counter Event on Channel 2 Interrupt Enable
pub fn chid3(&mut self) -> CHID3_W<'_>[src]
Bit 3 - Counter Event on Channel 3 Interrupt Enable
pub fn fchid0(&mut self) -> FCHID0_W<'_>[src]
Bit 16 - Fault Protection Trigger on Channel 0 Interrupt Enable
pub fn fchid1(&mut self) -> FCHID1_W<'_>[src]
Bit 17 - Fault Protection Trigger on Channel 1 Interrupt Enable
pub fn fchid2(&mut self) -> FCHID2_W<'_>[src]
Bit 18 - Fault Protection Trigger on Channel 2 Interrupt Enable
pub fn fchid3(&mut self) -> FCHID3_W<'_>[src]
Bit 19 - Fault Protection Trigger on Channel 3 Interrupt Enable
impl W<u32, Reg<u32, _IDR1>>[src]
pub fn chid0(&mut self) -> CHID0_W<'_>[src]
Bit 0 - Counter Event on Channel 0 Interrupt Disable
pub fn chid1(&mut self) -> CHID1_W<'_>[src]
Bit 1 - Counter Event on Channel 1 Interrupt Disable
pub fn chid2(&mut self) -> CHID2_W<'_>[src]
Bit 2 - Counter Event on Channel 2 Interrupt Disable
pub fn chid3(&mut self) -> CHID3_W<'_>[src]
Bit 3 - Counter Event on Channel 3 Interrupt Disable
pub fn fchid0(&mut self) -> FCHID0_W<'_>[src]
Bit 16 - Fault Protection Trigger on Channel 0 Interrupt Disable
pub fn fchid1(&mut self) -> FCHID1_W<'_>[src]
Bit 17 - Fault Protection Trigger on Channel 1 Interrupt Disable
pub fn fchid2(&mut self) -> FCHID2_W<'_>[src]
Bit 18 - Fault Protection Trigger on Channel 2 Interrupt Disable
pub fn fchid3(&mut self) -> FCHID3_W<'_>[src]
Bit 19 - Fault Protection Trigger on Channel 3 Interrupt Disable
impl W<u32, Reg<u32, _SCM>>[src]
pub fn sync0(&mut self) -> SYNC0_W<'_>[src]
Bit 0 - Synchronous Channel 0
pub fn sync1(&mut self) -> SYNC1_W<'_>[src]
Bit 1 - Synchronous Channel 1
pub fn sync2(&mut self) -> SYNC2_W<'_>[src]
Bit 2 - Synchronous Channel 2
pub fn sync3(&mut self) -> SYNC3_W<'_>[src]
Bit 3 - Synchronous Channel 3
pub fn updm(&mut self) -> UPDM_W<'_>[src]
Bits 16:17 - Synchronous Channels Update Mode
pub fn ptrm(&mut self) -> PTRM_W<'_>[src]
Bit 20 - PDC Transfer Request Mode
pub fn ptrcs(&mut self) -> PTRCS_W<'_>[src]
Bits 21:23 - PDC Transfer Request Comparison Selection
impl W<u32, Reg<u32, _SCUC>>[src]
pub fn updulock(&mut self) -> UPDULOCK_W<'_>[src]
Bit 0 - Synchronous Channels Update Unlock
impl W<u32, Reg<u32, _SCUP>>[src]
pub fn upr(&mut self) -> UPR_W<'_>[src]
Bits 0:3 - Update Period
pub fn uprcnt(&mut self) -> UPRCNT_W<'_>[src]
Bits 4:7 - Update Period Counter
impl W<u32, Reg<u32, _SCUPUPD>>[src]
impl W<u32, Reg<u32, _IER2>>[src]
pub fn wrdy(&mut self) -> WRDY_W<'_>[src]
Bit 0 - Write Ready for Synchronous Channels Update Interrupt Enable
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 1 - PDC End of TX Buffer Interrupt Enable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 2 - PDC TX Buffer Empty Interrupt Enable
pub fn unre(&mut self) -> UNRE_W<'_>[src]
Bit 3 - Synchronous Channels Update Underrun Error Interrupt Enable
pub fn cmpm0(&mut self) -> CMPM0_W<'_>[src]
Bit 8 - Comparison 0 Match Interrupt Enable
pub fn cmpm1(&mut self) -> CMPM1_W<'_>[src]
Bit 9 - Comparison 1 Match Interrupt Enable
pub fn cmpm2(&mut self) -> CMPM2_W<'_>[src]
Bit 10 - Comparison 2 Match Interrupt Enable
pub fn cmpm3(&mut self) -> CMPM3_W<'_>[src]
Bit 11 - Comparison 3 Match Interrupt Enable
pub fn cmpm4(&mut self) -> CMPM4_W<'_>[src]
Bit 12 - Comparison 4 Match Interrupt Enable
pub fn cmpm5(&mut self) -> CMPM5_W<'_>[src]
Bit 13 - Comparison 5 Match Interrupt Enable
pub fn cmpm6(&mut self) -> CMPM6_W<'_>[src]
Bit 14 - Comparison 6 Match Interrupt Enable
pub fn cmpm7(&mut self) -> CMPM7_W<'_>[src]
Bit 15 - Comparison 7 Match Interrupt Enable
pub fn cmpu0(&mut self) -> CMPU0_W<'_>[src]
Bit 16 - Comparison 0 Update Interrupt Enable
pub fn cmpu1(&mut self) -> CMPU1_W<'_>[src]
Bit 17 - Comparison 1 Update Interrupt Enable
pub fn cmpu2(&mut self) -> CMPU2_W<'_>[src]
Bit 18 - Comparison 2 Update Interrupt Enable
pub fn cmpu3(&mut self) -> CMPU3_W<'_>[src]
Bit 19 - Comparison 3 Update Interrupt Enable
pub fn cmpu4(&mut self) -> CMPU4_W<'_>[src]
Bit 20 - Comparison 4 Update Interrupt Enable
pub fn cmpu5(&mut self) -> CMPU5_W<'_>[src]
Bit 21 - Comparison 5 Update Interrupt Enable
pub fn cmpu6(&mut self) -> CMPU6_W<'_>[src]
Bit 22 - Comparison 6 Update Interrupt Enable
pub fn cmpu7(&mut self) -> CMPU7_W<'_>[src]
Bit 23 - Comparison 7 Update Interrupt Enable
impl W<u32, Reg<u32, _IDR2>>[src]
pub fn wrdy(&mut self) -> WRDY_W<'_>[src]
Bit 0 - Write Ready for Synchronous Channels Update Interrupt Disable
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 1 - PDC End of TX Buffer Interrupt Disable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 2 - PDC TX Buffer Empty Interrupt Disable
pub fn unre(&mut self) -> UNRE_W<'_>[src]
Bit 3 - Synchronous Channels Update Underrun Error Interrupt Disable
pub fn cmpm0(&mut self) -> CMPM0_W<'_>[src]
Bit 8 - Comparison 0 Match Interrupt Disable
pub fn cmpm1(&mut self) -> CMPM1_W<'_>[src]
Bit 9 - Comparison 1 Match Interrupt Disable
pub fn cmpm2(&mut self) -> CMPM2_W<'_>[src]
Bit 10 - Comparison 2 Match Interrupt Disable
pub fn cmpm3(&mut self) -> CMPM3_W<'_>[src]
Bit 11 - Comparison 3 Match Interrupt Disable
pub fn cmpm4(&mut self) -> CMPM4_W<'_>[src]
Bit 12 - Comparison 4 Match Interrupt Disable
pub fn cmpm5(&mut self) -> CMPM5_W<'_>[src]
Bit 13 - Comparison 5 Match Interrupt Disable
pub fn cmpm6(&mut self) -> CMPM6_W<'_>[src]
Bit 14 - Comparison 6 Match Interrupt Disable
pub fn cmpm7(&mut self) -> CMPM7_W<'_>[src]
Bit 15 - Comparison 7 Match Interrupt Disable
pub fn cmpu0(&mut self) -> CMPU0_W<'_>[src]
Bit 16 - Comparison 0 Update Interrupt Disable
pub fn cmpu1(&mut self) -> CMPU1_W<'_>[src]
Bit 17 - Comparison 1 Update Interrupt Disable
pub fn cmpu2(&mut self) -> CMPU2_W<'_>[src]
Bit 18 - Comparison 2 Update Interrupt Disable
pub fn cmpu3(&mut self) -> CMPU3_W<'_>[src]
Bit 19 - Comparison 3 Update Interrupt Disable
pub fn cmpu4(&mut self) -> CMPU4_W<'_>[src]
Bit 20 - Comparison 4 Update Interrupt Disable
pub fn cmpu5(&mut self) -> CMPU5_W<'_>[src]
Bit 21 - Comparison 5 Update Interrupt Disable
pub fn cmpu6(&mut self) -> CMPU6_W<'_>[src]
Bit 22 - Comparison 6 Update Interrupt Disable
pub fn cmpu7(&mut self) -> CMPU7_W<'_>[src]
Bit 23 - Comparison 7 Update Interrupt Disable
impl W<u32, Reg<u32, _OOV>>[src]
pub fn oovh0(&mut self) -> OOVH0_W<'_>[src]
Bit 0 - Output Override Value for PWMH output of the channel 0
pub fn oovh1(&mut self) -> OOVH1_W<'_>[src]
Bit 1 - Output Override Value for PWMH output of the channel 1
pub fn oovh2(&mut self) -> OOVH2_W<'_>[src]
Bit 2 - Output Override Value for PWMH output of the channel 2
pub fn oovh3(&mut self) -> OOVH3_W<'_>[src]
Bit 3 - Output Override Value for PWMH output of the channel 3
pub fn oovl0(&mut self) -> OOVL0_W<'_>[src]
Bit 16 - Output Override Value for PWML output of the channel 0
pub fn oovl1(&mut self) -> OOVL1_W<'_>[src]
Bit 17 - Output Override Value for PWML output of the channel 1
pub fn oovl2(&mut self) -> OOVL2_W<'_>[src]
Bit 18 - Output Override Value for PWML output of the channel 2
pub fn oovl3(&mut self) -> OOVL3_W<'_>[src]
Bit 19 - Output Override Value for PWML output of the channel 3
impl W<u32, Reg<u32, _OS>>[src]
pub fn osh0(&mut self) -> OSH0_W<'_>[src]
Bit 0 - Output Selection for PWMH output of the channel 0
pub fn osh1(&mut self) -> OSH1_W<'_>[src]
Bit 1 - Output Selection for PWMH output of the channel 1
pub fn osh2(&mut self) -> OSH2_W<'_>[src]
Bit 2 - Output Selection for PWMH output of the channel 2
pub fn osh3(&mut self) -> OSH3_W<'_>[src]
Bit 3 - Output Selection for PWMH output of the channel 3
pub fn osl0(&mut self) -> OSL0_W<'_>[src]
Bit 16 - Output Selection for PWML output of the channel 0
pub fn osl1(&mut self) -> OSL1_W<'_>[src]
Bit 17 - Output Selection for PWML output of the channel 1
pub fn osl2(&mut self) -> OSL2_W<'_>[src]
Bit 18 - Output Selection for PWML output of the channel 2
pub fn osl3(&mut self) -> OSL3_W<'_>[src]
Bit 19 - Output Selection for PWML output of the channel 3
impl W<u32, Reg<u32, _OSS>>[src]
pub fn ossh0(&mut self) -> OSSH0_W<'_>[src]
Bit 0 - Output Selection Set for PWMH output of the channel 0
pub fn ossh1(&mut self) -> OSSH1_W<'_>[src]
Bit 1 - Output Selection Set for PWMH output of the channel 1
pub fn ossh2(&mut self) -> OSSH2_W<'_>[src]
Bit 2 - Output Selection Set for PWMH output of the channel 2
pub fn ossh3(&mut self) -> OSSH3_W<'_>[src]
Bit 3 - Output Selection Set for PWMH output of the channel 3
pub fn ossl0(&mut self) -> OSSL0_W<'_>[src]
Bit 16 - Output Selection Set for PWML output of the channel 0
pub fn ossl1(&mut self) -> OSSL1_W<'_>[src]
Bit 17 - Output Selection Set for PWML output of the channel 1
pub fn ossl2(&mut self) -> OSSL2_W<'_>[src]
Bit 18 - Output Selection Set for PWML output of the channel 2
pub fn ossl3(&mut self) -> OSSL3_W<'_>[src]
Bit 19 - Output Selection Set for PWML output of the channel 3
impl W<u32, Reg<u32, _OSC>>[src]
pub fn osch0(&mut self) -> OSCH0_W<'_>[src]
Bit 0 - Output Selection Clear for PWMH output of the channel 0
pub fn osch1(&mut self) -> OSCH1_W<'_>[src]
Bit 1 - Output Selection Clear for PWMH output of the channel 1
pub fn osch2(&mut self) -> OSCH2_W<'_>[src]
Bit 2 - Output Selection Clear for PWMH output of the channel 2
pub fn osch3(&mut self) -> OSCH3_W<'_>[src]
Bit 3 - Output Selection Clear for PWMH output of the channel 3
pub fn oscl0(&mut self) -> OSCL0_W<'_>[src]
Bit 16 - Output Selection Clear for PWML output of the channel 0
pub fn oscl1(&mut self) -> OSCL1_W<'_>[src]
Bit 17 - Output Selection Clear for PWML output of the channel 1
pub fn oscl2(&mut self) -> OSCL2_W<'_>[src]
Bit 18 - Output Selection Clear for PWML output of the channel 2
pub fn oscl3(&mut self) -> OSCL3_W<'_>[src]
Bit 19 - Output Selection Clear for PWML output of the channel 3
impl W<u32, Reg<u32, _OSSUPD>>[src]
pub fn ossuph0(&mut self) -> OSSUPH0_W<'_>[src]
Bit 0 - Output Selection Set for PWMH output of the channel 0
pub fn ossuph1(&mut self) -> OSSUPH1_W<'_>[src]
Bit 1 - Output Selection Set for PWMH output of the channel 1
pub fn ossuph2(&mut self) -> OSSUPH2_W<'_>[src]
Bit 2 - Output Selection Set for PWMH output of the channel 2
pub fn ossuph3(&mut self) -> OSSUPH3_W<'_>[src]
Bit 3 - Output Selection Set for PWMH output of the channel 3
pub fn ossupl0(&mut self) -> OSSUPL0_W<'_>[src]
Bit 16 - Output Selection Set for PWML output of the channel 0
pub fn ossupl1(&mut self) -> OSSUPL1_W<'_>[src]
Bit 17 - Output Selection Set for PWML output of the channel 1
pub fn ossupl2(&mut self) -> OSSUPL2_W<'_>[src]
Bit 18 - Output Selection Set for PWML output of the channel 2
pub fn ossupl3(&mut self) -> OSSUPL3_W<'_>[src]
Bit 19 - Output Selection Set for PWML output of the channel 3
impl W<u32, Reg<u32, _OSCUPD>>[src]
pub fn oscuph0(&mut self) -> OSCUPH0_W<'_>[src]
Bit 0 - Output Selection Clear for PWMH output of the channel 0
pub fn oscuph1(&mut self) -> OSCUPH1_W<'_>[src]
Bit 1 - Output Selection Clear for PWMH output of the channel 1
pub fn oscuph2(&mut self) -> OSCUPH2_W<'_>[src]
Bit 2 - Output Selection Clear for PWMH output of the channel 2
pub fn oscuph3(&mut self) -> OSCUPH3_W<'_>[src]
Bit 3 - Output Selection Clear for PWMH output of the channel 3
pub fn oscupl0(&mut self) -> OSCUPL0_W<'_>[src]
Bit 16 - Output Selection Clear for PWML output of the channel 0
pub fn oscupl1(&mut self) -> OSCUPL1_W<'_>[src]
Bit 17 - Output Selection Clear for PWML output of the channel 1
pub fn oscupl2(&mut self) -> OSCUPL2_W<'_>[src]
Bit 18 - Output Selection Clear for PWML output of the channel 2
pub fn oscupl3(&mut self) -> OSCUPL3_W<'_>[src]
Bit 19 - Output Selection Clear for PWML output of the channel 3
impl W<u32, Reg<u32, _FMR>>[src]
pub fn fpol(&mut self) -> FPOL_W<'_>[src]
Bits 0:7 - Fault Polarity
pub fn fmod(&mut self) -> FMOD_W<'_>[src]
Bits 8:15 - Fault Activation Mode
pub fn ffil(&mut self) -> FFIL_W<'_>[src]
Bits 16:23 - Fault Filtering
impl W<u32, Reg<u32, _FCR>>[src]
impl W<u32, Reg<u32, _FPV>>[src]
pub fn fpvh0(&mut self) -> FPVH0_W<'_>[src]
Bit 0 - Fault Protection Value for PWMH output on channel 0
pub fn fpvh1(&mut self) -> FPVH1_W<'_>[src]
Bit 1 - Fault Protection Value for PWMH output on channel 1
pub fn fpvh2(&mut self) -> FPVH2_W<'_>[src]
Bit 2 - Fault Protection Value for PWMH output on channel 2
pub fn fpvh3(&mut self) -> FPVH3_W<'_>[src]
Bit 3 - Fault Protection Value for PWMH output on channel 3
pub fn fpvl0(&mut self) -> FPVL0_W<'_>[src]
Bit 16 - Fault Protection Value for PWML output on channel 0
pub fn fpvl1(&mut self) -> FPVL1_W<'_>[src]
Bit 17 - Fault Protection Value for PWML output on channel 1
pub fn fpvl2(&mut self) -> FPVL2_W<'_>[src]
Bit 18 - Fault Protection Value for PWML output on channel 2
pub fn fpvl3(&mut self) -> FPVL3_W<'_>[src]
Bit 19 - Fault Protection Value for PWML output on channel 3
impl W<u32, Reg<u32, _FPE>>[src]
pub fn fpe0(&mut self) -> FPE0_W<'_>[src]
Bits 0:7 - Fault Protection Enable for channel 0
pub fn fpe1(&mut self) -> FPE1_W<'_>[src]
Bits 8:15 - Fault Protection Enable for channel 1
pub fn fpe2(&mut self) -> FPE2_W<'_>[src]
Bits 16:23 - Fault Protection Enable for channel 2
pub fn fpe3(&mut self) -> FPE3_W<'_>[src]
Bits 24:31 - Fault Protection Enable for channel 3
impl W<u32, Reg<u32, _ELMR>>[src]
pub fn csel0(&mut self) -> CSEL0_W<'_>[src]
Bit 0 - Comparison 0 Selection
pub fn csel1(&mut self) -> CSEL1_W<'_>[src]
Bit 1 - Comparison 1 Selection
pub fn csel2(&mut self) -> CSEL2_W<'_>[src]
Bit 2 - Comparison 2 Selection
pub fn csel3(&mut self) -> CSEL3_W<'_>[src]
Bit 3 - Comparison 3 Selection
pub fn csel4(&mut self) -> CSEL4_W<'_>[src]
Bit 4 - Comparison 4 Selection
pub fn csel5(&mut self) -> CSEL5_W<'_>[src]
Bit 5 - Comparison 5 Selection
pub fn csel6(&mut self) -> CSEL6_W<'_>[src]
Bit 6 - Comparison 6 Selection
pub fn csel7(&mut self) -> CSEL7_W<'_>[src]
Bit 7 - Comparison 7 Selection
impl W<u32, Reg<u32, _SMMR>>[src]
pub fn gcen0(&mut self) -> GCEN0_W<'_>[src]
Bit 0 - Gray Count ENable
pub fn gcen1(&mut self) -> GCEN1_W<'_>[src]
Bit 1 - Gray Count ENable
pub fn down0(&mut self) -> DOWN0_W<'_>[src]
Bit 16 - DOWN Count
pub fn down1(&mut self) -> DOWN1_W<'_>[src]
Bit 17 - DOWN Count
impl W<u32, Reg<u32, _WPCR>>[src]
pub fn wpcmd(&mut self) -> WPCMD_W<'_>[src]
Bits 0:1 - Write Protect Command
pub fn wprg0(&mut self) -> WPRG0_W<'_>[src]
Bit 2 - Write Protect Register Group 0
pub fn wprg1(&mut self) -> WPRG1_W<'_>[src]
Bit 3 - Write Protect Register Group 1
pub fn wprg2(&mut self) -> WPRG2_W<'_>[src]
Bit 4 - Write Protect Register Group 2
pub fn wprg3(&mut self) -> WPRG3_W<'_>[src]
Bit 5 - Write Protect Register Group 3
pub fn wprg4(&mut self) -> WPRG4_W<'_>[src]
Bit 6 - Write Protect Register Group 4
pub fn wprg5(&mut self) -> WPRG5_W<'_>[src]
Bit 7 - Write Protect Register Group 5
pub fn wpkey(&mut self) -> WPKEY_W<'_>[src]
Bits 8:31 - Write Protect Key
impl W<u32, Reg<u32, _CMPV0>>[src]
pub fn cv(&mut self) -> CV_W<'_>[src]
Bits 0:23 - Comparison x Value
pub fn cvm(&mut self) -> CVM_W<'_>[src]
Bit 24 - Comparison x Value Mode
impl W<u32, Reg<u32, _CMPVUPD0>>[src]
pub fn cvupd(&mut self) -> CVUPD_W<'_>[src]
Bits 0:23 - Comparison x Value Update
pub fn cvmupd(&mut self) -> CVMUPD_W<'_>[src]
Bit 24 - Comparison x Value Mode Update
impl W<u32, Reg<u32, _CMPM0>>[src]
pub fn cen(&mut self) -> CEN_W<'_>[src]
Bit 0 - Comparison x Enable
pub fn ctr(&mut self) -> CTR_W<'_>[src]
Bits 4:7 - Comparison x Trigger
pub fn cpr(&mut self) -> CPR_W<'_>[src]
Bits 8:11 - Comparison x Period
pub fn cprcnt(&mut self) -> CPRCNT_W<'_>[src]
Bits 12:15 - Comparison x Period Counter
pub fn cupr(&mut self) -> CUPR_W<'_>[src]
Bits 16:19 - Comparison x Update Period
pub fn cuprcnt(&mut self) -> CUPRCNT_W<'_>[src]
Bits 20:23 - Comparison x Update Period Counter
impl W<u32, Reg<u32, _CMPMUPD0>>[src]
pub fn cenupd(&mut self) -> CENUPD_W<'_>[src]
Bit 0 - Comparison x Enable Update
pub fn ctrupd(&mut self) -> CTRUPD_W<'_>[src]
Bits 4:7 - Comparison x Trigger Update
pub fn cprupd(&mut self) -> CPRUPD_W<'_>[src]
Bits 8:11 - Comparison x Period Update
pub fn cuprupd(&mut self) -> CUPRUPD_W<'_>[src]
Bits 16:19 - Comparison x Update Period Update
impl W<u32, Reg<u32, _CMPV1>>[src]
pub fn cv(&mut self) -> CV_W<'_>[src]
Bits 0:23 - Comparison x Value
pub fn cvm(&mut self) -> CVM_W<'_>[src]
Bit 24 - Comparison x Value Mode
impl W<u32, Reg<u32, _CMPVUPD1>>[src]
pub fn cvupd(&mut self) -> CVUPD_W<'_>[src]
Bits 0:23 - Comparison x Value Update
pub fn cvmupd(&mut self) -> CVMUPD_W<'_>[src]
Bit 24 - Comparison x Value Mode Update
impl W<u32, Reg<u32, _CMPM1>>[src]
pub fn cen(&mut self) -> CEN_W<'_>[src]
Bit 0 - Comparison x Enable
pub fn ctr(&mut self) -> CTR_W<'_>[src]
Bits 4:7 - Comparison x Trigger
pub fn cpr(&mut self) -> CPR_W<'_>[src]
Bits 8:11 - Comparison x Period
pub fn cprcnt(&mut self) -> CPRCNT_W<'_>[src]
Bits 12:15 - Comparison x Period Counter
pub fn cupr(&mut self) -> CUPR_W<'_>[src]
Bits 16:19 - Comparison x Update Period
pub fn cuprcnt(&mut self) -> CUPRCNT_W<'_>[src]
Bits 20:23 - Comparison x Update Period Counter
impl W<u32, Reg<u32, _CMPMUPD1>>[src]
pub fn cenupd(&mut self) -> CENUPD_W<'_>[src]
Bit 0 - Comparison x Enable Update
pub fn ctrupd(&mut self) -> CTRUPD_W<'_>[src]
Bits 4:7 - Comparison x Trigger Update
pub fn cprupd(&mut self) -> CPRUPD_W<'_>[src]
Bits 8:11 - Comparison x Period Update
pub fn cuprupd(&mut self) -> CUPRUPD_W<'_>[src]
Bits 16:19 - Comparison x Update Period Update
impl W<u32, Reg<u32, _CMPV2>>[src]
pub fn cv(&mut self) -> CV_W<'_>[src]
Bits 0:23 - Comparison x Value
pub fn cvm(&mut self) -> CVM_W<'_>[src]
Bit 24 - Comparison x Value Mode
impl W<u32, Reg<u32, _CMPVUPD2>>[src]
pub fn cvupd(&mut self) -> CVUPD_W<'_>[src]
Bits 0:23 - Comparison x Value Update
pub fn cvmupd(&mut self) -> CVMUPD_W<'_>[src]
Bit 24 - Comparison x Value Mode Update
impl W<u32, Reg<u32, _CMPM2>>[src]
pub fn cen(&mut self) -> CEN_W<'_>[src]
Bit 0 - Comparison x Enable
pub fn ctr(&mut self) -> CTR_W<'_>[src]
Bits 4:7 - Comparison x Trigger
pub fn cpr(&mut self) -> CPR_W<'_>[src]
Bits 8:11 - Comparison x Period
pub fn cprcnt(&mut self) -> CPRCNT_W<'_>[src]
Bits 12:15 - Comparison x Period Counter
pub fn cupr(&mut self) -> CUPR_W<'_>[src]
Bits 16:19 - Comparison x Update Period
pub fn cuprcnt(&mut self) -> CUPRCNT_W<'_>[src]
Bits 20:23 - Comparison x Update Period Counter
impl W<u32, Reg<u32, _CMPMUPD2>>[src]
pub fn cenupd(&mut self) -> CENUPD_W<'_>[src]
Bit 0 - Comparison x Enable Update
pub fn ctrupd(&mut self) -> CTRUPD_W<'_>[src]
Bits 4:7 - Comparison x Trigger Update
pub fn cprupd(&mut self) -> CPRUPD_W<'_>[src]
Bits 8:11 - Comparison x Period Update
pub fn cuprupd(&mut self) -> CUPRUPD_W<'_>[src]
Bits 16:19 - Comparison x Update Period Update
impl W<u32, Reg<u32, _CMPV3>>[src]
pub fn cv(&mut self) -> CV_W<'_>[src]
Bits 0:23 - Comparison x Value
pub fn cvm(&mut self) -> CVM_W<'_>[src]
Bit 24 - Comparison x Value Mode
impl W<u32, Reg<u32, _CMPVUPD3>>[src]
pub fn cvupd(&mut self) -> CVUPD_W<'_>[src]
Bits 0:23 - Comparison x Value Update
pub fn cvmupd(&mut self) -> CVMUPD_W<'_>[src]
Bit 24 - Comparison x Value Mode Update
impl W<u32, Reg<u32, _CMPM3>>[src]
pub fn cen(&mut self) -> CEN_W<'_>[src]
Bit 0 - Comparison x Enable
pub fn ctr(&mut self) -> CTR_W<'_>[src]
Bits 4:7 - Comparison x Trigger
pub fn cpr(&mut self) -> CPR_W<'_>[src]
Bits 8:11 - Comparison x Period
pub fn cprcnt(&mut self) -> CPRCNT_W<'_>[src]
Bits 12:15 - Comparison x Period Counter
pub fn cupr(&mut self) -> CUPR_W<'_>[src]
Bits 16:19 - Comparison x Update Period
pub fn cuprcnt(&mut self) -> CUPRCNT_W<'_>[src]
Bits 20:23 - Comparison x Update Period Counter
impl W<u32, Reg<u32, _CMPMUPD3>>[src]
pub fn cenupd(&mut self) -> CENUPD_W<'_>[src]
Bit 0 - Comparison x Enable Update
pub fn ctrupd(&mut self) -> CTRUPD_W<'_>[src]
Bits 4:7 - Comparison x Trigger Update
pub fn cprupd(&mut self) -> CPRUPD_W<'_>[src]
Bits 8:11 - Comparison x Period Update
pub fn cuprupd(&mut self) -> CUPRUPD_W<'_>[src]
Bits 16:19 - Comparison x Update Period Update
impl W<u32, Reg<u32, _CMPV4>>[src]
pub fn cv(&mut self) -> CV_W<'_>[src]
Bits 0:23 - Comparison x Value
pub fn cvm(&mut self) -> CVM_W<'_>[src]
Bit 24 - Comparison x Value Mode
impl W<u32, Reg<u32, _CMPVUPD4>>[src]
pub fn cvupd(&mut self) -> CVUPD_W<'_>[src]
Bits 0:23 - Comparison x Value Update
pub fn cvmupd(&mut self) -> CVMUPD_W<'_>[src]
Bit 24 - Comparison x Value Mode Update
impl W<u32, Reg<u32, _CMPM4>>[src]
pub fn cen(&mut self) -> CEN_W<'_>[src]
Bit 0 - Comparison x Enable
pub fn ctr(&mut self) -> CTR_W<'_>[src]
Bits 4:7 - Comparison x Trigger
pub fn cpr(&mut self) -> CPR_W<'_>[src]
Bits 8:11 - Comparison x Period
pub fn cprcnt(&mut self) -> CPRCNT_W<'_>[src]
Bits 12:15 - Comparison x Period Counter
pub fn cupr(&mut self) -> CUPR_W<'_>[src]
Bits 16:19 - Comparison x Update Period
pub fn cuprcnt(&mut self) -> CUPRCNT_W<'_>[src]
Bits 20:23 - Comparison x Update Period Counter
impl W<u32, Reg<u32, _CMPMUPD4>>[src]
pub fn cenupd(&mut self) -> CENUPD_W<'_>[src]
Bit 0 - Comparison x Enable Update
pub fn ctrupd(&mut self) -> CTRUPD_W<'_>[src]
Bits 4:7 - Comparison x Trigger Update
pub fn cprupd(&mut self) -> CPRUPD_W<'_>[src]
Bits 8:11 - Comparison x Period Update
pub fn cuprupd(&mut self) -> CUPRUPD_W<'_>[src]
Bits 16:19 - Comparison x Update Period Update
impl W<u32, Reg<u32, _CMPV5>>[src]
pub fn cv(&mut self) -> CV_W<'_>[src]
Bits 0:23 - Comparison x Value
pub fn cvm(&mut self) -> CVM_W<'_>[src]
Bit 24 - Comparison x Value Mode
impl W<u32, Reg<u32, _CMPVUPD5>>[src]
pub fn cvupd(&mut self) -> CVUPD_W<'_>[src]
Bits 0:23 - Comparison x Value Update
pub fn cvmupd(&mut self) -> CVMUPD_W<'_>[src]
Bit 24 - Comparison x Value Mode Update
impl W<u32, Reg<u32, _CMPM5>>[src]
pub fn cen(&mut self) -> CEN_W<'_>[src]
Bit 0 - Comparison x Enable
pub fn ctr(&mut self) -> CTR_W<'_>[src]
Bits 4:7 - Comparison x Trigger
pub fn cpr(&mut self) -> CPR_W<'_>[src]
Bits 8:11 - Comparison x Period
pub fn cprcnt(&mut self) -> CPRCNT_W<'_>[src]
Bits 12:15 - Comparison x Period Counter
pub fn cupr(&mut self) -> CUPR_W<'_>[src]
Bits 16:19 - Comparison x Update Period
pub fn cuprcnt(&mut self) -> CUPRCNT_W<'_>[src]
Bits 20:23 - Comparison x Update Period Counter
impl W<u32, Reg<u32, _CMPMUPD5>>[src]
pub fn cenupd(&mut self) -> CENUPD_W<'_>[src]
Bit 0 - Comparison x Enable Update
pub fn ctrupd(&mut self) -> CTRUPD_W<'_>[src]
Bits 4:7 - Comparison x Trigger Update
pub fn cprupd(&mut self) -> CPRUPD_W<'_>[src]
Bits 8:11 - Comparison x Period Update
pub fn cuprupd(&mut self) -> CUPRUPD_W<'_>[src]
Bits 16:19 - Comparison x Update Period Update
impl W<u32, Reg<u32, _CMPV6>>[src]
pub fn cv(&mut self) -> CV_W<'_>[src]
Bits 0:23 - Comparison x Value
pub fn cvm(&mut self) -> CVM_W<'_>[src]
Bit 24 - Comparison x Value Mode
impl W<u32, Reg<u32, _CMPVUPD6>>[src]
pub fn cvupd(&mut self) -> CVUPD_W<'_>[src]
Bits 0:23 - Comparison x Value Update
pub fn cvmupd(&mut self) -> CVMUPD_W<'_>[src]
Bit 24 - Comparison x Value Mode Update
impl W<u32, Reg<u32, _CMPM6>>[src]
pub fn cen(&mut self) -> CEN_W<'_>[src]
Bit 0 - Comparison x Enable
pub fn ctr(&mut self) -> CTR_W<'_>[src]
Bits 4:7 - Comparison x Trigger
pub fn cpr(&mut self) -> CPR_W<'_>[src]
Bits 8:11 - Comparison x Period
pub fn cprcnt(&mut self) -> CPRCNT_W<'_>[src]
Bits 12:15 - Comparison x Period Counter
pub fn cupr(&mut self) -> CUPR_W<'_>[src]
Bits 16:19 - Comparison x Update Period
pub fn cuprcnt(&mut self) -> CUPRCNT_W<'_>[src]
Bits 20:23 - Comparison x Update Period Counter
impl W<u32, Reg<u32, _CMPMUPD6>>[src]
pub fn cenupd(&mut self) -> CENUPD_W<'_>[src]
Bit 0 - Comparison x Enable Update
pub fn ctrupd(&mut self) -> CTRUPD_W<'_>[src]
Bits 4:7 - Comparison x Trigger Update
pub fn cprupd(&mut self) -> CPRUPD_W<'_>[src]
Bits 8:11 - Comparison x Period Update
pub fn cuprupd(&mut self) -> CUPRUPD_W<'_>[src]
Bits 16:19 - Comparison x Update Period Update
impl W<u32, Reg<u32, _CMPV7>>[src]
pub fn cv(&mut self) -> CV_W<'_>[src]
Bits 0:23 - Comparison x Value
pub fn cvm(&mut self) -> CVM_W<'_>[src]
Bit 24 - Comparison x Value Mode
impl W<u32, Reg<u32, _CMPVUPD7>>[src]
pub fn cvupd(&mut self) -> CVUPD_W<'_>[src]
Bits 0:23 - Comparison x Value Update
pub fn cvmupd(&mut self) -> CVMUPD_W<'_>[src]
Bit 24 - Comparison x Value Mode Update
impl W<u32, Reg<u32, _CMPM7>>[src]
pub fn cen(&mut self) -> CEN_W<'_>[src]
Bit 0 - Comparison x Enable
pub fn ctr(&mut self) -> CTR_W<'_>[src]
Bits 4:7 - Comparison x Trigger
pub fn cpr(&mut self) -> CPR_W<'_>[src]
Bits 8:11 - Comparison x Period
pub fn cprcnt(&mut self) -> CPRCNT_W<'_>[src]
Bits 12:15 - Comparison x Period Counter
pub fn cupr(&mut self) -> CUPR_W<'_>[src]
Bits 16:19 - Comparison x Update Period
pub fn cuprcnt(&mut self) -> CUPRCNT_W<'_>[src]
Bits 20:23 - Comparison x Update Period Counter
impl W<u32, Reg<u32, _CMPMUPD7>>[src]
pub fn cenupd(&mut self) -> CENUPD_W<'_>[src]
Bit 0 - Comparison x Enable Update
pub fn ctrupd(&mut self) -> CTRUPD_W<'_>[src]
Bits 4:7 - Comparison x Trigger Update
pub fn cprupd(&mut self) -> CPRUPD_W<'_>[src]
Bits 8:11 - Comparison x Period Update
pub fn cuprupd(&mut self) -> CUPRUPD_W<'_>[src]
Bits 16:19 - Comparison x Update Period Update
impl W<u32, Reg<u32, _CMR0>>[src]
pub fn cpre(&mut self) -> CPRE_W<'_>[src]
Bits 0:3 - Channel Pre-scaler
pub fn calg(&mut self) -> CALG_W<'_>[src]
Bit 8 - Channel Alignment
pub fn cpol(&mut self) -> CPOL_W<'_>[src]
Bit 9 - Channel Polarity
pub fn ces(&mut self) -> CES_W<'_>[src]
Bit 10 - Counter Event Selection
pub fn dte(&mut self) -> DTE_W<'_>[src]
Bit 16 - Dead-Time Generator Enable
pub fn dthi(&mut self) -> DTHI_W<'_>[src]
Bit 17 - Dead-Time PWMHx Output Inverted
pub fn dtli(&mut self) -> DTLI_W<'_>[src]
Bit 18 - Dead-Time PWMLx Output Inverted
impl W<u32, Reg<u32, _CDTY0>>[src]
impl W<u32, Reg<u32, _CDTYUPD0>>[src]
impl W<u32, Reg<u32, _CPRD0>>[src]
impl W<u32, Reg<u32, _CPRDUPD0>>[src]
impl W<u32, Reg<u32, _DT0>>[src]
pub fn dth(&mut self) -> DTH_W<'_>[src]
Bits 0:15 - Dead-Time Value for PWMHx Output
pub fn dtl(&mut self) -> DTL_W<'_>[src]
Bits 16:31 - Dead-Time Value for PWMLx Output
impl W<u32, Reg<u32, _DTUPD0>>[src]
pub fn dthupd(&mut self) -> DTHUPD_W<'_>[src]
Bits 0:15 - Dead-Time Value Update for PWMHx Output
pub fn dtlupd(&mut self) -> DTLUPD_W<'_>[src]
Bits 16:31 - Dead-Time Value Update for PWMLx Output
impl W<u32, Reg<u32, _CMR1>>[src]
pub fn cpre(&mut self) -> CPRE_W<'_>[src]
Bits 0:3 - Channel Pre-scaler
pub fn calg(&mut self) -> CALG_W<'_>[src]
Bit 8 - Channel Alignment
pub fn cpol(&mut self) -> CPOL_W<'_>[src]
Bit 9 - Channel Polarity
pub fn ces(&mut self) -> CES_W<'_>[src]
Bit 10 - Counter Event Selection
pub fn dte(&mut self) -> DTE_W<'_>[src]
Bit 16 - Dead-Time Generator Enable
pub fn dthi(&mut self) -> DTHI_W<'_>[src]
Bit 17 - Dead-Time PWMHx Output Inverted
pub fn dtli(&mut self) -> DTLI_W<'_>[src]
Bit 18 - Dead-Time PWMLx Output Inverted
impl W<u32, Reg<u32, _CDTY1>>[src]
impl W<u32, Reg<u32, _CDTYUPD1>>[src]
impl W<u32, Reg<u32, _CPRD1>>[src]
impl W<u32, Reg<u32, _CPRDUPD1>>[src]
impl W<u32, Reg<u32, _DT1>>[src]
pub fn dth(&mut self) -> DTH_W<'_>[src]
Bits 0:15 - Dead-Time Value for PWMHx Output
pub fn dtl(&mut self) -> DTL_W<'_>[src]
Bits 16:31 - Dead-Time Value for PWMLx Output
impl W<u32, Reg<u32, _DTUPD1>>[src]
pub fn dthupd(&mut self) -> DTHUPD_W<'_>[src]
Bits 0:15 - Dead-Time Value Update for PWMHx Output
pub fn dtlupd(&mut self) -> DTLUPD_W<'_>[src]
Bits 16:31 - Dead-Time Value Update for PWMLx Output
impl W<u32, Reg<u32, _CMR2>>[src]
pub fn cpre(&mut self) -> CPRE_W<'_>[src]
Bits 0:3 - Channel Pre-scaler
pub fn calg(&mut self) -> CALG_W<'_>[src]
Bit 8 - Channel Alignment
pub fn cpol(&mut self) -> CPOL_W<'_>[src]
Bit 9 - Channel Polarity
pub fn ces(&mut self) -> CES_W<'_>[src]
Bit 10 - Counter Event Selection
pub fn dte(&mut self) -> DTE_W<'_>[src]
Bit 16 - Dead-Time Generator Enable
pub fn dthi(&mut self) -> DTHI_W<'_>[src]
Bit 17 - Dead-Time PWMHx Output Inverted
pub fn dtli(&mut self) -> DTLI_W<'_>[src]
Bit 18 - Dead-Time PWMLx Output Inverted
impl W<u32, Reg<u32, _CDTY2>>[src]
impl W<u32, Reg<u32, _CDTYUPD2>>[src]
impl W<u32, Reg<u32, _CPRD2>>[src]
impl W<u32, Reg<u32, _CPRDUPD2>>[src]
impl W<u32, Reg<u32, _DT2>>[src]
pub fn dth(&mut self) -> DTH_W<'_>[src]
Bits 0:15 - Dead-Time Value for PWMHx Output
pub fn dtl(&mut self) -> DTL_W<'_>[src]
Bits 16:31 - Dead-Time Value for PWMLx Output
impl W<u32, Reg<u32, _DTUPD2>>[src]
pub fn dthupd(&mut self) -> DTHUPD_W<'_>[src]
Bits 0:15 - Dead-Time Value Update for PWMHx Output
pub fn dtlupd(&mut self) -> DTLUPD_W<'_>[src]
Bits 16:31 - Dead-Time Value Update for PWMLx Output
impl W<u32, Reg<u32, _CMR3>>[src]
pub fn cpre(&mut self) -> CPRE_W<'_>[src]
Bits 0:3 - Channel Pre-scaler
pub fn calg(&mut self) -> CALG_W<'_>[src]
Bit 8 - Channel Alignment
pub fn cpol(&mut self) -> CPOL_W<'_>[src]
Bit 9 - Channel Polarity
pub fn ces(&mut self) -> CES_W<'_>[src]
Bit 10 - Counter Event Selection
pub fn dte(&mut self) -> DTE_W<'_>[src]
Bit 16 - Dead-Time Generator Enable
pub fn dthi(&mut self) -> DTHI_W<'_>[src]
Bit 17 - Dead-Time PWMHx Output Inverted
pub fn dtli(&mut self) -> DTLI_W<'_>[src]
Bit 18 - Dead-Time PWMLx Output Inverted
impl W<u32, Reg<u32, _CDTY3>>[src]
impl W<u32, Reg<u32, _CDTYUPD3>>[src]
impl W<u32, Reg<u32, _CPRD3>>[src]
impl W<u32, Reg<u32, _CPRDUPD3>>[src]
impl W<u32, Reg<u32, _DT3>>[src]
pub fn dth(&mut self) -> DTH_W<'_>[src]
Bits 0:15 - Dead-Time Value for PWMHx Output
pub fn dtl(&mut self) -> DTL_W<'_>[src]
Bits 16:31 - Dead-Time Value for PWMLx Output
impl W<u32, Reg<u32, _DTUPD3>>[src]
pub fn dthupd(&mut self) -> DTHUPD_W<'_>[src]
Bits 0:15 - Dead-Time Value Update for PWMHx Output
pub fn dtlupd(&mut self) -> DTLUPD_W<'_>[src]
Bits 16:31 - Dead-Time Value Update for PWMLx Output
impl W<u32, Reg<u32, _TPR>>[src]
impl W<u32, Reg<u32, _TCR>>[src]
impl W<u32, Reg<u32, _TNPR>>[src]
impl W<u32, Reg<u32, _TNCR>>[src]
impl W<u32, Reg<u32, _PTCR>>[src]
pub fn rxten(&mut self) -> RXTEN_W<'_>[src]
Bit 0 - Receiver Transfer Enable
pub fn rxtdis(&mut self) -> RXTDIS_W<'_>[src]
Bit 1 - Receiver Transfer Disable
pub fn txten(&mut self) -> TXTEN_W<'_>[src]
Bit 8 - Transmitter Transfer Enable
pub fn txtdis(&mut self) -> TXTDIS_W<'_>[src]
Bit 9 - Transmitter Transfer Disable
impl W<u32, Reg<u32, _CR>>[src]
pub fn rstrx(&mut self) -> RSTRX_W<'_>[src]
Bit 2 - Reset Receiver
pub fn rsttx(&mut self) -> RSTTX_W<'_>[src]
Bit 3 - Reset Transmitter
pub fn rxen(&mut self) -> RXEN_W<'_>[src]
Bit 4 - Receiver Enable
pub fn rxdis(&mut self) -> RXDIS_W<'_>[src]
Bit 5 - Receiver Disable
pub fn txen(&mut self) -> TXEN_W<'_>[src]
Bit 6 - Transmitter Enable
pub fn txdis(&mut self) -> TXDIS_W<'_>[src]
Bit 7 - Transmitter Disable
pub fn rststa(&mut self) -> RSTSTA_W<'_>[src]
Bit 8 - Reset Status Bits
pub fn sttbrk(&mut self) -> STTBRK_W<'_>[src]
Bit 9 - Start Break
pub fn stpbrk(&mut self) -> STPBRK_W<'_>[src]
Bit 10 - Stop Break
pub fn sttto(&mut self) -> STTTO_W<'_>[src]
Bit 11 - Start Time-out
pub fn senda(&mut self) -> SENDA_W<'_>[src]
Bit 12 - Send Address
pub fn rstit(&mut self) -> RSTIT_W<'_>[src]
Bit 13 - Reset Iterations
pub fn rstnack(&mut self) -> RSTNACK_W<'_>[src]
Bit 14 - Reset Non Acknowledge
pub fn retto(&mut self) -> RETTO_W<'_>[src]
Bit 15 - Rearm Time-out
pub fn dtren(&mut self) -> DTREN_W<'_>[src]
Bit 16 - Data Terminal Ready Enable
pub fn dtrdis(&mut self) -> DTRDIS_W<'_>[src]
Bit 17 - Data Terminal Ready Disable
pub fn rtsen(&mut self) -> RTSEN_W<'_>[src]
Bit 18 - Request to Send Enable
pub fn rtsdis(&mut self) -> RTSDIS_W<'_>[src]
Bit 19 - Request to Send Disable
impl W<u32, Reg<u32, _CR_SPI_MODE>>[src]
pub fn rstrx(&mut self) -> RSTRX_W<'_>[src]
Bit 2 - Reset Receiver
pub fn rsttx(&mut self) -> RSTTX_W<'_>[src]
Bit 3 - Reset Transmitter
pub fn rxen(&mut self) -> RXEN_W<'_>[src]
Bit 4 - Receiver Enable
pub fn rxdis(&mut self) -> RXDIS_W<'_>[src]
Bit 5 - Receiver Disable
pub fn txen(&mut self) -> TXEN_W<'_>[src]
Bit 6 - Transmitter Enable
pub fn txdis(&mut self) -> TXDIS_W<'_>[src]
Bit 7 - Transmitter Disable
pub fn rststa(&mut self) -> RSTSTA_W<'_>[src]
Bit 8 - Reset Status Bits
pub fn fcs(&mut self) -> FCS_W<'_>[src]
Bit 18 - Force SPI Chip Select
pub fn rcs(&mut self) -> RCS_W<'_>[src]
Bit 19 - Release SPI Chip Select
impl W<u32, Reg<u32, _MR>>[src]
pub fn usart_mode(&mut self) -> USART_MODE_W<'_>[src]
Bits 0:3 - USART Mode of Operation
pub fn usclks(&mut self) -> USCLKS_W<'_>[src]
Bits 4:5 - Clock Selection
pub fn chrl(&mut self) -> CHRL_W<'_>[src]
Bits 6:7 - Character Length
pub fn sync(&mut self) -> SYNC_W<'_>[src]
Bit 8 - Synchronous Mode Select
pub fn par(&mut self) -> PAR_W<'_>[src]
Bits 9:11 - Parity Type
pub fn nbstop(&mut self) -> NBSTOP_W<'_>[src]
Bits 12:13 - Number of Stop Bits
pub fn chmode(&mut self) -> CHMODE_W<'_>[src]
Bits 14:15 - Channel Mode
pub fn msbf(&mut self) -> MSBF_W<'_>[src]
Bit 16 - Bit Order
pub fn mode9(&mut self) -> MODE9_W<'_>[src]
Bit 17 - 9-bit Character Length
pub fn clko(&mut self) -> CLKO_W<'_>[src]
Bit 18 - Clock Output Select
pub fn over(&mut self) -> OVER_W<'_>[src]
Bit 19 - Oversampling Mode
pub fn inack(&mut self) -> INACK_W<'_>[src]
Bit 20 - Inhibit Non Acknowledge
pub fn dsnack(&mut self) -> DSNACK_W<'_>[src]
Bit 21 - Disable Successive NACK
pub fn var_sync(&mut self) -> VAR_SYNC_W<'_>[src]
Bit 22 - Variable Synchronization of Command/Data Sync Start Frame Delimiter
pub fn invdata(&mut self) -> INVDATA_W<'_>[src]
Bit 23 - Inverted Data
pub fn max_iteration(&mut self) -> MAX_ITERATION_W<'_>[src]
Bits 24:26 - Maximum Number of Automatic Iteration
pub fn filter(&mut self) -> FILTER_W<'_>[src]
Bit 28 - Infrared Receive Line Filter
pub fn man(&mut self) -> MAN_W<'_>[src]
Bit 29 - Manchester Encoder/Decoder Enable
pub fn modsync(&mut self) -> MODSYNC_W<'_>[src]
Bit 30 - Manchester Synchronization Mode
pub fn onebit(&mut self) -> ONEBIT_W<'_>[src]
Bit 31 - Start Frame Delimiter Selector
impl W<u32, Reg<u32, _MR_SPI_MODE>>[src]
pub fn usart_mode(&mut self) -> USART_MODE_W<'_>[src]
Bits 0:3 - USART Mode of Operation
pub fn usclks(&mut self) -> USCLKS_W<'_>[src]
Bits 4:5 - Clock Selection
pub fn chrl(&mut self) -> CHRL_W<'_>[src]
Bits 6:7 - Character Length
pub fn cpha(&mut self) -> CPHA_W<'_>[src]
Bit 8 - SPI Clock Phase
pub fn cpol(&mut self) -> CPOL_W<'_>[src]
Bit 16 - SPI Clock Polarity
pub fn wrdbt(&mut self) -> WRDBT_W<'_>[src]
Bit 20 - Wait Read Data Before Transfer
impl W<u32, Reg<u32, _IER>>[src]
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 0 - RXRDY Interrupt Enable
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 1 - TXRDY Interrupt Enable
pub fn rxbrk(&mut self) -> RXBRK_W<'_>[src]
Bit 2 - Receiver Break Interrupt Enable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 3 - End of Receive Transfer Interrupt Enable (available in all USART modes of operation)
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 4 - End of Transmit Interrupt Enable (available in all USART modes of operation)
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 5 - Overrun Error Interrupt Enable
pub fn frame(&mut self) -> FRAME_W<'_>[src]
Bit 6 - Framing Error Interrupt Enable
pub fn pare(&mut self) -> PARE_W<'_>[src]
Bit 7 - Parity Error Interrupt Enable
pub fn timeout(&mut self) -> TIMEOUT_W<'_>[src]
Bit 8 - Time-out Interrupt Enable
pub fn txempty(&mut self) -> TXEMPTY_W<'_>[src]
Bit 9 - TXEMPTY Interrupt Enable
pub fn iter(&mut self) -> ITER_W<'_>[src]
Bit 10 - Max number of Repetitions Reached Interrupt Enable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 11 - Buffer Empty Interrupt Enable (available in all USART modes of operation)
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 12 - Buffer Full Interrupt Enable (available in all USART modes of operation)
pub fn nack(&mut self) -> NACK_W<'_>[src]
Bit 13 - Non AcknowledgeInterrupt Enable
pub fn riic(&mut self) -> RIIC_W<'_>[src]
Bit 16 - Ring Indicator Input Change Enable
pub fn dsric(&mut self) -> DSRIC_W<'_>[src]
Bit 17 - Data Set Ready Input Change Enable
pub fn dcdic(&mut self) -> DCDIC_W<'_>[src]
Bit 18 - Data Carrier Detect Input Change Interrupt Enable
pub fn ctsic(&mut self) -> CTSIC_W<'_>[src]
Bit 19 - Clear to Send Input Change Interrupt Enable
pub fn mane(&mut self) -> MANE_W<'_>[src]
Bit 24 - Manchester Error Interrupt Enable
impl W<u32, Reg<u32, _IER_SPI_MODE>>[src]
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 0 - RXRDY Interrupt Enable
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 1 - TXRDY Interrupt Enable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 3
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 4
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 5 - Overrun Error Interrupt Enable
pub fn txempty(&mut self) -> TXEMPTY_W<'_>[src]
Bit 9 - TXEMPTY Interrupt Enable
pub fn unre(&mut self) -> UNRE_W<'_>[src]
Bit 10 - SPI Underrun Error Interrupt Enable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 11
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 12
impl W<u32, Reg<u32, _IDR>>[src]
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 0 - RXRDY Interrupt Disable
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 1 - TXRDY Interrupt Disable
pub fn rxbrk(&mut self) -> RXBRK_W<'_>[src]
Bit 2 - Receiver Break Interrupt Disable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 3 - End of Receive Transfer Interrupt Disable (available in all USART modes of operation)
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 4 - End of Transmit Interrupt Disable (available in all USART modes of operation)
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 5 - Overrun Error Interrupt Enable
pub fn frame(&mut self) -> FRAME_W<'_>[src]
Bit 6 - Framing Error Interrupt Disable
pub fn pare(&mut self) -> PARE_W<'_>[src]
Bit 7 - Parity Error Interrupt Disable
pub fn timeout(&mut self) -> TIMEOUT_W<'_>[src]
Bit 8 - Time-out Interrupt Disable
pub fn txempty(&mut self) -> TXEMPTY_W<'_>[src]
Bit 9 - TXEMPTY Interrupt Disable
pub fn iter(&mut self) -> ITER_W<'_>[src]
Bit 10 - Max Number of Repetitions Reached Interrupt Disable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 11 - Buffer Empty Interrupt Disable (available in all USART modes of operation)
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 12 - Buffer Full Interrupt Disable (available in all USART modes of operation)
pub fn nack(&mut self) -> NACK_W<'_>[src]
Bit 13 - Non AcknowledgeInterrupt Disable
pub fn riic(&mut self) -> RIIC_W<'_>[src]
Bit 16 - Ring Indicator Input Change Disable
pub fn dsric(&mut self) -> DSRIC_W<'_>[src]
Bit 17 - Data Set Ready Input Change Disable
pub fn dcdic(&mut self) -> DCDIC_W<'_>[src]
Bit 18 - Data Carrier Detect Input Change Interrupt Disable
pub fn ctsic(&mut self) -> CTSIC_W<'_>[src]
Bit 19 - Clear to Send Input Change Interrupt Disable
pub fn mane(&mut self) -> MANE_W<'_>[src]
Bit 24 - Manchester Error Interrupt Disable
impl W<u32, Reg<u32, _IDR_SPI_MODE>>[src]
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 0 - RXRDY Interrupt Disable
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 1 - TXRDY Interrupt Disable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 3
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 4
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 5 - Overrun Error Interrupt Disable
pub fn txempty(&mut self) -> TXEMPTY_W<'_>[src]
Bit 9 - TXEMPTY Interrupt Disable
pub fn unre(&mut self) -> UNRE_W<'_>[src]
Bit 10 - SPI Underrun Error Interrupt Disable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 11
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 12
impl W<u32, Reg<u32, _THR>>[src]
pub fn txchr(&mut self) -> TXCHR_W<'_>[src]
Bits 0:8 - Character to be Transmitted
pub fn txsynh(&mut self) -> TXSYNH_W<'_>[src]
Bit 15 - Sync Field to be Transmitted
impl W<u32, Reg<u32, _BRGR>>[src]
pub fn cd(&mut self) -> CD_W<'_>[src]
Bits 0:15 - Clock Divider
pub fn fp(&mut self) -> FP_W<'_>[src]
Bits 16:18 - Fractional Part
impl W<u32, Reg<u32, _RTOR>>[src]
impl W<u32, Reg<u32, _TTGR>>[src]
impl W<u32, Reg<u32, _FIDI>>[src]
pub fn fi_di_ratio(&mut self) -> FI_DI_RATIO_W<'_>[src]
Bits 0:10 - FI Over DI Ratio Value
impl W<u32, Reg<u32, _IF>>[src]
pub fn irda_filter(&mut self) -> IRDA_FILTER_W<'_>[src]
Bits 0:7 - IrDA Filter
impl W<u32, Reg<u32, _MAN>>[src]
pub fn tx_pl(&mut self) -> TX_PL_W<'_>[src]
Bits 0:3 - Transmitter Preamble Length
pub fn tx_pp(&mut self) -> TX_PP_W<'_>[src]
Bits 8:9 - Transmitter Preamble Pattern
pub fn tx_mpol(&mut self) -> TX_MPOL_W<'_>[src]
Bit 12 - Transmitter Manchester Polarity
pub fn rx_pl(&mut self) -> RX_PL_W<'_>[src]
Bits 16:19 - Receiver Preamble Length
pub fn rx_pp(&mut self) -> RX_PP_W<'_>[src]
Bits 24:25 - Receiver Preamble Pattern detected
pub fn rx_mpol(&mut self) -> RX_MPOL_W<'_>[src]
Bit 28 - Receiver Manchester Polarity
pub fn one(&mut self) -> ONE_W<'_>[src]
Bit 29 - Must Be Set to 1
pub fn drift(&mut self) -> DRIFT_W<'_>[src]
Bit 30 - Drift Compensation
impl W<u32, Reg<u32, _WPMR>>[src]
pub fn wpen(&mut self) -> WPEN_W<'_>[src]
Bit 0 - Write Protection Enable
pub fn wpkey(&mut self) -> WPKEY_W<'_>[src]
Bits 8:31 - Write Protection Key
impl W<u32, Reg<u32, _RPR>>[src]
impl W<u32, Reg<u32, _RCR>>[src]
impl W<u32, Reg<u32, _TPR>>[src]
impl W<u32, Reg<u32, _TCR>>[src]
impl W<u32, Reg<u32, _RNPR>>[src]
impl W<u32, Reg<u32, _RNCR>>[src]
impl W<u32, Reg<u32, _TNPR>>[src]
impl W<u32, Reg<u32, _TNCR>>[src]
impl W<u32, Reg<u32, _PTCR>>[src]
pub fn rxten(&mut self) -> RXTEN_W<'_>[src]
Bit 0 - Receiver Transfer Enable
pub fn rxtdis(&mut self) -> RXTDIS_W<'_>[src]
Bit 1 - Receiver Transfer Disable
pub fn txten(&mut self) -> TXTEN_W<'_>[src]
Bit 8 - Transmitter Transfer Enable
pub fn txtdis(&mut self) -> TXTDIS_W<'_>[src]
Bit 9 - Transmitter Transfer Disable
impl W<u32, Reg<u32, _CR>>[src]
pub fn rstrx(&mut self) -> RSTRX_W<'_>[src]
Bit 2 - Reset Receiver
pub fn rsttx(&mut self) -> RSTTX_W<'_>[src]
Bit 3 - Reset Transmitter
pub fn rxen(&mut self) -> RXEN_W<'_>[src]
Bit 4 - Receiver Enable
pub fn rxdis(&mut self) -> RXDIS_W<'_>[src]
Bit 5 - Receiver Disable
pub fn txen(&mut self) -> TXEN_W<'_>[src]
Bit 6 - Transmitter Enable
pub fn txdis(&mut self) -> TXDIS_W<'_>[src]
Bit 7 - Transmitter Disable
pub fn rststa(&mut self) -> RSTSTA_W<'_>[src]
Bit 8 - Reset Status Bits
pub fn sttbrk(&mut self) -> STTBRK_W<'_>[src]
Bit 9 - Start Break
pub fn stpbrk(&mut self) -> STPBRK_W<'_>[src]
Bit 10 - Stop Break
pub fn sttto(&mut self) -> STTTO_W<'_>[src]
Bit 11 - Start Time-out
pub fn senda(&mut self) -> SENDA_W<'_>[src]
Bit 12 - Send Address
pub fn rstit(&mut self) -> RSTIT_W<'_>[src]
Bit 13 - Reset Iterations
pub fn rstnack(&mut self) -> RSTNACK_W<'_>[src]
Bit 14 - Reset Non Acknowledge
pub fn retto(&mut self) -> RETTO_W<'_>[src]
Bit 15 - Rearm Time-out
pub fn dtren(&mut self) -> DTREN_W<'_>[src]
Bit 16 - Data Terminal Ready Enable
pub fn dtrdis(&mut self) -> DTRDIS_W<'_>[src]
Bit 17 - Data Terminal Ready Disable
pub fn rtsen(&mut self) -> RTSEN_W<'_>[src]
Bit 18 - Request to Send Enable
pub fn rtsdis(&mut self) -> RTSDIS_W<'_>[src]
Bit 19 - Request to Send Disable
impl W<u32, Reg<u32, _CR_SPI_MODE>>[src]
pub fn rstrx(&mut self) -> RSTRX_W<'_>[src]
Bit 2 - Reset Receiver
pub fn rsttx(&mut self) -> RSTTX_W<'_>[src]
Bit 3 - Reset Transmitter
pub fn rxen(&mut self) -> RXEN_W<'_>[src]
Bit 4 - Receiver Enable
pub fn rxdis(&mut self) -> RXDIS_W<'_>[src]
Bit 5 - Receiver Disable
pub fn txen(&mut self) -> TXEN_W<'_>[src]
Bit 6 - Transmitter Enable
pub fn txdis(&mut self) -> TXDIS_W<'_>[src]
Bit 7 - Transmitter Disable
pub fn rststa(&mut self) -> RSTSTA_W<'_>[src]
Bit 8 - Reset Status Bits
pub fn fcs(&mut self) -> FCS_W<'_>[src]
Bit 18 - Force SPI Chip Select
pub fn rcs(&mut self) -> RCS_W<'_>[src]
Bit 19 - Release SPI Chip Select
impl W<u32, Reg<u32, _MR>>[src]
pub fn usart_mode(&mut self) -> USART_MODE_W<'_>[src]
Bits 0:3 - USART Mode of Operation
pub fn usclks(&mut self) -> USCLKS_W<'_>[src]
Bits 4:5 - Clock Selection
pub fn chrl(&mut self) -> CHRL_W<'_>[src]
Bits 6:7 - Character Length
pub fn sync(&mut self) -> SYNC_W<'_>[src]
Bit 8 - Synchronous Mode Select
pub fn par(&mut self) -> PAR_W<'_>[src]
Bits 9:11 - Parity Type
pub fn nbstop(&mut self) -> NBSTOP_W<'_>[src]
Bits 12:13 - Number of Stop Bits
pub fn chmode(&mut self) -> CHMODE_W<'_>[src]
Bits 14:15 - Channel Mode
pub fn msbf(&mut self) -> MSBF_W<'_>[src]
Bit 16 - Bit Order
pub fn mode9(&mut self) -> MODE9_W<'_>[src]
Bit 17 - 9-bit Character Length
pub fn clko(&mut self) -> CLKO_W<'_>[src]
Bit 18 - Clock Output Select
pub fn over(&mut self) -> OVER_W<'_>[src]
Bit 19 - Oversampling Mode
pub fn inack(&mut self) -> INACK_W<'_>[src]
Bit 20 - Inhibit Non Acknowledge
pub fn dsnack(&mut self) -> DSNACK_W<'_>[src]
Bit 21 - Disable Successive NACK
pub fn var_sync(&mut self) -> VAR_SYNC_W<'_>[src]
Bit 22 - Variable Synchronization of Command/Data Sync Start Frame Delimiter
pub fn invdata(&mut self) -> INVDATA_W<'_>[src]
Bit 23 - Inverted Data
pub fn max_iteration(&mut self) -> MAX_ITERATION_W<'_>[src]
Bits 24:26 - Maximum Number of Automatic Iteration
pub fn filter(&mut self) -> FILTER_W<'_>[src]
Bit 28 - Infrared Receive Line Filter
pub fn man(&mut self) -> MAN_W<'_>[src]
Bit 29 - Manchester Encoder/Decoder Enable
pub fn modsync(&mut self) -> MODSYNC_W<'_>[src]
Bit 30 - Manchester Synchronization Mode
pub fn onebit(&mut self) -> ONEBIT_W<'_>[src]
Bit 31 - Start Frame Delimiter Selector
impl W<u32, Reg<u32, _MR_SPI_MODE>>[src]
pub fn usart_mode(&mut self) -> USART_MODE_W<'_>[src]
Bits 0:3 - USART Mode of Operation
pub fn usclks(&mut self) -> USCLKS_W<'_>[src]
Bits 4:5 - Clock Selection
pub fn chrl(&mut self) -> CHRL_W<'_>[src]
Bits 6:7 - Character Length
pub fn cpha(&mut self) -> CPHA_W<'_>[src]
Bit 8 - SPI Clock Phase
pub fn cpol(&mut self) -> CPOL_W<'_>[src]
Bit 16 - SPI Clock Polarity
pub fn wrdbt(&mut self) -> WRDBT_W<'_>[src]
Bit 20 - Wait Read Data Before Transfer
impl W<u32, Reg<u32, _IER>>[src]
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 0 - RXRDY Interrupt Enable
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 1 - TXRDY Interrupt Enable
pub fn rxbrk(&mut self) -> RXBRK_W<'_>[src]
Bit 2 - Receiver Break Interrupt Enable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 3 - End of Receive Transfer Interrupt Enable (available in all USART modes of operation)
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 4 - End of Transmit Interrupt Enable (available in all USART modes of operation)
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 5 - Overrun Error Interrupt Enable
pub fn frame(&mut self) -> FRAME_W<'_>[src]
Bit 6 - Framing Error Interrupt Enable
pub fn pare(&mut self) -> PARE_W<'_>[src]
Bit 7 - Parity Error Interrupt Enable
pub fn timeout(&mut self) -> TIMEOUT_W<'_>[src]
Bit 8 - Time-out Interrupt Enable
pub fn txempty(&mut self) -> TXEMPTY_W<'_>[src]
Bit 9 - TXEMPTY Interrupt Enable
pub fn iter(&mut self) -> ITER_W<'_>[src]
Bit 10 - Max number of Repetitions Reached Interrupt Enable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 11 - Buffer Empty Interrupt Enable (available in all USART modes of operation)
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 12 - Buffer Full Interrupt Enable (available in all USART modes of operation)
pub fn nack(&mut self) -> NACK_W<'_>[src]
Bit 13 - Non AcknowledgeInterrupt Enable
pub fn riic(&mut self) -> RIIC_W<'_>[src]
Bit 16 - Ring Indicator Input Change Enable
pub fn dsric(&mut self) -> DSRIC_W<'_>[src]
Bit 17 - Data Set Ready Input Change Enable
pub fn dcdic(&mut self) -> DCDIC_W<'_>[src]
Bit 18 - Data Carrier Detect Input Change Interrupt Enable
pub fn ctsic(&mut self) -> CTSIC_W<'_>[src]
Bit 19 - Clear to Send Input Change Interrupt Enable
pub fn mane(&mut self) -> MANE_W<'_>[src]
Bit 24 - Manchester Error Interrupt Enable
impl W<u32, Reg<u32, _IER_SPI_MODE>>[src]
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 0 - RXRDY Interrupt Enable
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 1 - TXRDY Interrupt Enable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 3
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 4
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 5 - Overrun Error Interrupt Enable
pub fn txempty(&mut self) -> TXEMPTY_W<'_>[src]
Bit 9 - TXEMPTY Interrupt Enable
pub fn unre(&mut self) -> UNRE_W<'_>[src]
Bit 10 - SPI Underrun Error Interrupt Enable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 11
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 12
impl W<u32, Reg<u32, _IDR>>[src]
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 0 - RXRDY Interrupt Disable
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 1 - TXRDY Interrupt Disable
pub fn rxbrk(&mut self) -> RXBRK_W<'_>[src]
Bit 2 - Receiver Break Interrupt Disable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 3 - End of Receive Transfer Interrupt Disable (available in all USART modes of operation)
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 4 - End of Transmit Interrupt Disable (available in all USART modes of operation)
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 5 - Overrun Error Interrupt Enable
pub fn frame(&mut self) -> FRAME_W<'_>[src]
Bit 6 - Framing Error Interrupt Disable
pub fn pare(&mut self) -> PARE_W<'_>[src]
Bit 7 - Parity Error Interrupt Disable
pub fn timeout(&mut self) -> TIMEOUT_W<'_>[src]
Bit 8 - Time-out Interrupt Disable
pub fn txempty(&mut self) -> TXEMPTY_W<'_>[src]
Bit 9 - TXEMPTY Interrupt Disable
pub fn iter(&mut self) -> ITER_W<'_>[src]
Bit 10 - Max Number of Repetitions Reached Interrupt Disable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 11 - Buffer Empty Interrupt Disable (available in all USART modes of operation)
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 12 - Buffer Full Interrupt Disable (available in all USART modes of operation)
pub fn nack(&mut self) -> NACK_W<'_>[src]
Bit 13 - Non AcknowledgeInterrupt Disable
pub fn riic(&mut self) -> RIIC_W<'_>[src]
Bit 16 - Ring Indicator Input Change Disable
pub fn dsric(&mut self) -> DSRIC_W<'_>[src]
Bit 17 - Data Set Ready Input Change Disable
pub fn dcdic(&mut self) -> DCDIC_W<'_>[src]
Bit 18 - Data Carrier Detect Input Change Interrupt Disable
pub fn ctsic(&mut self) -> CTSIC_W<'_>[src]
Bit 19 - Clear to Send Input Change Interrupt Disable
pub fn mane(&mut self) -> MANE_W<'_>[src]
Bit 24 - Manchester Error Interrupt Disable
impl W<u32, Reg<u32, _IDR_SPI_MODE>>[src]
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 0 - RXRDY Interrupt Disable
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 1 - TXRDY Interrupt Disable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 3
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 4
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 5 - Overrun Error Interrupt Disable
pub fn txempty(&mut self) -> TXEMPTY_W<'_>[src]
Bit 9 - TXEMPTY Interrupt Disable
pub fn unre(&mut self) -> UNRE_W<'_>[src]
Bit 10 - SPI Underrun Error Interrupt Disable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 11
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 12
impl W<u32, Reg<u32, _THR>>[src]
pub fn txchr(&mut self) -> TXCHR_W<'_>[src]
Bits 0:8 - Character to be Transmitted
pub fn txsynh(&mut self) -> TXSYNH_W<'_>[src]
Bit 15 - Sync Field to be Transmitted
impl W<u32, Reg<u32, _BRGR>>[src]
pub fn cd(&mut self) -> CD_W<'_>[src]
Bits 0:15 - Clock Divider
pub fn fp(&mut self) -> FP_W<'_>[src]
Bits 16:18 - Fractional Part
impl W<u32, Reg<u32, _RTOR>>[src]
impl W<u32, Reg<u32, _TTGR>>[src]
impl W<u32, Reg<u32, _FIDI>>[src]
pub fn fi_di_ratio(&mut self) -> FI_DI_RATIO_W<'_>[src]
Bits 0:10 - FI Over DI Ratio Value
impl W<u32, Reg<u32, _IF>>[src]
pub fn irda_filter(&mut self) -> IRDA_FILTER_W<'_>[src]
Bits 0:7 - IrDA Filter
impl W<u32, Reg<u32, _MAN>>[src]
pub fn tx_pl(&mut self) -> TX_PL_W<'_>[src]
Bits 0:3 - Transmitter Preamble Length
pub fn tx_pp(&mut self) -> TX_PP_W<'_>[src]
Bits 8:9 - Transmitter Preamble Pattern
pub fn tx_mpol(&mut self) -> TX_MPOL_W<'_>[src]
Bit 12 - Transmitter Manchester Polarity
pub fn rx_pl(&mut self) -> RX_PL_W<'_>[src]
Bits 16:19 - Receiver Preamble Length
pub fn rx_pp(&mut self) -> RX_PP_W<'_>[src]
Bits 24:25 - Receiver Preamble Pattern detected
pub fn rx_mpol(&mut self) -> RX_MPOL_W<'_>[src]
Bit 28 - Receiver Manchester Polarity
pub fn one(&mut self) -> ONE_W<'_>[src]
Bit 29 - Must Be Set to 1
pub fn drift(&mut self) -> DRIFT_W<'_>[src]
Bit 30 - Drift Compensation
impl W<u32, Reg<u32, _WPMR>>[src]
pub fn wpen(&mut self) -> WPEN_W<'_>[src]
Bit 0 - Write Protection Enable
pub fn wpkey(&mut self) -> WPKEY_W<'_>[src]
Bits 8:31 - Write Protection Key
impl W<u32, Reg<u32, _RPR>>[src]
impl W<u32, Reg<u32, _RCR>>[src]
impl W<u32, Reg<u32, _TPR>>[src]
impl W<u32, Reg<u32, _TCR>>[src]
impl W<u32, Reg<u32, _RNPR>>[src]
impl W<u32, Reg<u32, _RNCR>>[src]
impl W<u32, Reg<u32, _TNPR>>[src]
impl W<u32, Reg<u32, _TNCR>>[src]
impl W<u32, Reg<u32, _PTCR>>[src]
pub fn rxten(&mut self) -> RXTEN_W<'_>[src]
Bit 0 - Receiver Transfer Enable
pub fn rxtdis(&mut self) -> RXTDIS_W<'_>[src]
Bit 1 - Receiver Transfer Disable
pub fn txten(&mut self) -> TXTEN_W<'_>[src]
Bit 8 - Transmitter Transfer Enable
pub fn txtdis(&mut self) -> TXTDIS_W<'_>[src]
Bit 9 - Transmitter Transfer Disable
impl W<u32, Reg<u32, _GLB_STAT>>[src]
pub fn fadden(&mut self) -> FADDEN_W<'_>[src]
Bit 0 - Function Address Enable
pub fn confg(&mut self) -> CONFG_W<'_>[src]
Bit 1 - Configured
pub fn esr(&mut self) -> ESR_W<'_>[src]
Bit 2 - Enable Send Resume
pub fn rsminpr(&mut self) -> RSMINPR_W<'_>[src]
Bit 3
pub fn rmwupe(&mut self) -> RMWUPE_W<'_>[src]
Bit 4 - Remote Wake Up Enable
impl W<u32, Reg<u32, _FADDR>>[src]
pub fn fadd(&mut self) -> FADD_W<'_>[src]
Bits 0:6 - Function Address Value
pub fn fen(&mut self) -> FEN_W<'_>[src]
Bit 8 - Function Enable
impl W<u32, Reg<u32, _IER>>[src]
pub fn ep0int(&mut self) -> EP0INT_W<'_>[src]
Bit 0 - Enable Endpoint 0 Interrupt
pub fn ep1int(&mut self) -> EP1INT_W<'_>[src]
Bit 1 - Enable Endpoint 1 Interrupt
pub fn ep2int(&mut self) -> EP2INT_W<'_>[src]
Bit 2 - Enable Endpoint 2Interrupt
pub fn ep3int(&mut self) -> EP3INT_W<'_>[src]
Bit 3 - Enable Endpoint 3 Interrupt
pub fn ep4int(&mut self) -> EP4INT_W<'_>[src]
Bit 4 - Enable Endpoint 4 Interrupt
pub fn ep5int(&mut self) -> EP5INT_W<'_>[src]
Bit 5 - Enable Endpoint 5 Interrupt
pub fn ep6int(&mut self) -> EP6INT_W<'_>[src]
Bit 6 - Enable Endpoint 6 Interrupt
pub fn ep7int(&mut self) -> EP7INT_W<'_>[src]
Bit 7 - Enable Endpoint 7 Interrupt
pub fn rxsusp(&mut self) -> RXSUSP_W<'_>[src]
Bit 8 - Enable UDP Suspend Interrupt
pub fn rxrsm(&mut self) -> RXRSM_W<'_>[src]
Bit 9 - Enable UDP Resume Interrupt
pub fn extrsm(&mut self) -> EXTRSM_W<'_>[src]
Bit 10
pub fn sofint(&mut self) -> SOFINT_W<'_>[src]
Bit 11 - Enable Start Of Frame Interrupt
pub fn wakeup(&mut self) -> WAKEUP_W<'_>[src]
Bit 13 - Enable UDP bus Wakeup Interrupt
impl W<u32, Reg<u32, _IDR>>[src]
pub fn ep0int(&mut self) -> EP0INT_W<'_>[src]
Bit 0 - Disable Endpoint 0 Interrupt
pub fn ep1int(&mut self) -> EP1INT_W<'_>[src]
Bit 1 - Disable Endpoint 1 Interrupt
pub fn ep2int(&mut self) -> EP2INT_W<'_>[src]
Bit 2 - Disable Endpoint 2 Interrupt
pub fn ep3int(&mut self) -> EP3INT_W<'_>[src]
Bit 3 - Disable Endpoint 3 Interrupt
pub fn ep4int(&mut self) -> EP4INT_W<'_>[src]
Bit 4 - Disable Endpoint 4 Interrupt
pub fn ep5int(&mut self) -> EP5INT_W<'_>[src]
Bit 5 - Disable Endpoint 5 Interrupt
pub fn ep6int(&mut self) -> EP6INT_W<'_>[src]
Bit 6 - Disable Endpoint 6 Interrupt
pub fn ep7int(&mut self) -> EP7INT_W<'_>[src]
Bit 7 - Disable Endpoint 7 Interrupt
pub fn rxsusp(&mut self) -> RXSUSP_W<'_>[src]
Bit 8 - Disable UDP Suspend Interrupt
pub fn rxrsm(&mut self) -> RXRSM_W<'_>[src]
Bit 9 - Disable UDP Resume Interrupt
pub fn extrsm(&mut self) -> EXTRSM_W<'_>[src]
Bit 10
pub fn sofint(&mut self) -> SOFINT_W<'_>[src]
Bit 11 - Disable Start Of Frame Interrupt
pub fn wakeup(&mut self) -> WAKEUP_W<'_>[src]
Bit 13 - Disable USB Bus Interrupt
impl W<u32, Reg<u32, _ICR>>[src]
pub fn rxsusp(&mut self) -> RXSUSP_W<'_>[src]
Bit 8 - Clear UDP Suspend Interrupt
pub fn rxrsm(&mut self) -> RXRSM_W<'_>[src]
Bit 9 - Clear UDP Resume Interrupt
pub fn extrsm(&mut self) -> EXTRSM_W<'_>[src]
Bit 10
pub fn sofint(&mut self) -> SOFINT_W<'_>[src]
Bit 11 - Clear Start Of Frame Interrupt
pub fn endbusres(&mut self) -> ENDBUSRES_W<'_>[src]
Bit 12 - Clear End of Bus Reset Interrupt
pub fn wakeup(&mut self) -> WAKEUP_W<'_>[src]
Bit 13 - Clear Wakeup Interrupt
impl W<u32, Reg<u32, _RST_EP>>[src]
pub fn ep0(&mut self) -> EP0_W<'_>[src]
Bit 0 - Reset Endpoint 0
pub fn ep1(&mut self) -> EP1_W<'_>[src]
Bit 1 - Reset Endpoint 1
pub fn ep2(&mut self) -> EP2_W<'_>[src]
Bit 2 - Reset Endpoint 2
pub fn ep3(&mut self) -> EP3_W<'_>[src]
Bit 3 - Reset Endpoint 3
pub fn ep4(&mut self) -> EP4_W<'_>[src]
Bit 4 - Reset Endpoint 4
pub fn ep5(&mut self) -> EP5_W<'_>[src]
Bit 5 - Reset Endpoint 5
pub fn ep6(&mut self) -> EP6_W<'_>[src]
Bit 6 - Reset Endpoint 6
pub fn ep7(&mut self) -> EP7_W<'_>[src]
Bit 7 - Reset Endpoint 7
impl W<u32, Reg<u32, _CSR>>[src]
pub fn txcomp(&mut self) -> TXCOMP_W<'_>[src]
Bit 0 - Generates an IN Packet with Data Previously Written in the DPR
pub fn rx_data_bk0(&mut self) -> RX_DATA_BK0_W<'_>[src]
Bit 1 - Receive Data Bank 0
pub fn rxsetup(&mut self) -> RXSETUP_W<'_>[src]
Bit 2 - Received Setup
pub fn stallsent(&mut self) -> STALLSENT_W<'_>[src]
Bit 3 - Stall Sent
pub fn txpktrdy(&mut self) -> TXPKTRDY_W<'_>[src]
Bit 4 - Transmit Packet Ready
pub fn forcestall(&mut self) -> FORCESTALL_W<'_>[src]
Bit 5 - Force Stall (used by Control, Bulk and Isochronous Endpoints)
pub fn rx_data_bk1(&mut self) -> RX_DATA_BK1_W<'_>[src]
Bit 6 - Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
pub fn dir(&mut self) -> DIR_W<'_>[src]
Bit 7 - Transfer Direction (only available for control endpoints)
pub fn eptype(&mut self) -> EPTYPE_W<'_>[src]
Bits 8:10 - Endpoint Type
pub fn dtgle(&mut self) -> DTGLE_W<'_>[src]
Bit 11 - Data Toggle
pub fn epeds(&mut self) -> EPEDS_W<'_>[src]
Bit 15 - Endpoint Enable Disable
pub fn rxbytecnt(&mut self) -> RXBYTECNT_W<'_>[src]
Bits 16:26 - Number of Bytes Available in the FIFO
impl W<u32, Reg<u32, _CSR0_ISOCHRONOUS>>[src]
pub fn txcomp(&mut self) -> TXCOMP_W<'_>[src]
Bit 0 - Generates an IN Packet with Data Previously Written in the DPR
pub fn rx_data_bk0(&mut self) -> RX_DATA_BK0_W<'_>[src]
Bit 1 - Receive Data Bank 0
pub fn rxsetup(&mut self) -> RXSETUP_W<'_>[src]
Bit 2 - Received Setup
pub fn isoerror(&mut self) -> ISOERROR_W<'_>[src]
Bit 3 - A CRC error has been detected in an isochronous transfer
pub fn txpktrdy(&mut self) -> TXPKTRDY_W<'_>[src]
Bit 4 - Transmit Packet Ready
pub fn forcestall(&mut self) -> FORCESTALL_W<'_>[src]
Bit 5 - Force Stall (used by Control, Bulk and Isochronous Endpoints)
pub fn rx_data_bk1(&mut self) -> RX_DATA_BK1_W<'_>[src]
Bit 6 - Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
pub fn dir(&mut self) -> DIR_W<'_>[src]
Bit 7 - Transfer Direction (only available for control endpoints)
pub fn eptype(&mut self) -> EPTYPE_W<'_>[src]
Bits 8:10 - Endpoint Type
pub fn dtgle(&mut self) -> DTGLE_W<'_>[src]
Bit 11 - Data Toggle
pub fn epeds(&mut self) -> EPEDS_W<'_>[src]
Bit 15 - Endpoint Enable Disable
pub fn rxbytecnt(&mut self) -> RXBYTECNT_W<'_>[src]
Bits 16:26 - Number of Bytes Available in the FIFO
impl W<u32, Reg<u32, _FDR>>[src]
pub fn fifo_data(&mut self) -> FIFO_DATA_W<'_>[src]
Bits 0:7 - FIFO Data Value
impl W<u32, Reg<u32, _TXVC>>[src]
pub fn txvdis(&mut self) -> TXVDIS_W<'_>[src]
Bit 8 - Transceiver Disable
pub fn puon(&mut self) -> PUON_W<'_>[src]
Bit 9 - Pull-up On
impl W<u32, Reg<u32, _CR>>[src]
pub fn swrst(&mut self) -> SWRST_W<'_>[src]
Bit 0 - Software Reset
pub fn start(&mut self) -> START_W<'_>[src]
Bit 1 - Start Conversion
pub fn autocal(&mut self) -> AUTOCAL_W<'_>[src]
Bit 3 - Automatic Calibration of ADC
impl W<u32, Reg<u32, _MR>>[src]
pub fn trgen(&mut self) -> TRGEN_W<'_>[src]
Bit 0 - Trigger Enable
pub fn trgsel(&mut self) -> TRGSEL_W<'_>[src]
Bits 1:3 - Trigger Selection
pub fn sleep(&mut self) -> SLEEP_W<'_>[src]
Bit 5 - Sleep Mode
pub fn fwup(&mut self) -> FWUP_W<'_>[src]
Bit 6 - Fast Wake Up
pub fn freerun(&mut self) -> FREERUN_W<'_>[src]
Bit 7 - Free Run Mode
pub fn prescal(&mut self) -> PRESCAL_W<'_>[src]
Bits 8:15 - Prescaler Rate Selection
pub fn startup(&mut self) -> STARTUP_W<'_>[src]
Bits 16:19 - Start Up Time
pub fn settling(&mut self) -> SETTLING_W<'_>[src]
Bits 20:21 - Analog Settling Time
pub fn anach(&mut self) -> ANACH_W<'_>[src]
Bit 23 - Analog Change
pub fn tracktim(&mut self) -> TRACKTIM_W<'_>[src]
Bits 24:27 - Tracking Time
pub fn transfer(&mut self) -> TRANSFER_W<'_>[src]
Bits 28:29 - Transfer Period
pub fn useq(&mut self) -> USEQ_W<'_>[src]
Bit 31 - Use Sequence Enable
impl W<u32, Reg<u32, _SEQR1>>[src]
pub fn usch1(&mut self) -> USCH1_W<'_>[src]
Bits 0:3 - User Sequence Number 1
pub fn usch2(&mut self) -> USCH2_W<'_>[src]
Bits 4:7 - User Sequence Number 2
pub fn usch3(&mut self) -> USCH3_W<'_>[src]
Bits 8:11 - User Sequence Number 3
pub fn usch4(&mut self) -> USCH4_W<'_>[src]
Bits 12:15 - User Sequence Number 4
pub fn usch5(&mut self) -> USCH5_W<'_>[src]
Bits 16:19 - User Sequence Number 5
pub fn usch6(&mut self) -> USCH6_W<'_>[src]
Bits 20:23 - User Sequence Number 6
pub fn usch7(&mut self) -> USCH7_W<'_>[src]
Bits 24:27 - User Sequence Number 7
pub fn usch8(&mut self) -> USCH8_W<'_>[src]
Bits 28:31 - User Sequence Number 8
impl W<u32, Reg<u32, _SEQR2>>[src]
pub fn usch9(&mut self) -> USCH9_W<'_>[src]
Bits 0:3 - User Sequence Number 9
pub fn usch10(&mut self) -> USCH10_W<'_>[src]
Bits 4:7 - User Sequence Number 10
pub fn usch11(&mut self) -> USCH11_W<'_>[src]
Bits 8:11 - User Sequence Number 11
pub fn usch12(&mut self) -> USCH12_W<'_>[src]
Bits 12:15 - User Sequence Number 12
pub fn usch13(&mut self) -> USCH13_W<'_>[src]
Bits 16:19 - User Sequence Number 13
pub fn usch14(&mut self) -> USCH14_W<'_>[src]
Bits 20:23 - User Sequence Number 14
pub fn usch15(&mut self) -> USCH15_W<'_>[src]
Bits 24:27 - User Sequence Number 15
impl W<u32, Reg<u32, _CHER>>[src]
pub fn ch0(&mut self) -> CH0_W<'_>[src]
Bit 0 - Channel 0 Enable
pub fn ch1(&mut self) -> CH1_W<'_>[src]
Bit 1 - Channel 1 Enable
pub fn ch2(&mut self) -> CH2_W<'_>[src]
Bit 2 - Channel 2 Enable
pub fn ch3(&mut self) -> CH3_W<'_>[src]
Bit 3 - Channel 3 Enable
pub fn ch4(&mut self) -> CH4_W<'_>[src]
Bit 4 - Channel 4 Enable
pub fn ch5(&mut self) -> CH5_W<'_>[src]
Bit 5 - Channel 5 Enable
pub fn ch6(&mut self) -> CH6_W<'_>[src]
Bit 6 - Channel 6 Enable
pub fn ch7(&mut self) -> CH7_W<'_>[src]
Bit 7 - Channel 7 Enable
pub fn ch8(&mut self) -> CH8_W<'_>[src]
Bit 8 - Channel 8 Enable
pub fn ch9(&mut self) -> CH9_W<'_>[src]
Bit 9 - Channel 9 Enable
pub fn ch10(&mut self) -> CH10_W<'_>[src]
Bit 10 - Channel 10 Enable
pub fn ch11(&mut self) -> CH11_W<'_>[src]
Bit 11 - Channel 11 Enable
pub fn ch12(&mut self) -> CH12_W<'_>[src]
Bit 12 - Channel 12 Enable
pub fn ch13(&mut self) -> CH13_W<'_>[src]
Bit 13 - Channel 13 Enable
pub fn ch14(&mut self) -> CH14_W<'_>[src]
Bit 14 - Channel 14 Enable
pub fn ch15(&mut self) -> CH15_W<'_>[src]
Bit 15 - Channel 15 Enable
impl W<u32, Reg<u32, _CHDR>>[src]
pub fn ch0(&mut self) -> CH0_W<'_>[src]
Bit 0 - Channel 0 Disable
pub fn ch1(&mut self) -> CH1_W<'_>[src]
Bit 1 - Channel 1 Disable
pub fn ch2(&mut self) -> CH2_W<'_>[src]
Bit 2 - Channel 2 Disable
pub fn ch3(&mut self) -> CH3_W<'_>[src]
Bit 3 - Channel 3 Disable
pub fn ch4(&mut self) -> CH4_W<'_>[src]
Bit 4 - Channel 4 Disable
pub fn ch5(&mut self) -> CH5_W<'_>[src]
Bit 5 - Channel 5 Disable
pub fn ch6(&mut self) -> CH6_W<'_>[src]
Bit 6 - Channel 6 Disable
pub fn ch7(&mut self) -> CH7_W<'_>[src]
Bit 7 - Channel 7 Disable
pub fn ch8(&mut self) -> CH8_W<'_>[src]
Bit 8 - Channel 8 Disable
pub fn ch9(&mut self) -> CH9_W<'_>[src]
Bit 9 - Channel 9 Disable
pub fn ch10(&mut self) -> CH10_W<'_>[src]
Bit 10 - Channel 10 Disable
pub fn ch11(&mut self) -> CH11_W<'_>[src]
Bit 11 - Channel 11 Disable
pub fn ch12(&mut self) -> CH12_W<'_>[src]
Bit 12 - Channel 12 Disable
pub fn ch13(&mut self) -> CH13_W<'_>[src]
Bit 13 - Channel 13 Disable
pub fn ch14(&mut self) -> CH14_W<'_>[src]
Bit 14 - Channel 14 Disable
pub fn ch15(&mut self) -> CH15_W<'_>[src]
Bit 15 - Channel 15 Disable
impl W<u32, Reg<u32, _IER>>[src]
pub fn eoc0(&mut self) -> EOC0_W<'_>[src]
Bit 0 - End of Conversion Interrupt Enable 0
pub fn eoc1(&mut self) -> EOC1_W<'_>[src]
Bit 1 - End of Conversion Interrupt Enable 1
pub fn eoc2(&mut self) -> EOC2_W<'_>[src]
Bit 2 - End of Conversion Interrupt Enable 2
pub fn eoc3(&mut self) -> EOC3_W<'_>[src]
Bit 3 - End of Conversion Interrupt Enable 3
pub fn eoc4(&mut self) -> EOC4_W<'_>[src]
Bit 4 - End of Conversion Interrupt Enable 4
pub fn eoc5(&mut self) -> EOC5_W<'_>[src]
Bit 5 - End of Conversion Interrupt Enable 5
pub fn eoc6(&mut self) -> EOC6_W<'_>[src]
Bit 6 - End of Conversion Interrupt Enable 6
pub fn eoc7(&mut self) -> EOC7_W<'_>[src]
Bit 7 - End of Conversion Interrupt Enable 7
pub fn eoc8(&mut self) -> EOC8_W<'_>[src]
Bit 8 - End of Conversion Interrupt Enable 8
pub fn eoc9(&mut self) -> EOC9_W<'_>[src]
Bit 9 - End of Conversion Interrupt Enable 9
pub fn eoc10(&mut self) -> EOC10_W<'_>[src]
Bit 10 - End of Conversion Interrupt Enable 10
pub fn eoc11(&mut self) -> EOC11_W<'_>[src]
Bit 11 - End of Conversion Interrupt Enable 11
pub fn eoc12(&mut self) -> EOC12_W<'_>[src]
Bit 12 - End of Conversion Interrupt Enable 12
pub fn eoc13(&mut self) -> EOC13_W<'_>[src]
Bit 13 - End of Conversion Interrupt Enable 13
pub fn eoc14(&mut self) -> EOC14_W<'_>[src]
Bit 14 - End of Conversion Interrupt Enable 14
pub fn eoc15(&mut self) -> EOC15_W<'_>[src]
Bit 15 - End of Conversion Interrupt Enable 15
pub fn eocal(&mut self) -> EOCAL_W<'_>[src]
Bit 23 - End of Calibration Sequence
pub fn drdy(&mut self) -> DRDY_W<'_>[src]
Bit 24 - Data Ready Interrupt Enable
pub fn govre(&mut self) -> GOVRE_W<'_>[src]
Bit 25 - General Overrun Error Interrupt Enable
pub fn compe(&mut self) -> COMPE_W<'_>[src]
Bit 26 - Comparison Event Interrupt Enable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 27 - End of Receive Buffer Interrupt Enable
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 28 - Receive Buffer Full Interrupt Enable
impl W<u32, Reg<u32, _IDR>>[src]
pub fn eoc0(&mut self) -> EOC0_W<'_>[src]
Bit 0 - End of Conversion Interrupt Disable 0
pub fn eoc1(&mut self) -> EOC1_W<'_>[src]
Bit 1 - End of Conversion Interrupt Disable 1
pub fn eoc2(&mut self) -> EOC2_W<'_>[src]
Bit 2 - End of Conversion Interrupt Disable 2
pub fn eoc3(&mut self) -> EOC3_W<'_>[src]
Bit 3 - End of Conversion Interrupt Disable 3
pub fn eoc4(&mut self) -> EOC4_W<'_>[src]
Bit 4 - End of Conversion Interrupt Disable 4
pub fn eoc5(&mut self) -> EOC5_W<'_>[src]
Bit 5 - End of Conversion Interrupt Disable 5
pub fn eoc6(&mut self) -> EOC6_W<'_>[src]
Bit 6 - End of Conversion Interrupt Disable 6
pub fn eoc7(&mut self) -> EOC7_W<'_>[src]
Bit 7 - End of Conversion Interrupt Disable 7
pub fn eoc8(&mut self) -> EOC8_W<'_>[src]
Bit 8 - End of Conversion Interrupt Disable 8
pub fn eoc9(&mut self) -> EOC9_W<'_>[src]
Bit 9 - End of Conversion Interrupt Disable 9
pub fn eoc10(&mut self) -> EOC10_W<'_>[src]
Bit 10 - End of Conversion Interrupt Disable 10
pub fn eoc11(&mut self) -> EOC11_W<'_>[src]
Bit 11 - End of Conversion Interrupt Disable 11
pub fn eoc12(&mut self) -> EOC12_W<'_>[src]
Bit 12 - End of Conversion Interrupt Disable 12
pub fn eoc13(&mut self) -> EOC13_W<'_>[src]
Bit 13 - End of Conversion Interrupt Disable 13
pub fn eoc14(&mut self) -> EOC14_W<'_>[src]
Bit 14 - End of Conversion Interrupt Disable 14
pub fn eoc15(&mut self) -> EOC15_W<'_>[src]
Bit 15 - End of Conversion Interrupt Disable 15
pub fn eocal(&mut self) -> EOCAL_W<'_>[src]
Bit 23 - End of Calibration Sequence
pub fn drdy(&mut self) -> DRDY_W<'_>[src]
Bit 24 - Data Ready Interrupt Disable
pub fn govre(&mut self) -> GOVRE_W<'_>[src]
Bit 25 - General Overrun Error Interrupt Disable
pub fn compe(&mut self) -> COMPE_W<'_>[src]
Bit 26 - Comparison Event Interrupt Disable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 27 - End of Receive Buffer Interrupt Disable
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 28 - Receive Buffer Full Interrupt Disable
impl W<u32, Reg<u32, _EMR>>[src]
pub fn cmpmode(&mut self) -> CMPMODE_W<'_>[src]
Bits 0:1 - Comparison Mode
pub fn cmpsel(&mut self) -> CMPSEL_W<'_>[src]
Bits 4:7 - Comparison Selected Channel
pub fn cmpall(&mut self) -> CMPALL_W<'_>[src]
Bit 9 - Compare All Channels
pub fn tag(&mut self) -> TAG_W<'_>[src]
Bit 24 - Tag of the ADC_LDCR
impl W<u32, Reg<u32, _CWR>>[src]
pub fn lowthres(&mut self) -> LOWTHRES_W<'_>[src]
Bits 0:11 - Low Threshold
pub fn highthres(&mut self) -> HIGHTHRES_W<'_>[src]
Bits 16:27 - High Threshold
impl W<u32, Reg<u32, _CGR>>[src]
pub fn gain0(&mut self) -> GAIN0_W<'_>[src]
Bits 0:1 - Gain for Channel 0
pub fn gain1(&mut self) -> GAIN1_W<'_>[src]
Bits 2:3 - Gain for Channel 1
pub fn gain2(&mut self) -> GAIN2_W<'_>[src]
Bits 4:5 - Gain for Channel 2
pub fn gain3(&mut self) -> GAIN3_W<'_>[src]
Bits 6:7 - Gain for Channel 3
pub fn gain4(&mut self) -> GAIN4_W<'_>[src]
Bits 8:9 - Gain for Channel 4
pub fn gain5(&mut self) -> GAIN5_W<'_>[src]
Bits 10:11 - Gain for Channel 5
pub fn gain6(&mut self) -> GAIN6_W<'_>[src]
Bits 12:13 - Gain for Channel 6
pub fn gain7(&mut self) -> GAIN7_W<'_>[src]
Bits 14:15 - Gain for Channel 7
pub fn gain8(&mut self) -> GAIN8_W<'_>[src]
Bits 16:17 - Gain for Channel 8
pub fn gain9(&mut self) -> GAIN9_W<'_>[src]
Bits 18:19 - Gain for Channel 9
pub fn gain10(&mut self) -> GAIN10_W<'_>[src]
Bits 20:21 - Gain for Channel 10
pub fn gain11(&mut self) -> GAIN11_W<'_>[src]
Bits 22:23 - Gain for Channel 11
pub fn gain12(&mut self) -> GAIN12_W<'_>[src]
Bits 24:25 - Gain for Channel 12
pub fn gain13(&mut self) -> GAIN13_W<'_>[src]
Bits 26:27 - Gain for Channel 13
pub fn gain14(&mut self) -> GAIN14_W<'_>[src]
Bits 28:29 - Gain for Channel 14
pub fn gain15(&mut self) -> GAIN15_W<'_>[src]
Bits 30:31 - Gain for Channel 15
impl W<u32, Reg<u32, _COR>>[src]
pub fn off0(&mut self) -> OFF0_W<'_>[src]
Bit 0 - Offset for channel 0
pub fn off1(&mut self) -> OFF1_W<'_>[src]
Bit 1 - Offset for channel 1
pub fn off2(&mut self) -> OFF2_W<'_>[src]
Bit 2 - Offset for channel 2
pub fn off3(&mut self) -> OFF3_W<'_>[src]
Bit 3 - Offset for channel 3
pub fn off4(&mut self) -> OFF4_W<'_>[src]
Bit 4 - Offset for channel 4
pub fn off5(&mut self) -> OFF5_W<'_>[src]
Bit 5 - Offset for channel 5
pub fn off6(&mut self) -> OFF6_W<'_>[src]
Bit 6 - Offset for channel 6
pub fn off7(&mut self) -> OFF7_W<'_>[src]
Bit 7 - Offset for channel 7
pub fn off8(&mut self) -> OFF8_W<'_>[src]
Bit 8 - Offset for channel 8
pub fn off9(&mut self) -> OFF9_W<'_>[src]
Bit 9 - Offset for channel 9
pub fn off10(&mut self) -> OFF10_W<'_>[src]
Bit 10 - Offset for channel 10
pub fn off11(&mut self) -> OFF11_W<'_>[src]
Bit 11 - Offset for channel 11
pub fn off12(&mut self) -> OFF12_W<'_>[src]
Bit 12 - Offset for channel 12
pub fn off13(&mut self) -> OFF13_W<'_>[src]
Bit 13 - Offset for channel 13
pub fn off14(&mut self) -> OFF14_W<'_>[src]
Bit 14 - Offset for channel 14
pub fn off15(&mut self) -> OFF15_W<'_>[src]
Bit 15 - Offset for channel 15
pub fn diff0(&mut self) -> DIFF0_W<'_>[src]
Bit 16 - Differential inputs for channel 0
pub fn diff1(&mut self) -> DIFF1_W<'_>[src]
Bit 17 - Differential inputs for channel 1
pub fn diff2(&mut self) -> DIFF2_W<'_>[src]
Bit 18 - Differential inputs for channel 2
pub fn diff3(&mut self) -> DIFF3_W<'_>[src]
Bit 19 - Differential inputs for channel 3
pub fn diff4(&mut self) -> DIFF4_W<'_>[src]
Bit 20 - Differential inputs for channel 4
pub fn diff5(&mut self) -> DIFF5_W<'_>[src]
Bit 21 - Differential inputs for channel 5
pub fn diff6(&mut self) -> DIFF6_W<'_>[src]
Bit 22 - Differential inputs for channel 6
pub fn diff7(&mut self) -> DIFF7_W<'_>[src]
Bit 23 - Differential inputs for channel 7
pub fn diff8(&mut self) -> DIFF8_W<'_>[src]
Bit 24 - Differential inputs for channel 8
pub fn diff9(&mut self) -> DIFF9_W<'_>[src]
Bit 25 - Differential inputs for channel 9
pub fn diff10(&mut self) -> DIFF10_W<'_>[src]
Bit 26 - Differential inputs for channel 10
pub fn diff11(&mut self) -> DIFF11_W<'_>[src]
Bit 27 - Differential inputs for channel 11
pub fn diff12(&mut self) -> DIFF12_W<'_>[src]
Bit 28 - Differential inputs for channel 12
pub fn diff13(&mut self) -> DIFF13_W<'_>[src]
Bit 29 - Differential inputs for channel 13
pub fn diff14(&mut self) -> DIFF14_W<'_>[src]
Bit 30 - Differential inputs for channel 14
pub fn diff15(&mut self) -> DIFF15_W<'_>[src]
Bit 31 - Differential inputs for channel 15
impl W<u32, Reg<u32, _ACR>>[src]
pub fn tson(&mut self) -> TSON_W<'_>[src]
Bit 4 - Temperature Sensor On
pub fn ibctl(&mut self) -> IBCTL_W<'_>[src]
Bits 8:9 - ADC Bias Current Control
impl W<u32, Reg<u32, _WPMR>>[src]
pub fn wpen(&mut self) -> WPEN_W<'_>[src]
Bit 0 - Write Protection Enable
pub fn wpkey(&mut self) -> WPKEY_W<'_>[src]
Bits 8:31 - Write Protection Key
impl W<u32, Reg<u32, _RPR>>[src]
impl W<u32, Reg<u32, _RCR>>[src]
impl W<u32, Reg<u32, _RNPR>>[src]
impl W<u32, Reg<u32, _RNCR>>[src]
impl W<u32, Reg<u32, _PTCR>>[src]
pub fn rxten(&mut self) -> RXTEN_W<'_>[src]
Bit 0 - Receiver Transfer Enable
pub fn rxtdis(&mut self) -> RXTDIS_W<'_>[src]
Bit 1 - Receiver Transfer Disable
pub fn txten(&mut self) -> TXTEN_W<'_>[src]
Bit 8 - Transmitter Transfer Enable
pub fn txtdis(&mut self) -> TXTDIS_W<'_>[src]
Bit 9 - Transmitter Transfer Disable
impl W<u32, Reg<u32, _CR>>[src]
impl W<u32, Reg<u32, _MR>>[src]
pub fn trgen(&mut self) -> TRGEN_W<'_>[src]
Bit 0 - Trigger Enable
pub fn trgsel(&mut self) -> TRGSEL_W<'_>[src]
Bits 1:3 - Trigger Selection
pub fn word(&mut self) -> WORD_W<'_>[src]
Bit 4 - Word Transfer
pub fn sleep(&mut self) -> SLEEP_W<'_>[src]
Bit 5 - Sleep Mode
pub fn fastwkup(&mut self) -> FASTWKUP_W<'_>[src]
Bit 6 - Fast Wake-up Mode
pub fn refresh(&mut self) -> REFRESH_W<'_>[src]
Bits 8:15 - Automatic Refresh Period
pub fn user_sel(&mut self) -> USER_SEL_W<'_>[src]
Bits 16:17 - User Channel Selection
pub fn tag(&mut self) -> TAG_W<'_>[src]
Bit 20 - Tag Selection Mode
pub fn maxs(&mut self) -> MAXS_W<'_>[src]
Bit 21 - Max Speed Mode
pub fn startup(&mut self) -> STARTUP_W<'_>[src]
Bits 24:29 - Startup Time Selection
impl W<u32, Reg<u32, _CHER>>[src]
pub fn ch0(&mut self) -> CH0_W<'_>[src]
Bit 0 - Channel 0 Enable
pub fn ch1(&mut self) -> CH1_W<'_>[src]
Bit 1 - Channel 1 Enable
impl W<u32, Reg<u32, _CHDR>>[src]
pub fn ch0(&mut self) -> CH0_W<'_>[src]
Bit 0 - Channel 0 Disable
pub fn ch1(&mut self) -> CH1_W<'_>[src]
Bit 1 - Channel 1 Disable
impl W<u32, Reg<u32, _CDR>>[src]
impl W<u32, Reg<u32, _IER>>[src]
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 0 - Transmit Ready Interrupt Enable
pub fn eoc(&mut self) -> EOC_W<'_>[src]
Bit 1 - End of Conversion Interrupt Enable
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 2 - End of Transmit Buffer Interrupt Enable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 3 - Transmit Buffer Empty Interrupt Enable
impl W<u32, Reg<u32, _IDR>>[src]
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 0 - Transmit Ready Interrupt Disable.
pub fn eoc(&mut self) -> EOC_W<'_>[src]
Bit 1 - End of Conversion Interrupt Disable
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 2 - End of Transmit Buffer Interrupt Disable
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 3 - Transmit Buffer Empty Interrupt Disable
impl W<u32, Reg<u32, _ACR>>[src]
pub fn ibctlch0(&mut self) -> IBCTLCH0_W<'_>[src]
Bits 0:1 - Analog Output Current Control
pub fn ibctlch1(&mut self) -> IBCTLCH1_W<'_>[src]
Bits 2:3 - Analog Output Current Control
pub fn ibctldaccore(&mut self) -> IBCTLDACCORE_W<'_>[src]
Bits 8:9 - Bias Current Control for DAC Core
impl W<u32, Reg<u32, _WPMR>>[src]
pub fn wpen(&mut self) -> WPEN_W<'_>[src]
Bit 0 - Write Protection Enable
pub fn wpkey(&mut self) -> WPKEY_W<'_>[src]
Bits 8:31 - Write Protection KEY
impl W<u32, Reg<u32, _TPR>>[src]
impl W<u32, Reg<u32, _TCR>>[src]
impl W<u32, Reg<u32, _TNPR>>[src]
impl W<u32, Reg<u32, _TNCR>>[src]
impl W<u32, Reg<u32, _PTCR>>[src]
pub fn rxten(&mut self) -> RXTEN_W<'_>[src]
Bit 0 - Receiver Transfer Enable
pub fn rxtdis(&mut self) -> RXTDIS_W<'_>[src]
Bit 1 - Receiver Transfer Disable
pub fn txten(&mut self) -> TXTEN_W<'_>[src]
Bit 8 - Transmitter Transfer Enable
pub fn txtdis(&mut self) -> TXTDIS_W<'_>[src]
Bit 9 - Transmitter Transfer Disable
impl W<u32, Reg<u32, _CR>>[src]
impl W<u32, Reg<u32, _MR>>[src]
pub fn selminus(&mut self) -> SELMINUS_W<'_>[src]
Bits 0:2 - Selection for Minus Comparator Input
pub fn selplus(&mut self) -> SELPLUS_W<'_>[src]
Bits 4:6 - Selection For Plus Comparator Input
pub fn acen(&mut self) -> ACEN_W<'_>[src]
Bit 8 - Analog Comparator Enable
pub fn edgetyp(&mut self) -> EDGETYP_W<'_>[src]
Bits 9:10 - Edge Type
pub fn inv(&mut self) -> INV_W<'_>[src]
Bit 12 - Invert Comparator Output
pub fn selfs(&mut self) -> SELFS_W<'_>[src]
Bit 13 - Selection Of Fault Source
pub fn fe(&mut self) -> FE_W<'_>[src]
Bit 14 - Fault Enable
impl W<u32, Reg<u32, _IER>>[src]
impl W<u32, Reg<u32, _IDR>>[src]
impl W<u32, Reg<u32, _ACR>>[src]
pub fn isel(&mut self) -> ISEL_W<'_>[src]
Bit 0 - Current Selection
pub fn hyst(&mut self) -> HYST_W<'_>[src]
Bits 1:2 - Hysteresis Selection
impl W<u32, Reg<u32, _WPMR>>[src]
pub fn wpen(&mut self) -> WPEN_W<'_>[src]
Bit 0 - Write Protection Enable
pub fn wpkey(&mut self) -> WPKEY_W<'_>[src]
Bits 8:31 - Write Protection Key
impl W<u32, Reg<u32, _DSCR>>[src]
impl W<u32, Reg<u32, _DMA_EN>>[src]
impl W<u32, Reg<u32, _DMA_DIS>>[src]
impl W<u32, Reg<u32, _DMA_IER>>[src]
impl W<u32, Reg<u32, _DMA_IDR>>[src]
impl W<u32, Reg<u32, _CR>>[src]
impl W<u32, Reg<u32, _MR>>[src]
pub fn enable(&mut self) -> ENABLE_W<'_>[src]
Bit 0 - CRC Enable
pub fn compare(&mut self) -> COMPARE_W<'_>[src]
Bit 1 - CRC Compare
pub fn ptype(&mut self) -> PTYPE_W<'_>[src]
Bits 2:3 - Primitive Polynomial
pub fn divider(&mut self) -> DIVIDER_W<'_>[src]
Bits 4:7 - Request Divider
impl W<u32, Reg<u32, _IER>>[src]
impl W<u32, Reg<u32, _IDR>>[src]
impl W<u32, Reg<u32, _CFG>>[src]
impl W<u32, Reg<u32, _CTRL>>[src]
impl W<u32, Reg<u32, _MAINT0>>[src]
impl W<u32, Reg<u32, _MAINT1>>[src]
pub fn index(&mut self) -> INDEX_W<'_>[src]
Bits 4:8 - Invalidate Index
pub fn way(&mut self) -> WAY_W<'_>[src]
Bits 30:31 - Invalidate Way
impl W<u32, Reg<u32, _MCFG>>[src]
impl W<u32, Reg<u32, _MEN>>[src]
impl W<u32, Reg<u32, _MCTRL>>[src]
impl W<u32, Reg<u32, _MATRIX_MCFG>>[src]
impl W<u32, Reg<u32, _MATRIX_SCFG>>[src]
pub fn slot_cycle(&mut self) -> SLOT_CYCLE_W<'_>[src]
Bits 0:7 - Maximum Number of Allowed Cycles for a Burst
pub fn defmstr_type(&mut self) -> DEFMSTR_TYPE_W<'_>[src]
Bits 16:17 - Default Master Type
pub fn fixed_defmstr(&mut self) -> FIXED_DEFMSTR_W<'_>[src]
Bits 18:20 - Fixed Default Master
pub fn arbt(&mut self) -> ARBT_W<'_>[src]
Bits 24:25 - Arbitration Type
impl W<u32, Reg<u32, _MATRIX_PRAS0>>[src]
pub fn m0pr(&mut self) -> M0PR_W<'_>[src]
Bits 0:1 - Master 0 Priority
pub fn m1pr(&mut self) -> M1PR_W<'_>[src]
Bits 4:5 - Master 1 Priority
pub fn m2pr(&mut self) -> M2PR_W<'_>[src]
Bits 8:9 - Master 2 Priority
pub fn m3pr(&mut self) -> M3PR_W<'_>[src]
Bits 12:13 - Master 3 Priority
pub fn m4pr(&mut self) -> M4PR_W<'_>[src]
Bits 16:17 - Master 4 Priority
impl W<u32, Reg<u32, _MATRIX_PRAS1>>[src]
pub fn m0pr(&mut self) -> M0PR_W<'_>[src]
Bits 0:1 - Master 0 Priority
pub fn m1pr(&mut self) -> M1PR_W<'_>[src]
Bits 4:5 - Master 1 Priority
pub fn m2pr(&mut self) -> M2PR_W<'_>[src]
Bits 8:9 - Master 2 Priority
pub fn m3pr(&mut self) -> M3PR_W<'_>[src]
Bits 12:13 - Master 3 Priority
pub fn m4pr(&mut self) -> M4PR_W<'_>[src]
Bits 16:17 - Master 4 Priority
impl W<u32, Reg<u32, _MATRIX_PRAS2>>[src]
pub fn m0pr(&mut self) -> M0PR_W<'_>[src]
Bits 0:1 - Master 0 Priority
pub fn m1pr(&mut self) -> M1PR_W<'_>[src]
Bits 4:5 - Master 1 Priority
pub fn m2pr(&mut self) -> M2PR_W<'_>[src]
Bits 8:9 - Master 2 Priority
pub fn m3pr(&mut self) -> M3PR_W<'_>[src]
Bits 12:13 - Master 3 Priority
pub fn m4pr(&mut self) -> M4PR_W<'_>[src]
Bits 16:17 - Master 4 Priority
impl W<u32, Reg<u32, _MATRIX_PRAS3>>[src]
pub fn m0pr(&mut self) -> M0PR_W<'_>[src]
Bits 0:1 - Master 0 Priority
pub fn m1pr(&mut self) -> M1PR_W<'_>[src]
Bits 4:5 - Master 1 Priority
pub fn m2pr(&mut self) -> M2PR_W<'_>[src]
Bits 8:9 - Master 2 Priority
pub fn m3pr(&mut self) -> M3PR_W<'_>[src]
Bits 12:13 - Master 3 Priority
pub fn m4pr(&mut self) -> M4PR_W<'_>[src]
Bits 16:17 - Master 4 Priority
impl W<u32, Reg<u32, _MATRIX_PRAS4>>[src]
pub fn m0pr(&mut self) -> M0PR_W<'_>[src]
Bits 0:1 - Master 0 Priority
pub fn m1pr(&mut self) -> M1PR_W<'_>[src]
Bits 4:5 - Master 1 Priority
pub fn m2pr(&mut self) -> M2PR_W<'_>[src]
Bits 8:9 - Master 2 Priority
pub fn m3pr(&mut self) -> M3PR_W<'_>[src]
Bits 12:13 - Master 3 Priority
pub fn m4pr(&mut self) -> M4PR_W<'_>[src]
Bits 16:17 - Master 4 Priority
impl W<u32, Reg<u32, _CCFG_SYSIO>>[src]
pub fn sysio4(&mut self) -> SYSIO4_W<'_>[src]
Bit 4 - PB4 or TDI Assignment
pub fn sysio5(&mut self) -> SYSIO5_W<'_>[src]
Bit 5 - PB5 or TDO/TRACESWO Assignment
pub fn sysio6(&mut self) -> SYSIO6_W<'_>[src]
Bit 6 - PB6 or TMS/SWDIO Assignment
pub fn sysio7(&mut self) -> SYSIO7_W<'_>[src]
Bit 7 - PB7 or TCK/SWCLK Assignment
pub fn sysio10(&mut self) -> SYSIO10_W<'_>[src]
Bit 10 - PB10 or DDM Assignment
pub fn sysio11(&mut self) -> SYSIO11_W<'_>[src]
Bit 11 - PB11 or DDP Assignment
pub fn sysio12(&mut self) -> SYSIO12_W<'_>[src]
Bit 12 - PB12 or ERASE Assignment
impl W<u32, Reg<u32, _CCFG_SMCNFCS>>[src]
pub fn smc_nfcs0(&mut self) -> SMC_NFCS0_W<'_>[src]
Bit 0 - SMC NAND Flash Chip Select 0 Assignment
pub fn smc_nfcs1(&mut self) -> SMC_NFCS1_W<'_>[src]
Bit 1 - SMC NAND Flash Chip Select 1 Assignment
pub fn smc_nfcs2(&mut self) -> SMC_NFCS2_W<'_>[src]
Bit 2 - SMC NAND Flash Chip Select 2 Assignment
pub fn smc_nfcs3(&mut self) -> SMC_NFCS3_W<'_>[src]
Bit 3 - SMC NAND Flash Chip Select 3 Assignment
impl W<u32, Reg<u32, _MATRIX_WPMR>>[src]
pub fn wpen(&mut self) -> WPEN_W<'_>[src]
Bit 0 - Write Protection Enable
pub fn wpkey(&mut self) -> WPKEY_W<'_>[src]
Bits 8:31 - Write Protect Key
impl W<u32, Reg<u32, _PMC_SCER>>[src]
pub fn udp(&mut self) -> UDP_W<'_>[src]
Bit 7 - USB Device Port Clock Enable
pub fn pck0(&mut self) -> PCK0_W<'_>[src]
Bit 8 - Programmable Clock 0 Output Enable
pub fn pck1(&mut self) -> PCK1_W<'_>[src]
Bit 9 - Programmable Clock 1 Output Enable
pub fn pck2(&mut self) -> PCK2_W<'_>[src]
Bit 10 - Programmable Clock 2 Output Enable
impl W<u32, Reg<u32, _PMC_SCDR>>[src]
pub fn udp(&mut self) -> UDP_W<'_>[src]
Bit 7 - USB Device Port Clock Disable
pub fn pck0(&mut self) -> PCK0_W<'_>[src]
Bit 8 - Programmable Clock 0 Output Disable
pub fn pck1(&mut self) -> PCK1_W<'_>[src]
Bit 9 - Programmable Clock 1 Output Disable
pub fn pck2(&mut self) -> PCK2_W<'_>[src]
Bit 10 - Programmable Clock 2 Output Disable
impl W<u32, Reg<u32, _PMC_PCER0>>[src]
pub fn pid8(&mut self) -> PID8_W<'_>[src]
Bit 8 - Peripheral Clock 8 Enable
pub fn pid9(&mut self) -> PID9_W<'_>[src]
Bit 9 - Peripheral Clock 9 Enable
pub fn pid10(&mut self) -> PID10_W<'_>[src]
Bit 10 - Peripheral Clock 10 Enable
pub fn pid11(&mut self) -> PID11_W<'_>[src]
Bit 11 - Peripheral Clock 11 Enable
pub fn pid12(&mut self) -> PID12_W<'_>[src]
Bit 12 - Peripheral Clock 12 Enable
pub fn pid13(&mut self) -> PID13_W<'_>[src]
Bit 13 - Peripheral Clock 13 Enable
pub fn pid14(&mut self) -> PID14_W<'_>[src]
Bit 14 - Peripheral Clock 14 Enable
pub fn pid15(&mut self) -> PID15_W<'_>[src]
Bit 15 - Peripheral Clock 15 Enable
pub fn pid16(&mut self) -> PID16_W<'_>[src]
Bit 16 - Peripheral Clock 16 Enable
pub fn pid17(&mut self) -> PID17_W<'_>[src]
Bit 17 - Peripheral Clock 17 Enable
pub fn pid18(&mut self) -> PID18_W<'_>[src]
Bit 18 - Peripheral Clock 18 Enable
pub fn pid19(&mut self) -> PID19_W<'_>[src]
Bit 19 - Peripheral Clock 19 Enable
pub fn pid20(&mut self) -> PID20_W<'_>[src]
Bit 20 - Peripheral Clock 20 Enable
pub fn pid21(&mut self) -> PID21_W<'_>[src]
Bit 21 - Peripheral Clock 21 Enable
pub fn pid22(&mut self) -> PID22_W<'_>[src]
Bit 22 - Peripheral Clock 22 Enable
pub fn pid23(&mut self) -> PID23_W<'_>[src]
Bit 23 - Peripheral Clock 23 Enable
pub fn pid24(&mut self) -> PID24_W<'_>[src]
Bit 24 - Peripheral Clock 24 Enable
pub fn pid25(&mut self) -> PID25_W<'_>[src]
Bit 25 - Peripheral Clock 25 Enable
pub fn pid26(&mut self) -> PID26_W<'_>[src]
Bit 26 - Peripheral Clock 26 Enable
pub fn pid27(&mut self) -> PID27_W<'_>[src]
Bit 27 - Peripheral Clock 27 Enable
pub fn pid28(&mut self) -> PID28_W<'_>[src]
Bit 28 - Peripheral Clock 28 Enable
pub fn pid29(&mut self) -> PID29_W<'_>[src]
Bit 29 - Peripheral Clock 29 Enable
pub fn pid30(&mut self) -> PID30_W<'_>[src]
Bit 30 - Peripheral Clock 30 Enable
pub fn pid31(&mut self) -> PID31_W<'_>[src]
Bit 31 - Peripheral Clock 31 Enable
impl W<u32, Reg<u32, _PMC_PCDR0>>[src]
pub fn pid8(&mut self) -> PID8_W<'_>[src]
Bit 8 - Peripheral Clock 8 Disable
pub fn pid9(&mut self) -> PID9_W<'_>[src]
Bit 9 - Peripheral Clock 9 Disable
pub fn pid10(&mut self) -> PID10_W<'_>[src]
Bit 10 - Peripheral Clock 10 Disable
pub fn pid11(&mut self) -> PID11_W<'_>[src]
Bit 11 - Peripheral Clock 11 Disable
pub fn pid12(&mut self) -> PID12_W<'_>[src]
Bit 12 - Peripheral Clock 12 Disable
pub fn pid13(&mut self) -> PID13_W<'_>[src]
Bit 13 - Peripheral Clock 13 Disable
pub fn pid14(&mut self) -> PID14_W<'_>[src]
Bit 14 - Peripheral Clock 14 Disable
pub fn pid15(&mut self) -> PID15_W<'_>[src]
Bit 15 - Peripheral Clock 15 Disable
pub fn pid16(&mut self) -> PID16_W<'_>[src]
Bit 16 - Peripheral Clock 16 Disable
pub fn pid17(&mut self) -> PID17_W<'_>[src]
Bit 17 - Peripheral Clock 17 Disable
pub fn pid18(&mut self) -> PID18_W<'_>[src]
Bit 18 - Peripheral Clock 18 Disable
pub fn pid19(&mut self) -> PID19_W<'_>[src]
Bit 19 - Peripheral Clock 19 Disable
pub fn pid20(&mut self) -> PID20_W<'_>[src]
Bit 20 - Peripheral Clock 20 Disable
pub fn pid21(&mut self) -> PID21_W<'_>[src]
Bit 21 - Peripheral Clock 21 Disable
pub fn pid22(&mut self) -> PID22_W<'_>[src]
Bit 22 - Peripheral Clock 22 Disable
pub fn pid23(&mut self) -> PID23_W<'_>[src]
Bit 23 - Peripheral Clock 23 Disable
pub fn pid24(&mut self) -> PID24_W<'_>[src]
Bit 24 - Peripheral Clock 24 Disable
pub fn pid25(&mut self) -> PID25_W<'_>[src]
Bit 25 - Peripheral Clock 25 Disable
pub fn pid26(&mut self) -> PID26_W<'_>[src]
Bit 26 - Peripheral Clock 26 Disable
pub fn pid27(&mut self) -> PID27_W<'_>[src]
Bit 27 - Peripheral Clock 27 Disable
pub fn pid28(&mut self) -> PID28_W<'_>[src]
Bit 28 - Peripheral Clock 28 Disable
pub fn pid29(&mut self) -> PID29_W<'_>[src]
Bit 29 - Peripheral Clock 29 Disable
pub fn pid30(&mut self) -> PID30_W<'_>[src]
Bit 30 - Peripheral Clock 30 Disable
pub fn pid31(&mut self) -> PID31_W<'_>[src]
Bit 31 - Peripheral Clock 31 Disable
impl W<u32, Reg<u32, _CKGR_MOR>>[src]
pub fn moscxten(&mut self) -> MOSCXTEN_W<'_>[src]
Bit 0 - Main Crystal Oscillator Enable
pub fn moscxtby(&mut self) -> MOSCXTBY_W<'_>[src]
Bit 1 - Main Crystal Oscillator Bypass
pub fn waitmode(&mut self) -> WAITMODE_W<'_>[src]
Bit 2 - Wait Mode Command
pub fn moscrcen(&mut self) -> MOSCRCEN_W<'_>[src]
Bit 3 - Main On-Chip RC Oscillator Enable
pub fn moscrcf(&mut self) -> MOSCRCF_W<'_>[src]
Bits 4:6 - Main On-Chip RC Oscillator Frequency Selection
pub fn moscxtst(&mut self) -> MOSCXTST_W<'_>[src]
Bits 8:15 - Main Crystal Oscillator Start-up Time
pub fn key(&mut self) -> KEY_W<'_>[src]
Bits 16:23 - Write Access Password
pub fn moscsel(&mut self) -> MOSCSEL_W<'_>[src]
Bit 24 - Main Oscillator Selection
pub fn cfden(&mut self) -> CFDEN_W<'_>[src]
Bit 25 - Clock Failure Detector Enable
impl W<u32, Reg<u32, _CKGR_MCFR>>[src]
pub fn mainf(&mut self) -> MAINF_W<'_>[src]
Bits 0:15 - Main Clock Frequency
pub fn mainfrdy(&mut self) -> MAINFRDY_W<'_>[src]
Bit 16 - Main Clock Ready
pub fn rcmeas(&mut self) -> RCMEAS_W<'_>[src]
Bit 20 - RC Oscillator Frequency Measure (write-only)
impl W<u32, Reg<u32, _CKGR_PLLAR>>[src]
pub fn diva(&mut self) -> DIVA_W<'_>[src]
Bits 0:7 - PLLA Front_End Divider
pub fn pllacount(&mut self) -> PLLACOUNT_W<'_>[src]
Bits 8:13 - PLLA Counter
pub fn mula(&mut self) -> MULA_W<'_>[src]
Bits 16:26 - PLLA Multiplier
pub fn one(&mut self) -> ONE_W<'_>[src]
Bit 29 - Must Be Set to 1
impl W<u32, Reg<u32, _CKGR_PLLBR>>[src]
pub fn divb(&mut self) -> DIVB_W<'_>[src]
Bits 0:7 - PLLB Front-End Divider
pub fn pllbcount(&mut self) -> PLLBCOUNT_W<'_>[src]
Bits 8:13 - PLLB Counter
pub fn mulb(&mut self) -> MULB_W<'_>[src]
Bits 16:26 - PLLB Multiplier
impl W<u32, Reg<u32, _PMC_MCKR>>[src]
pub fn css(&mut self) -> CSS_W<'_>[src]
Bits 0:1 - Master Clock Source Selection
pub fn pres(&mut self) -> PRES_W<'_>[src]
Bits 4:6 - Processor Clock Prescaler
pub fn plladiv2(&mut self) -> PLLADIV2_W<'_>[src]
Bit 12 - PLLA Divisor by 2
pub fn pllbdiv2(&mut self) -> PLLBDIV2_W<'_>[src]
Bit 13 - PLLB Divisor by 2
impl W<u32, Reg<u32, _PMC_USB>>[src]
pub fn usbs(&mut self) -> USBS_W<'_>[src]
Bit 0 - USB Input Clock Selection
pub fn usbdiv(&mut self) -> USBDIV_W<'_>[src]
Bits 8:11 - Divider for USB Clock
impl W<u32, Reg<u32, _PMC_PCK>>[src]
pub fn css(&mut self) -> CSS_W<'_>[src]
Bits 0:2 - Master Clock Source Selection
pub fn pres(&mut self) -> PRES_W<'_>[src]
Bits 4:6 - Programmable Clock Prescaler
impl W<u32, Reg<u32, _PMC_IER>>[src]
pub fn moscxts(&mut self) -> MOSCXTS_W<'_>[src]
Bit 0 - Main Crystal Oscillator Status Interrupt Enable
pub fn locka(&mut self) -> LOCKA_W<'_>[src]
Bit 1 - PLLA Lock Interrupt Enable
pub fn lockb(&mut self) -> LOCKB_W<'_>[src]
Bit 2 - PLLB Lock Interrupt Enable
pub fn mckrdy(&mut self) -> MCKRDY_W<'_>[src]
Bit 3 - Master Clock Ready Interrupt Enable
pub fn pckrdy0(&mut self) -> PCKRDY0_W<'_>[src]
Bit 8 - Programmable Clock Ready 0 Interrupt Enable
pub fn pckrdy1(&mut self) -> PCKRDY1_W<'_>[src]
Bit 9 - Programmable Clock Ready 1 Interrupt Enable
pub fn pckrdy2(&mut self) -> PCKRDY2_W<'_>[src]
Bit 10 - Programmable Clock Ready 2 Interrupt Enable
pub fn moscsels(&mut self) -> MOSCSELS_W<'_>[src]
Bit 16 - Main Oscillator Selection Status Interrupt Enable
pub fn moscrcs(&mut self) -> MOSCRCS_W<'_>[src]
Bit 17 - Main On-Chip RC Status Interrupt Enable
pub fn cfdev(&mut self) -> CFDEV_W<'_>[src]
Bit 18 - Clock Failure Detector Event Interrupt Enable
impl W<u32, Reg<u32, _PMC_IDR>>[src]
pub fn moscxts(&mut self) -> MOSCXTS_W<'_>[src]
Bit 0 - Main Crystal Oscillator Status Interrupt Disable
pub fn locka(&mut self) -> LOCKA_W<'_>[src]
Bit 1 - PLLA Lock Interrupt Disable
pub fn lockb(&mut self) -> LOCKB_W<'_>[src]
Bit 2 - PLLB Lock Interrupt Disable
pub fn mckrdy(&mut self) -> MCKRDY_W<'_>[src]
Bit 3 - Master Clock Ready Interrupt Disable
pub fn pckrdy0(&mut self) -> PCKRDY0_W<'_>[src]
Bit 8 - Programmable Clock Ready 0 Interrupt Disable
pub fn pckrdy1(&mut self) -> PCKRDY1_W<'_>[src]
Bit 9 - Programmable Clock Ready 1 Interrupt Disable
pub fn pckrdy2(&mut self) -> PCKRDY2_W<'_>[src]
Bit 10 - Programmable Clock Ready 2 Interrupt Disable
pub fn moscsels(&mut self) -> MOSCSELS_W<'_>[src]
Bit 16 - Main Oscillator Selection Status Interrupt Disable
pub fn moscrcs(&mut self) -> MOSCRCS_W<'_>[src]
Bit 17 - Main On-Chip RC Status Interrupt Disable
pub fn cfdev(&mut self) -> CFDEV_W<'_>[src]
Bit 18 - Clock Failure Detector Event Interrupt Disable
impl W<u32, Reg<u32, _PMC_FSMR>>[src]
pub fn fstt0(&mut self) -> FSTT0_W<'_>[src]
Bit 0 - Fast Start-up Input Enable 0
pub fn fstt1(&mut self) -> FSTT1_W<'_>[src]
Bit 1 - Fast Start-up Input Enable 1
pub fn fstt2(&mut self) -> FSTT2_W<'_>[src]
Bit 2 - Fast Start-up Input Enable 2
pub fn fstt3(&mut self) -> FSTT3_W<'_>[src]
Bit 3 - Fast Start-up Input Enable 3
pub fn fstt4(&mut self) -> FSTT4_W<'_>[src]
Bit 4 - Fast Start-up Input Enable 4
pub fn fstt5(&mut self) -> FSTT5_W<'_>[src]
Bit 5 - Fast Start-up Input Enable 5
pub fn fstt6(&mut self) -> FSTT6_W<'_>[src]
Bit 6 - Fast Start-up Input Enable 6
pub fn fstt7(&mut self) -> FSTT7_W<'_>[src]
Bit 7 - Fast Start-up Input Enable 7
pub fn fstt8(&mut self) -> FSTT8_W<'_>[src]
Bit 8 - Fast Start-up Input Enable 8
pub fn fstt9(&mut self) -> FSTT9_W<'_>[src]
Bit 9 - Fast Start-up Input Enable 9
pub fn fstt10(&mut self) -> FSTT10_W<'_>[src]
Bit 10 - Fast Start-up Input Enable 10
pub fn fstt11(&mut self) -> FSTT11_W<'_>[src]
Bit 11 - Fast Start-up Input Enable 11
pub fn fstt12(&mut self) -> FSTT12_W<'_>[src]
Bit 12 - Fast Start-up Input Enable 12
pub fn fstt13(&mut self) -> FSTT13_W<'_>[src]
Bit 13 - Fast Start-up Input Enable 13
pub fn fstt14(&mut self) -> FSTT14_W<'_>[src]
Bit 14 - Fast Start-up Input Enable 14
pub fn fstt15(&mut self) -> FSTT15_W<'_>[src]
Bit 15 - Fast Start-up Input Enable 15
pub fn rttal(&mut self) -> RTTAL_W<'_>[src]
Bit 16 - RTT Alarm Enable
pub fn rtcal(&mut self) -> RTCAL_W<'_>[src]
Bit 17 - RTC Alarm Enable
pub fn usbal(&mut self) -> USBAL_W<'_>[src]
Bit 18 - USB Alarm Enable
pub fn lpm(&mut self) -> LPM_W<'_>[src]
Bit 20 - Low-power Mode
pub fn flpm(&mut self) -> FLPM_W<'_>[src]
Bits 21:22 - Flash Low-power Mode
impl W<u32, Reg<u32, _PMC_FSPR>>[src]
pub fn fstp0(&mut self) -> FSTP0_W<'_>[src]
Bit 0 - Fast Start-up Input Polarityx
pub fn fstp1(&mut self) -> FSTP1_W<'_>[src]
Bit 1 - Fast Start-up Input Polarityx
pub fn fstp2(&mut self) -> FSTP2_W<'_>[src]
Bit 2 - Fast Start-up Input Polarityx
pub fn fstp3(&mut self) -> FSTP3_W<'_>[src]
Bit 3 - Fast Start-up Input Polarityx
pub fn fstp4(&mut self) -> FSTP4_W<'_>[src]
Bit 4 - Fast Start-up Input Polarityx
pub fn fstp5(&mut self) -> FSTP5_W<'_>[src]
Bit 5 - Fast Start-up Input Polarityx
pub fn fstp6(&mut self) -> FSTP6_W<'_>[src]
Bit 6 - Fast Start-up Input Polarityx
pub fn fstp7(&mut self) -> FSTP7_W<'_>[src]
Bit 7 - Fast Start-up Input Polarityx
pub fn fstp8(&mut self) -> FSTP8_W<'_>[src]
Bit 8 - Fast Start-up Input Polarityx
pub fn fstp9(&mut self) -> FSTP9_W<'_>[src]
Bit 9 - Fast Start-up Input Polarityx
pub fn fstp10(&mut self) -> FSTP10_W<'_>[src]
Bit 10 - Fast Start-up Input Polarityx
pub fn fstp11(&mut self) -> FSTP11_W<'_>[src]
Bit 11 - Fast Start-up Input Polarityx
pub fn fstp12(&mut self) -> FSTP12_W<'_>[src]
Bit 12 - Fast Start-up Input Polarityx
pub fn fstp13(&mut self) -> FSTP13_W<'_>[src]
Bit 13 - Fast Start-up Input Polarityx
pub fn fstp14(&mut self) -> FSTP14_W<'_>[src]
Bit 14 - Fast Start-up Input Polarityx
pub fn fstp15(&mut self) -> FSTP15_W<'_>[src]
Bit 15 - Fast Start-up Input Polarityx
impl W<u32, Reg<u32, _PMC_FOCR>>[src]
impl W<u32, Reg<u32, _PMC_WPMR>>[src]
pub fn wpen(&mut self) -> WPEN_W<'_>[src]
Bit 0 - Write Protection Enable
pub fn wpkey(&mut self) -> WPKEY_W<'_>[src]
Bits 8:31 - Write Protection Key
impl W<u32, Reg<u32, _PMC_PCER1>>[src]
pub fn pid32(&mut self) -> PID32_W<'_>[src]
Bit 0 - Peripheral Clock 32 Enable
pub fn pid33(&mut self) -> PID33_W<'_>[src]
Bit 1 - Peripheral Clock 33 Enable
pub fn pid34(&mut self) -> PID34_W<'_>[src]
Bit 2 - Peripheral Clock 34 Enable
impl W<u32, Reg<u32, _PMC_PCDR1>>[src]
pub fn pid32(&mut self) -> PID32_W<'_>[src]
Bit 0 - Peripheral Clock 32 Disable
pub fn pid33(&mut self) -> PID33_W<'_>[src]
Bit 1 - Peripheral Clock 33 Disable
pub fn pid34(&mut self) -> PID34_W<'_>[src]
Bit 2 - Peripheral Clock 34 Disable
impl W<u32, Reg<u32, _PMC_OCR>>[src]
pub fn cal4(&mut self) -> CAL4_W<'_>[src]
Bits 0:6 - RC Oscillator Calibration bits for 4 MHz
pub fn sel4(&mut self) -> SEL4_W<'_>[src]
Bit 7 - Selection of RC Oscillator Calibration bits for 4 MHz
pub fn cal8(&mut self) -> CAL8_W<'_>[src]
Bits 8:14 - RC Oscillator Calibration bits for 8 MHz
pub fn sel8(&mut self) -> SEL8_W<'_>[src]
Bit 15 - Selection of RC Oscillator Calibration bits for 8 MHz
pub fn cal12(&mut self) -> CAL12_W<'_>[src]
Bits 16:22 - RC Oscillator Calibration bits for 12 MHz
pub fn sel12(&mut self) -> SEL12_W<'_>[src]
Bit 23 - Selection of RC Oscillator Calibration bits for 12 MHz
impl W<u32, Reg<u32, _CR>>[src]
pub fn rstrx(&mut self) -> RSTRX_W<'_>[src]
Bit 2 - Reset Receiver
pub fn rsttx(&mut self) -> RSTTX_W<'_>[src]
Bit 3 - Reset Transmitter
pub fn rxen(&mut self) -> RXEN_W<'_>[src]
Bit 4 - Receiver Enable
pub fn rxdis(&mut self) -> RXDIS_W<'_>[src]
Bit 5 - Receiver Disable
pub fn txen(&mut self) -> TXEN_W<'_>[src]
Bit 6 - Transmitter Enable
pub fn txdis(&mut self) -> TXDIS_W<'_>[src]
Bit 7 - Transmitter Disable
pub fn rststa(&mut self) -> RSTSTA_W<'_>[src]
Bit 8 - Reset Status Bits
impl W<u32, Reg<u32, _MR>>[src]
pub fn par(&mut self) -> PAR_W<'_>[src]
Bits 9:11 - Parity Type
pub fn chmode(&mut self) -> CHMODE_W<'_>[src]
Bits 14:15 - Channel Mode
impl W<u32, Reg<u32, _IER>>[src]
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 0 - Enable RXRDY Interrupt
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 1 - Enable TXRDY Interrupt
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 3 - Enable End of Receive Transfer Interrupt
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 4 - Enable End of Transmit Interrupt
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 5 - Enable Overrun Error Interrupt
pub fn frame(&mut self) -> FRAME_W<'_>[src]
Bit 6 - Enable Framing Error Interrupt
pub fn pare(&mut self) -> PARE_W<'_>[src]
Bit 7 - Enable Parity Error Interrupt
pub fn txempty(&mut self) -> TXEMPTY_W<'_>[src]
Bit 9 - Enable TXEMPTY Interrupt
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 11 - Enable Buffer Empty Interrupt
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 12 - Enable Buffer Full Interrupt
impl W<u32, Reg<u32, _IDR>>[src]
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 0 - Disable RXRDY Interrupt
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 1 - Disable TXRDY Interrupt
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 3 - Disable End of Receive Transfer Interrupt
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 4 - Disable End of Transmit Interrupt
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 5 - Disable Overrun Error Interrupt
pub fn frame(&mut self) -> FRAME_W<'_>[src]
Bit 6 - Disable Framing Error Interrupt
pub fn pare(&mut self) -> PARE_W<'_>[src]
Bit 7 - Disable Parity Error Interrupt
pub fn txempty(&mut self) -> TXEMPTY_W<'_>[src]
Bit 9 - Disable TXEMPTY Interrupt
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 11 - Disable Buffer Empty Interrupt
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 12 - Disable Buffer Full Interrupt
impl W<u32, Reg<u32, _THR>>[src]
impl W<u32, Reg<u32, _BRGR>>[src]
impl W<u32, Reg<u32, _RPR>>[src]
impl W<u32, Reg<u32, _RCR>>[src]
impl W<u32, Reg<u32, _TPR>>[src]
impl W<u32, Reg<u32, _TCR>>[src]
impl W<u32, Reg<u32, _RNPR>>[src]
impl W<u32, Reg<u32, _RNCR>>[src]
impl W<u32, Reg<u32, _TNPR>>[src]
impl W<u32, Reg<u32, _TNCR>>[src]
impl W<u32, Reg<u32, _PTCR>>[src]
pub fn rxten(&mut self) -> RXTEN_W<'_>[src]
Bit 0 - Receiver Transfer Enable
pub fn rxtdis(&mut self) -> RXTDIS_W<'_>[src]
Bit 1 - Receiver Transfer Disable
pub fn txten(&mut self) -> TXTEN_W<'_>[src]
Bit 8 - Transmitter Transfer Enable
pub fn txtdis(&mut self) -> TXTDIS_W<'_>[src]
Bit 9 - Transmitter Transfer Disable
impl W<u32, Reg<u32, _CR>>[src]
pub fn rstrx(&mut self) -> RSTRX_W<'_>[src]
Bit 2 - Reset Receiver
pub fn rsttx(&mut self) -> RSTTX_W<'_>[src]
Bit 3 - Reset Transmitter
pub fn rxen(&mut self) -> RXEN_W<'_>[src]
Bit 4 - Receiver Enable
pub fn rxdis(&mut self) -> RXDIS_W<'_>[src]
Bit 5 - Receiver Disable
pub fn txen(&mut self) -> TXEN_W<'_>[src]
Bit 6 - Transmitter Enable
pub fn txdis(&mut self) -> TXDIS_W<'_>[src]
Bit 7 - Transmitter Disable
pub fn rststa(&mut self) -> RSTSTA_W<'_>[src]
Bit 8 - Reset Status Bits
impl W<u32, Reg<u32, _MR>>[src]
pub fn par(&mut self) -> PAR_W<'_>[src]
Bits 9:11 - Parity Type
pub fn chmode(&mut self) -> CHMODE_W<'_>[src]
Bits 14:15 - Channel Mode
impl W<u32, Reg<u32, _IER>>[src]
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 0 - Enable RXRDY Interrupt
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 1 - Enable TXRDY Interrupt
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 3 - Enable End of Receive Transfer Interrupt
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 4 - Enable End of Transmit Interrupt
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 5 - Enable Overrun Error Interrupt
pub fn frame(&mut self) -> FRAME_W<'_>[src]
Bit 6 - Enable Framing Error Interrupt
pub fn pare(&mut self) -> PARE_W<'_>[src]
Bit 7 - Enable Parity Error Interrupt
pub fn txempty(&mut self) -> TXEMPTY_W<'_>[src]
Bit 9 - Enable TXEMPTY Interrupt
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 11 - Enable Buffer Empty Interrupt
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 12 - Enable Buffer Full Interrupt
impl W<u32, Reg<u32, _IDR>>[src]
pub fn rxrdy(&mut self) -> RXRDY_W<'_>[src]
Bit 0 - Disable RXRDY Interrupt
pub fn txrdy(&mut self) -> TXRDY_W<'_>[src]
Bit 1 - Disable TXRDY Interrupt
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 3 - Disable End of Receive Transfer Interrupt
pub fn endtx(&mut self) -> ENDTX_W<'_>[src]
Bit 4 - Disable End of Transmit Interrupt
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 5 - Disable Overrun Error Interrupt
pub fn frame(&mut self) -> FRAME_W<'_>[src]
Bit 6 - Disable Framing Error Interrupt
pub fn pare(&mut self) -> PARE_W<'_>[src]
Bit 7 - Disable Parity Error Interrupt
pub fn txempty(&mut self) -> TXEMPTY_W<'_>[src]
Bit 9 - Disable TXEMPTY Interrupt
pub fn txbufe(&mut self) -> TXBUFE_W<'_>[src]
Bit 11 - Disable Buffer Empty Interrupt
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 12 - Disable Buffer Full Interrupt
impl W<u32, Reg<u32, _THR>>[src]
impl W<u32, Reg<u32, _BRGR>>[src]
impl W<u32, Reg<u32, _RPR>>[src]
impl W<u32, Reg<u32, _RCR>>[src]
impl W<u32, Reg<u32, _TPR>>[src]
impl W<u32, Reg<u32, _TCR>>[src]
impl W<u32, Reg<u32, _RNPR>>[src]
impl W<u32, Reg<u32, _RNCR>>[src]
impl W<u32, Reg<u32, _TNPR>>[src]
impl W<u32, Reg<u32, _TNCR>>[src]
impl W<u32, Reg<u32, _PTCR>>[src]
pub fn rxten(&mut self) -> RXTEN_W<'_>[src]
Bit 0 - Receiver Transfer Enable
pub fn rxtdis(&mut self) -> RXTDIS_W<'_>[src]
Bit 1 - Receiver Transfer Disable
pub fn txten(&mut self) -> TXTEN_W<'_>[src]
Bit 8 - Transmitter Transfer Enable
pub fn txtdis(&mut self) -> TXTDIS_W<'_>[src]
Bit 9 - Transmitter Transfer Disable
impl W<u32, Reg<u32, _FMR>>[src]
pub fn frdy(&mut self) -> FRDY_W<'_>[src]
Bit 0 - Ready Interrupt Enable
pub fn fws(&mut self) -> FWS_W<'_>[src]
Bits 8:11 - Flash Wait State
pub fn scod(&mut self) -> SCOD_W<'_>[src]
Bit 16 - Sequential Code Optimization Disable
pub fn fam(&mut self) -> FAM_W<'_>[src]
Bit 24 - Flash Access Mode
pub fn cloe(&mut self) -> CLOE_W<'_>[src]
Bit 26 - Code Loop Optimization Enable
impl W<u32, Reg<u32, _FCR>>[src]
pub fn fcmd(&mut self) -> FCMD_W<'_>[src]
Bits 0:7 - Flash Command
pub fn farg(&mut self) -> FARG_W<'_>[src]
Bits 8:23 - Flash Command Argument
pub fn fkey(&mut self) -> FKEY_W<'_>[src]
Bits 24:31 - Flash Writing Protection Key
impl W<u32, Reg<u32, _FMR>>[src]
pub fn frdy(&mut self) -> FRDY_W<'_>[src]
Bit 0 - Ready Interrupt Enable
pub fn fws(&mut self) -> FWS_W<'_>[src]
Bits 8:11 - Flash Wait State
pub fn scod(&mut self) -> SCOD_W<'_>[src]
Bit 16 - Sequential Code Optimization Disable
pub fn fam(&mut self) -> FAM_W<'_>[src]
Bit 24 - Flash Access Mode
pub fn cloe(&mut self) -> CLOE_W<'_>[src]
Bit 26 - Code Loop Optimization Enable
impl W<u32, Reg<u32, _FCR>>[src]
pub fn fcmd(&mut self) -> FCMD_W<'_>[src]
Bits 0:7 - Flash Command
pub fn farg(&mut self) -> FARG_W<'_>[src]
Bits 8:23 - Flash Command Argument
pub fn fkey(&mut self) -> FKEY_W<'_>[src]
Bits 24:31 - Flash Writing Protection Key
impl W<u32, Reg<u32, _PER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - PIO Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - PIO Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - PIO Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - PIO Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - PIO Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - PIO Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - PIO Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - PIO Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - PIO Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - PIO Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - PIO Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - PIO Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - PIO Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - PIO Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - PIO Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - PIO Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - PIO Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - PIO Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - PIO Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - PIO Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - PIO Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - PIO Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - PIO Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - PIO Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - PIO Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - PIO Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - PIO Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - PIO Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - PIO Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - PIO Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - PIO Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - PIO Enable
impl W<u32, Reg<u32, _PDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - PIO Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - PIO Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - PIO Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - PIO Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - PIO Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - PIO Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - PIO Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - PIO Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - PIO Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - PIO Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - PIO Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - PIO Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - PIO Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - PIO Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - PIO Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - PIO Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - PIO Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - PIO Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - PIO Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - PIO Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - PIO Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - PIO Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - PIO Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - PIO Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - PIO Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - PIO Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - PIO Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - PIO Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - PIO Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - PIO Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - PIO Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - PIO Disable
impl W<u32, Reg<u32, _OER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Output Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Output Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Output Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Output Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Output Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Output Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Output Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Output Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Output Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Output Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Output Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Output Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Output Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Output Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Output Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Output Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Output Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Output Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Output Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Output Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Output Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Output Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Output Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Output Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Output Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Output Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Output Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Output Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Output Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Output Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Output Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Output Enable
impl W<u32, Reg<u32, _ODR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Output Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Output Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Output Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Output Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Output Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Output Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Output Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Output Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Output Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Output Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Output Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Output Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Output Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Output Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Output Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Output Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Output Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Output Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Output Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Output Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Output Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Output Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Output Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Output Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Output Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Output Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Output Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Output Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Output Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Output Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Output Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Output Disable
impl W<u32, Reg<u32, _IFER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Input Filter Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Input Filter Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Input Filter Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Input Filter Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Input Filter Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Input Filter Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Input Filter Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Input Filter Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Input Filter Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Input Filter Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Input Filter Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Input Filter Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Input Filter Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Input Filter Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Input Filter Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Input Filter Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Input Filter Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Input Filter Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Input Filter Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Input Filter Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Input Filter Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Input Filter Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Input Filter Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Input Filter Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Input Filter Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Input Filter Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Input Filter Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Input Filter Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Input Filter Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Input Filter Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Input Filter Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Input Filter Enable
impl W<u32, Reg<u32, _IFDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Input Filter Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Input Filter Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Input Filter Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Input Filter Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Input Filter Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Input Filter Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Input Filter Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Input Filter Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Input Filter Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Input Filter Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Input Filter Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Input Filter Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Input Filter Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Input Filter Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Input Filter Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Input Filter Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Input Filter Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Input Filter Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Input Filter Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Input Filter Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Input Filter Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Input Filter Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Input Filter Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Input Filter Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Input Filter Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Input Filter Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Input Filter Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Input Filter Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Input Filter Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Input Filter Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Input Filter Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Input Filter Disable
impl W<u32, Reg<u32, _SODR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Set Output Data
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Set Output Data
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Set Output Data
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Set Output Data
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Set Output Data
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Set Output Data
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Set Output Data
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Set Output Data
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Set Output Data
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Set Output Data
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Set Output Data
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Set Output Data
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Set Output Data
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Set Output Data
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Set Output Data
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Set Output Data
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Set Output Data
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Set Output Data
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Set Output Data
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Set Output Data
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Set Output Data
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Set Output Data
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Set Output Data
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Set Output Data
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Set Output Data
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Set Output Data
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Set Output Data
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Set Output Data
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Set Output Data
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Set Output Data
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Set Output Data
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Set Output Data
impl W<u32, Reg<u32, _CODR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Clear Output Data
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Clear Output Data
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Clear Output Data
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Clear Output Data
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Clear Output Data
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Clear Output Data
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Clear Output Data
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Clear Output Data
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Clear Output Data
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Clear Output Data
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Clear Output Data
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Clear Output Data
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Clear Output Data
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Clear Output Data
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Clear Output Data
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Clear Output Data
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Clear Output Data
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Clear Output Data
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Clear Output Data
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Clear Output Data
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Clear Output Data
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Clear Output Data
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Clear Output Data
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Clear Output Data
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Clear Output Data
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Clear Output Data
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Clear Output Data
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Clear Output Data
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Clear Output Data
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Clear Output Data
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Clear Output Data
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Clear Output Data
impl W<u32, Reg<u32, _ODSR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Output Data Status
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Output Data Status
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Output Data Status
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Output Data Status
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Output Data Status
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Output Data Status
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Output Data Status
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Output Data Status
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Output Data Status
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Output Data Status
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Output Data Status
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Output Data Status
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Output Data Status
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Output Data Status
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Output Data Status
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Output Data Status
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Output Data Status
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Output Data Status
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Output Data Status
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Output Data Status
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Output Data Status
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Output Data Status
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Output Data Status
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Output Data Status
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Output Data Status
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Output Data Status
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Output Data Status
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Output Data Status
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Output Data Status
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Output Data Status
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Output Data Status
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Output Data Status
impl W<u32, Reg<u32, _IER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Input Change Interrupt Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Input Change Interrupt Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Input Change Interrupt Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Input Change Interrupt Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Input Change Interrupt Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Input Change Interrupt Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Input Change Interrupt Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Input Change Interrupt Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Input Change Interrupt Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Input Change Interrupt Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Input Change Interrupt Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Input Change Interrupt Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Input Change Interrupt Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Input Change Interrupt Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Input Change Interrupt Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Input Change Interrupt Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Input Change Interrupt Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Input Change Interrupt Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Input Change Interrupt Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Input Change Interrupt Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Input Change Interrupt Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Input Change Interrupt Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Input Change Interrupt Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Input Change Interrupt Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Input Change Interrupt Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Input Change Interrupt Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Input Change Interrupt Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Input Change Interrupt Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Input Change Interrupt Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Input Change Interrupt Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Input Change Interrupt Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Input Change Interrupt Enable
impl W<u32, Reg<u32, _IDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Input Change Interrupt Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Input Change Interrupt Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Input Change Interrupt Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Input Change Interrupt Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Input Change Interrupt Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Input Change Interrupt Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Input Change Interrupt Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Input Change Interrupt Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Input Change Interrupt Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Input Change Interrupt Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Input Change Interrupt Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Input Change Interrupt Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Input Change Interrupt Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Input Change Interrupt Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Input Change Interrupt Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Input Change Interrupt Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Input Change Interrupt Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Input Change Interrupt Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Input Change Interrupt Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Input Change Interrupt Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Input Change Interrupt Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Input Change Interrupt Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Input Change Interrupt Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Input Change Interrupt Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Input Change Interrupt Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Input Change Interrupt Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Input Change Interrupt Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Input Change Interrupt Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Input Change Interrupt Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Input Change Interrupt Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Input Change Interrupt Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Input Change Interrupt Disable
impl W<u32, Reg<u32, _MDER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Multi-Drive Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Multi-Drive Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Multi-Drive Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Multi-Drive Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Multi-Drive Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Multi-Drive Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Multi-Drive Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Multi-Drive Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Multi-Drive Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Multi-Drive Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Multi-Drive Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Multi-Drive Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Multi-Drive Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Multi-Drive Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Multi-Drive Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Multi-Drive Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Multi-Drive Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Multi-Drive Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Multi-Drive Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Multi-Drive Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Multi-Drive Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Multi-Drive Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Multi-Drive Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Multi-Drive Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Multi-Drive Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Multi-Drive Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Multi-Drive Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Multi-Drive Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Multi-Drive Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Multi-Drive Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Multi-Drive Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Multi-Drive Enable
impl W<u32, Reg<u32, _MDDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Multi-Drive Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Multi-Drive Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Multi-Drive Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Multi-Drive Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Multi-Drive Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Multi-Drive Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Multi-Drive Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Multi-Drive Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Multi-Drive Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Multi-Drive Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Multi-Drive Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Multi-Drive Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Multi-Drive Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Multi-Drive Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Multi-Drive Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Multi-Drive Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Multi-Drive Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Multi-Drive Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Multi-Drive Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Multi-Drive Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Multi-Drive Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Multi-Drive Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Multi-Drive Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Multi-Drive Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Multi-Drive Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Multi-Drive Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Multi-Drive Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Multi-Drive Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Multi-Drive Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Multi-Drive Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Multi-Drive Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Multi-Drive Disable
impl W<u32, Reg<u32, _PUDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Pull-Up Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Pull-Up Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Pull-Up Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Pull-Up Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Pull-Up Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Pull-Up Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Pull-Up Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Pull-Up Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Pull-Up Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Pull-Up Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Pull-Up Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Pull-Up Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Pull-Up Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Pull-Up Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Pull-Up Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Pull-Up Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Pull-Up Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Pull-Up Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Pull-Up Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Pull-Up Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Pull-Up Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Pull-Up Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Pull-Up Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Pull-Up Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Pull-Up Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Pull-Up Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Pull-Up Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Pull-Up Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Pull-Up Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Pull-Up Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Pull-Up Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Pull-Up Disable
impl W<u32, Reg<u32, _PUER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Pull-Up Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Pull-Up Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Pull-Up Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Pull-Up Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Pull-Up Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Pull-Up Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Pull-Up Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Pull-Up Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Pull-Up Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Pull-Up Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Pull-Up Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Pull-Up Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Pull-Up Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Pull-Up Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Pull-Up Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Pull-Up Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Pull-Up Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Pull-Up Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Pull-Up Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Pull-Up Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Pull-Up Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Pull-Up Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Pull-Up Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Pull-Up Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Pull-Up Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Pull-Up Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Pull-Up Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Pull-Up Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Pull-Up Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Pull-Up Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Pull-Up Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Pull-Up Enable
impl W<u32, Reg<u32, _ABCDSR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Peripheral Select
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Peripheral Select
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Peripheral Select
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Peripheral Select
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Peripheral Select
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Peripheral Select
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Peripheral Select
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Peripheral Select
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Peripheral Select
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Peripheral Select
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Peripheral Select
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Peripheral Select
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Peripheral Select
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Peripheral Select
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Peripheral Select
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Peripheral Select
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Peripheral Select
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Peripheral Select
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Peripheral Select
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Peripheral Select
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Peripheral Select
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Peripheral Select
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Peripheral Select
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Peripheral Select
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Peripheral Select
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Peripheral Select
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Peripheral Select
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Peripheral Select
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Peripheral Select
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Peripheral Select
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Peripheral Select
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Peripheral Select
impl W<u32, Reg<u32, _IFSCDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - PIO Clock Glitch Filtering Select
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - PIO Clock Glitch Filtering Select
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - PIO Clock Glitch Filtering Select
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - PIO Clock Glitch Filtering Select
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - PIO Clock Glitch Filtering Select
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - PIO Clock Glitch Filtering Select
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - PIO Clock Glitch Filtering Select
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - PIO Clock Glitch Filtering Select
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - PIO Clock Glitch Filtering Select
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - PIO Clock Glitch Filtering Select
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - PIO Clock Glitch Filtering Select
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - PIO Clock Glitch Filtering Select
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - PIO Clock Glitch Filtering Select
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - PIO Clock Glitch Filtering Select
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - PIO Clock Glitch Filtering Select
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - PIO Clock Glitch Filtering Select
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - PIO Clock Glitch Filtering Select
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - PIO Clock Glitch Filtering Select
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - PIO Clock Glitch Filtering Select
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - PIO Clock Glitch Filtering Select
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - PIO Clock Glitch Filtering Select
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - PIO Clock Glitch Filtering Select
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - PIO Clock Glitch Filtering Select
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - PIO Clock Glitch Filtering Select
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - PIO Clock Glitch Filtering Select
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - PIO Clock Glitch Filtering Select
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - PIO Clock Glitch Filtering Select
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - PIO Clock Glitch Filtering Select
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - PIO Clock Glitch Filtering Select
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - PIO Clock Glitch Filtering Select
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - PIO Clock Glitch Filtering Select
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - PIO Clock Glitch Filtering Select
impl W<u32, Reg<u32, _IFSCER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Debouncing Filtering Select
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Debouncing Filtering Select
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Debouncing Filtering Select
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Debouncing Filtering Select
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Debouncing Filtering Select
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Debouncing Filtering Select
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Debouncing Filtering Select
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Debouncing Filtering Select
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Debouncing Filtering Select
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Debouncing Filtering Select
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Debouncing Filtering Select
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Debouncing Filtering Select
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Debouncing Filtering Select
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Debouncing Filtering Select
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Debouncing Filtering Select
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Debouncing Filtering Select
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Debouncing Filtering Select
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Debouncing Filtering Select
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Debouncing Filtering Select
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Debouncing Filtering Select
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Debouncing Filtering Select
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Debouncing Filtering Select
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Debouncing Filtering Select
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Debouncing Filtering Select
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Debouncing Filtering Select
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Debouncing Filtering Select
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Debouncing Filtering Select
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Debouncing Filtering Select
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Debouncing Filtering Select
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Debouncing Filtering Select
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Debouncing Filtering Select
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Debouncing Filtering Select
impl W<u32, Reg<u32, _SCDR>>[src]
impl W<u32, Reg<u32, _PPDDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Pull-Down Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Pull-Down Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Pull-Down Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Pull-Down Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Pull-Down Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Pull-Down Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Pull-Down Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Pull-Down Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Pull-Down Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Pull-Down Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Pull-Down Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Pull-Down Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Pull-Down Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Pull-Down Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Pull-Down Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Pull-Down Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Pull-Down Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Pull-Down Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Pull-Down Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Pull-Down Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Pull-Down Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Pull-Down Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Pull-Down Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Pull-Down Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Pull-Down Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Pull-Down Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Pull-Down Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Pull-Down Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Pull-Down Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Pull-Down Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Pull-Down Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Pull-Down Disable
impl W<u32, Reg<u32, _PPDER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Pull-Down Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Pull-Down Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Pull-Down Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Pull-Down Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Pull-Down Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Pull-Down Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Pull-Down Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Pull-Down Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Pull-Down Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Pull-Down Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Pull-Down Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Pull-Down Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Pull-Down Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Pull-Down Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Pull-Down Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Pull-Down Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Pull-Down Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Pull-Down Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Pull-Down Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Pull-Down Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Pull-Down Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Pull-Down Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Pull-Down Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Pull-Down Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Pull-Down Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Pull-Down Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Pull-Down Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Pull-Down Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Pull-Down Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Pull-Down Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Pull-Down Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Pull-Down Enable
impl W<u32, Reg<u32, _OWER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Output Write Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Output Write Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Output Write Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Output Write Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Output Write Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Output Write Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Output Write Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Output Write Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Output Write Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Output Write Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Output Write Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Output Write Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Output Write Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Output Write Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Output Write Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Output Write Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Output Write Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Output Write Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Output Write Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Output Write Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Output Write Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Output Write Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Output Write Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Output Write Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Output Write Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Output Write Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Output Write Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Output Write Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Output Write Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Output Write Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Output Write Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Output Write Enable
impl W<u32, Reg<u32, _OWDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Output Write Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Output Write Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Output Write Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Output Write Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Output Write Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Output Write Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Output Write Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Output Write Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Output Write Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Output Write Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Output Write Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Output Write Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Output Write Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Output Write Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Output Write Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Output Write Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Output Write Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Output Write Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Output Write Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Output Write Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Output Write Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Output Write Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Output Write Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Output Write Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Output Write Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Output Write Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Output Write Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Output Write Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Output Write Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Output Write Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Output Write Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Output Write Disable
impl W<u32, Reg<u32, _AIMER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Additional Interrupt Modes Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Additional Interrupt Modes Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Additional Interrupt Modes Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Additional Interrupt Modes Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Additional Interrupt Modes Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Additional Interrupt Modes Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Additional Interrupt Modes Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Additional Interrupt Modes Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Additional Interrupt Modes Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Additional Interrupt Modes Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Additional Interrupt Modes Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Additional Interrupt Modes Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Additional Interrupt Modes Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Additional Interrupt Modes Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Additional Interrupt Modes Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Additional Interrupt Modes Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Additional Interrupt Modes Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Additional Interrupt Modes Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Additional Interrupt Modes Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Additional Interrupt Modes Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Additional Interrupt Modes Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Additional Interrupt Modes Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Additional Interrupt Modes Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Additional Interrupt Modes Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Additional Interrupt Modes Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Additional Interrupt Modes Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Additional Interrupt Modes Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Additional Interrupt Modes Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Additional Interrupt Modes Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Additional Interrupt Modes Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Additional Interrupt Modes Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Additional Interrupt Modes Enable
impl W<u32, Reg<u32, _AIMDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Additional Interrupt Modes Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Additional Interrupt Modes Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Additional Interrupt Modes Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Additional Interrupt Modes Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Additional Interrupt Modes Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Additional Interrupt Modes Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Additional Interrupt Modes Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Additional Interrupt Modes Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Additional Interrupt Modes Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Additional Interrupt Modes Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Additional Interrupt Modes Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Additional Interrupt Modes Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Additional Interrupt Modes Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Additional Interrupt Modes Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Additional Interrupt Modes Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Additional Interrupt Modes Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Additional Interrupt Modes Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Additional Interrupt Modes Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Additional Interrupt Modes Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Additional Interrupt Modes Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Additional Interrupt Modes Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Additional Interrupt Modes Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Additional Interrupt Modes Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Additional Interrupt Modes Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Additional Interrupt Modes Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Additional Interrupt Modes Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Additional Interrupt Modes Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Additional Interrupt Modes Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Additional Interrupt Modes Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Additional Interrupt Modes Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Additional Interrupt Modes Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Additional Interrupt Modes Disable
impl W<u32, Reg<u32, _ESR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Edge Interrupt Selection
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Edge Interrupt Selection
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Edge Interrupt Selection
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Edge Interrupt Selection
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Edge Interrupt Selection
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Edge Interrupt Selection
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Edge Interrupt Selection
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Edge Interrupt Selection
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Edge Interrupt Selection
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Edge Interrupt Selection
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Edge Interrupt Selection
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Edge Interrupt Selection
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Edge Interrupt Selection
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Edge Interrupt Selection
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Edge Interrupt Selection
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Edge Interrupt Selection
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Edge Interrupt Selection
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Edge Interrupt Selection
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Edge Interrupt Selection
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Edge Interrupt Selection
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Edge Interrupt Selection
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Edge Interrupt Selection
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Edge Interrupt Selection
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Edge Interrupt Selection
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Edge Interrupt Selection
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Edge Interrupt Selection
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Edge Interrupt Selection
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Edge Interrupt Selection
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Edge Interrupt Selection
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Edge Interrupt Selection
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Edge Interrupt Selection
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Edge Interrupt Selection
impl W<u32, Reg<u32, _LSR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Level Interrupt Selection
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Level Interrupt Selection
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Level Interrupt Selection
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Level Interrupt Selection
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Level Interrupt Selection
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Level Interrupt Selection
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Level Interrupt Selection
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Level Interrupt Selection
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Level Interrupt Selection
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Level Interrupt Selection
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Level Interrupt Selection
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Level Interrupt Selection
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Level Interrupt Selection
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Level Interrupt Selection
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Level Interrupt Selection
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Level Interrupt Selection
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Level Interrupt Selection
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Level Interrupt Selection
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Level Interrupt Selection
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Level Interrupt Selection
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Level Interrupt Selection
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Level Interrupt Selection
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Level Interrupt Selection
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Level Interrupt Selection
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Level Interrupt Selection
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Level Interrupt Selection
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Level Interrupt Selection
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Level Interrupt Selection
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Level Interrupt Selection
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Level Interrupt Selection
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Level Interrupt Selection
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Level Interrupt Selection
impl W<u32, Reg<u32, _FELLSR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Falling Edge/Low-Level Interrupt Selection
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Falling Edge/Low-Level Interrupt Selection
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Falling Edge/Low-Level Interrupt Selection
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Falling Edge/Low-Level Interrupt Selection
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Falling Edge/Low-Level Interrupt Selection
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Falling Edge/Low-Level Interrupt Selection
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Falling Edge/Low-Level Interrupt Selection
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Falling Edge/Low-Level Interrupt Selection
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Falling Edge/Low-Level Interrupt Selection
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Falling Edge/Low-Level Interrupt Selection
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Falling Edge/Low-Level Interrupt Selection
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Falling Edge/Low-Level Interrupt Selection
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Falling Edge/Low-Level Interrupt Selection
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Falling Edge/Low-Level Interrupt Selection
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Falling Edge/Low-Level Interrupt Selection
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Falling Edge/Low-Level Interrupt Selection
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Falling Edge/Low-Level Interrupt Selection
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Falling Edge/Low-Level Interrupt Selection
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Falling Edge/Low-Level Interrupt Selection
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Falling Edge/Low-Level Interrupt Selection
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Falling Edge/Low-Level Interrupt Selection
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Falling Edge/Low-Level Interrupt Selection
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Falling Edge/Low-Level Interrupt Selection
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Falling Edge/Low-Level Interrupt Selection
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Falling Edge/Low-Level Interrupt Selection
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Falling Edge/Low-Level Interrupt Selection
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Falling Edge/Low-Level Interrupt Selection
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Falling Edge/Low-Level Interrupt Selection
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Falling Edge/Low-Level Interrupt Selection
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Falling Edge/Low-Level Interrupt Selection
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Falling Edge/Low-Level Interrupt Selection
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Falling Edge/Low-Level Interrupt Selection
impl W<u32, Reg<u32, _REHLSR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Rising Edge /High-Level Interrupt Selection
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Rising Edge /High-Level Interrupt Selection
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Rising Edge /High-Level Interrupt Selection
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Rising Edge /High-Level Interrupt Selection
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Rising Edge /High-Level Interrupt Selection
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Rising Edge /High-Level Interrupt Selection
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Rising Edge /High-Level Interrupt Selection
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Rising Edge /High-Level Interrupt Selection
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Rising Edge /High-Level Interrupt Selection
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Rising Edge /High-Level Interrupt Selection
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Rising Edge /High-Level Interrupt Selection
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Rising Edge /High-Level Interrupt Selection
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Rising Edge /High-Level Interrupt Selection
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Rising Edge /High-Level Interrupt Selection
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Rising Edge /High-Level Interrupt Selection
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Rising Edge /High-Level Interrupt Selection
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Rising Edge /High-Level Interrupt Selection
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Rising Edge /High-Level Interrupt Selection
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Rising Edge /High-Level Interrupt Selection
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Rising Edge /High-Level Interrupt Selection
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Rising Edge /High-Level Interrupt Selection
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Rising Edge /High-Level Interrupt Selection
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Rising Edge /High-Level Interrupt Selection
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Rising Edge /High-Level Interrupt Selection
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Rising Edge /High-Level Interrupt Selection
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Rising Edge /High-Level Interrupt Selection
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Rising Edge /High-Level Interrupt Selection
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Rising Edge /High-Level Interrupt Selection
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Rising Edge /High-Level Interrupt Selection
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Rising Edge /High-Level Interrupt Selection
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Rising Edge /High-Level Interrupt Selection
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Rising Edge /High-Level Interrupt Selection
impl W<u32, Reg<u32, _WPMR>>[src]
pub fn wpen(&mut self) -> WPEN_W<'_>[src]
Bit 0 - Write Protection Enable
pub fn wpkey(&mut self) -> WPKEY_W<'_>[src]
Bits 8:31 - Write Protection Key.
impl W<u32, Reg<u32, _SCHMITT>>[src]
pub fn schmitt0(&mut self) -> SCHMITT0_W<'_>[src]
Bit 0 - Schmitt Trigger Control
pub fn schmitt1(&mut self) -> SCHMITT1_W<'_>[src]
Bit 1 - Schmitt Trigger Control
pub fn schmitt2(&mut self) -> SCHMITT2_W<'_>[src]
Bit 2 - Schmitt Trigger Control
pub fn schmitt3(&mut self) -> SCHMITT3_W<'_>[src]
Bit 3 - Schmitt Trigger Control
pub fn schmitt4(&mut self) -> SCHMITT4_W<'_>[src]
Bit 4 - Schmitt Trigger Control
pub fn schmitt5(&mut self) -> SCHMITT5_W<'_>[src]
Bit 5 - Schmitt Trigger Control
pub fn schmitt6(&mut self) -> SCHMITT6_W<'_>[src]
Bit 6 - Schmitt Trigger Control
pub fn schmitt7(&mut self) -> SCHMITT7_W<'_>[src]
Bit 7 - Schmitt Trigger Control
pub fn schmitt8(&mut self) -> SCHMITT8_W<'_>[src]
Bit 8 - Schmitt Trigger Control
pub fn schmitt9(&mut self) -> SCHMITT9_W<'_>[src]
Bit 9 - Schmitt Trigger Control
pub fn schmitt10(&mut self) -> SCHMITT10_W<'_>[src]
Bit 10 - Schmitt Trigger Control
pub fn schmitt11(&mut self) -> SCHMITT11_W<'_>[src]
Bit 11 - Schmitt Trigger Control
pub fn schmitt12(&mut self) -> SCHMITT12_W<'_>[src]
Bit 12 - Schmitt Trigger Control
pub fn schmitt13(&mut self) -> SCHMITT13_W<'_>[src]
Bit 13 - Schmitt Trigger Control
pub fn schmitt14(&mut self) -> SCHMITT14_W<'_>[src]
Bit 14 - Schmitt Trigger Control
pub fn schmitt15(&mut self) -> SCHMITT15_W<'_>[src]
Bit 15 - Schmitt Trigger Control
pub fn schmitt16(&mut self) -> SCHMITT16_W<'_>[src]
Bit 16 - Schmitt Trigger Control
pub fn schmitt17(&mut self) -> SCHMITT17_W<'_>[src]
Bit 17 - Schmitt Trigger Control
pub fn schmitt18(&mut self) -> SCHMITT18_W<'_>[src]
Bit 18 - Schmitt Trigger Control
pub fn schmitt19(&mut self) -> SCHMITT19_W<'_>[src]
Bit 19 - Schmitt Trigger Control
pub fn schmitt20(&mut self) -> SCHMITT20_W<'_>[src]
Bit 20 - Schmitt Trigger Control
pub fn schmitt21(&mut self) -> SCHMITT21_W<'_>[src]
Bit 21 - Schmitt Trigger Control
pub fn schmitt22(&mut self) -> SCHMITT22_W<'_>[src]
Bit 22 - Schmitt Trigger Control
pub fn schmitt23(&mut self) -> SCHMITT23_W<'_>[src]
Bit 23 - Schmitt Trigger Control
pub fn schmitt24(&mut self) -> SCHMITT24_W<'_>[src]
Bit 24 - Schmitt Trigger Control
pub fn schmitt25(&mut self) -> SCHMITT25_W<'_>[src]
Bit 25 - Schmitt Trigger Control
pub fn schmitt26(&mut self) -> SCHMITT26_W<'_>[src]
Bit 26 - Schmitt Trigger Control
pub fn schmitt27(&mut self) -> SCHMITT27_W<'_>[src]
Bit 27 - Schmitt Trigger Control
pub fn schmitt28(&mut self) -> SCHMITT28_W<'_>[src]
Bit 28 - Schmitt Trigger Control
pub fn schmitt29(&mut self) -> SCHMITT29_W<'_>[src]
Bit 29 - Schmitt Trigger Control
pub fn schmitt30(&mut self) -> SCHMITT30_W<'_>[src]
Bit 30 - Schmitt Trigger Control
pub fn schmitt31(&mut self) -> SCHMITT31_W<'_>[src]
Bit 31 - Schmitt Trigger Control
impl W<u32, Reg<u32, _PCMR>>[src]
pub fn pcen(&mut self) -> PCEN_W<'_>[src]
Bit 0 - Parallel Capture Mode Enable
pub fn dsize(&mut self) -> DSIZE_W<'_>[src]
Bits 4:5 - Parallel Capture Mode Data Size
pub fn alwys(&mut self) -> ALWYS_W<'_>[src]
Bit 9 - Parallel Capture Mode Always Sampling
pub fn halfs(&mut self) -> HALFS_W<'_>[src]
Bit 10 - Parallel Capture Mode Half Sampling
pub fn frsts(&mut self) -> FRSTS_W<'_>[src]
Bit 11 - Parallel Capture Mode First Sample
impl W<u32, Reg<u32, _PCIER>>[src]
pub fn drdy(&mut self) -> DRDY_W<'_>[src]
Bit 0 - Parallel Capture Mode Data Ready Interrupt Enable
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 1 - Parallel Capture Mode Overrun Error Interrupt Enable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 2 - End of Reception Transfer Interrupt Enable
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 3 - Reception Buffer Full Interrupt Enable
impl W<u32, Reg<u32, _PCIDR>>[src]
pub fn drdy(&mut self) -> DRDY_W<'_>[src]
Bit 0 - Parallel Capture Mode Data Ready Interrupt Disable
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 1 - Parallel Capture Mode Overrun Error Interrupt Disable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 2 - End of Reception Transfer Interrupt Disable
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 3 - Reception Buffer Full Interrupt Disable
impl W<u32, Reg<u32, _RPR>>[src]
impl W<u32, Reg<u32, _RCR>>[src]
impl W<u32, Reg<u32, _RNPR>>[src]
impl W<u32, Reg<u32, _RNCR>>[src]
impl W<u32, Reg<u32, _PTCR>>[src]
pub fn rxten(&mut self) -> RXTEN_W<'_>[src]
Bit 0 - Receiver Transfer Enable
pub fn rxtdis(&mut self) -> RXTDIS_W<'_>[src]
Bit 1 - Receiver Transfer Disable
pub fn txten(&mut self) -> TXTEN_W<'_>[src]
Bit 8 - Transmitter Transfer Enable
pub fn txtdis(&mut self) -> TXTDIS_W<'_>[src]
Bit 9 - Transmitter Transfer Disable
impl W<u32, Reg<u32, _PER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - PIO Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - PIO Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - PIO Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - PIO Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - PIO Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - PIO Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - PIO Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - PIO Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - PIO Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - PIO Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - PIO Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - PIO Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - PIO Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - PIO Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - PIO Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - PIO Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - PIO Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - PIO Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - PIO Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - PIO Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - PIO Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - PIO Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - PIO Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - PIO Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - PIO Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - PIO Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - PIO Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - PIO Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - PIO Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - PIO Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - PIO Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - PIO Enable
impl W<u32, Reg<u32, _PDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - PIO Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - PIO Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - PIO Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - PIO Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - PIO Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - PIO Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - PIO Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - PIO Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - PIO Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - PIO Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - PIO Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - PIO Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - PIO Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - PIO Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - PIO Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - PIO Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - PIO Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - PIO Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - PIO Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - PIO Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - PIO Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - PIO Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - PIO Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - PIO Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - PIO Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - PIO Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - PIO Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - PIO Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - PIO Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - PIO Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - PIO Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - PIO Disable
impl W<u32, Reg<u32, _OER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Output Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Output Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Output Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Output Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Output Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Output Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Output Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Output Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Output Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Output Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Output Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Output Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Output Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Output Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Output Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Output Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Output Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Output Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Output Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Output Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Output Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Output Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Output Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Output Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Output Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Output Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Output Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Output Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Output Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Output Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Output Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Output Enable
impl W<u32, Reg<u32, _ODR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Output Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Output Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Output Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Output Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Output Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Output Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Output Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Output Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Output Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Output Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Output Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Output Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Output Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Output Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Output Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Output Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Output Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Output Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Output Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Output Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Output Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Output Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Output Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Output Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Output Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Output Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Output Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Output Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Output Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Output Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Output Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Output Disable
impl W<u32, Reg<u32, _IFER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Input Filter Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Input Filter Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Input Filter Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Input Filter Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Input Filter Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Input Filter Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Input Filter Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Input Filter Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Input Filter Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Input Filter Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Input Filter Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Input Filter Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Input Filter Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Input Filter Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Input Filter Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Input Filter Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Input Filter Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Input Filter Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Input Filter Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Input Filter Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Input Filter Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Input Filter Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Input Filter Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Input Filter Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Input Filter Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Input Filter Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Input Filter Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Input Filter Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Input Filter Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Input Filter Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Input Filter Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Input Filter Enable
impl W<u32, Reg<u32, _IFDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Input Filter Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Input Filter Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Input Filter Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Input Filter Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Input Filter Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Input Filter Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Input Filter Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Input Filter Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Input Filter Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Input Filter Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Input Filter Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Input Filter Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Input Filter Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Input Filter Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Input Filter Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Input Filter Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Input Filter Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Input Filter Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Input Filter Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Input Filter Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Input Filter Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Input Filter Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Input Filter Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Input Filter Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Input Filter Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Input Filter Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Input Filter Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Input Filter Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Input Filter Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Input Filter Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Input Filter Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Input Filter Disable
impl W<u32, Reg<u32, _SODR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Set Output Data
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Set Output Data
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Set Output Data
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Set Output Data
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Set Output Data
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Set Output Data
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Set Output Data
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Set Output Data
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Set Output Data
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Set Output Data
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Set Output Data
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Set Output Data
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Set Output Data
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Set Output Data
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Set Output Data
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Set Output Data
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Set Output Data
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Set Output Data
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Set Output Data
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Set Output Data
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Set Output Data
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Set Output Data
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Set Output Data
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Set Output Data
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Set Output Data
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Set Output Data
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Set Output Data
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Set Output Data
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Set Output Data
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Set Output Data
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Set Output Data
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Set Output Data
impl W<u32, Reg<u32, _CODR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Clear Output Data
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Clear Output Data
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Clear Output Data
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Clear Output Data
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Clear Output Data
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Clear Output Data
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Clear Output Data
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Clear Output Data
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Clear Output Data
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Clear Output Data
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Clear Output Data
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Clear Output Data
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Clear Output Data
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Clear Output Data
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Clear Output Data
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Clear Output Data
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Clear Output Data
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Clear Output Data
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Clear Output Data
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Clear Output Data
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Clear Output Data
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Clear Output Data
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Clear Output Data
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Clear Output Data
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Clear Output Data
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Clear Output Data
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Clear Output Data
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Clear Output Data
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Clear Output Data
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Clear Output Data
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Clear Output Data
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Clear Output Data
impl W<u32, Reg<u32, _ODSR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Output Data Status
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Output Data Status
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Output Data Status
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Output Data Status
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Output Data Status
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Output Data Status
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Output Data Status
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Output Data Status
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Output Data Status
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Output Data Status
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Output Data Status
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Output Data Status
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Output Data Status
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Output Data Status
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Output Data Status
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Output Data Status
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Output Data Status
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Output Data Status
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Output Data Status
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Output Data Status
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Output Data Status
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Output Data Status
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Output Data Status
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Output Data Status
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Output Data Status
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Output Data Status
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Output Data Status
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Output Data Status
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Output Data Status
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Output Data Status
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Output Data Status
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Output Data Status
impl W<u32, Reg<u32, _IER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Input Change Interrupt Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Input Change Interrupt Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Input Change Interrupt Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Input Change Interrupt Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Input Change Interrupt Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Input Change Interrupt Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Input Change Interrupt Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Input Change Interrupt Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Input Change Interrupt Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Input Change Interrupt Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Input Change Interrupt Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Input Change Interrupt Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Input Change Interrupt Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Input Change Interrupt Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Input Change Interrupt Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Input Change Interrupt Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Input Change Interrupt Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Input Change Interrupt Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Input Change Interrupt Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Input Change Interrupt Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Input Change Interrupt Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Input Change Interrupt Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Input Change Interrupt Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Input Change Interrupt Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Input Change Interrupt Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Input Change Interrupt Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Input Change Interrupt Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Input Change Interrupt Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Input Change Interrupt Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Input Change Interrupt Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Input Change Interrupt Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Input Change Interrupt Enable
impl W<u32, Reg<u32, _IDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Input Change Interrupt Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Input Change Interrupt Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Input Change Interrupt Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Input Change Interrupt Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Input Change Interrupt Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Input Change Interrupt Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Input Change Interrupt Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Input Change Interrupt Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Input Change Interrupt Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Input Change Interrupt Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Input Change Interrupt Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Input Change Interrupt Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Input Change Interrupt Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Input Change Interrupt Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Input Change Interrupt Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Input Change Interrupt Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Input Change Interrupt Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Input Change Interrupt Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Input Change Interrupt Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Input Change Interrupt Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Input Change Interrupt Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Input Change Interrupt Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Input Change Interrupt Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Input Change Interrupt Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Input Change Interrupt Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Input Change Interrupt Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Input Change Interrupt Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Input Change Interrupt Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Input Change Interrupt Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Input Change Interrupt Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Input Change Interrupt Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Input Change Interrupt Disable
impl W<u32, Reg<u32, _MDER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Multi-Drive Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Multi-Drive Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Multi-Drive Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Multi-Drive Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Multi-Drive Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Multi-Drive Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Multi-Drive Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Multi-Drive Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Multi-Drive Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Multi-Drive Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Multi-Drive Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Multi-Drive Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Multi-Drive Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Multi-Drive Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Multi-Drive Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Multi-Drive Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Multi-Drive Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Multi-Drive Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Multi-Drive Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Multi-Drive Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Multi-Drive Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Multi-Drive Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Multi-Drive Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Multi-Drive Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Multi-Drive Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Multi-Drive Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Multi-Drive Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Multi-Drive Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Multi-Drive Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Multi-Drive Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Multi-Drive Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Multi-Drive Enable
impl W<u32, Reg<u32, _MDDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Multi-Drive Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Multi-Drive Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Multi-Drive Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Multi-Drive Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Multi-Drive Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Multi-Drive Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Multi-Drive Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Multi-Drive Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Multi-Drive Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Multi-Drive Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Multi-Drive Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Multi-Drive Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Multi-Drive Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Multi-Drive Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Multi-Drive Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Multi-Drive Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Multi-Drive Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Multi-Drive Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Multi-Drive Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Multi-Drive Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Multi-Drive Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Multi-Drive Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Multi-Drive Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Multi-Drive Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Multi-Drive Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Multi-Drive Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Multi-Drive Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Multi-Drive Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Multi-Drive Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Multi-Drive Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Multi-Drive Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Multi-Drive Disable
impl W<u32, Reg<u32, _PUDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Pull-Up Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Pull-Up Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Pull-Up Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Pull-Up Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Pull-Up Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Pull-Up Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Pull-Up Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Pull-Up Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Pull-Up Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Pull-Up Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Pull-Up Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Pull-Up Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Pull-Up Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Pull-Up Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Pull-Up Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Pull-Up Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Pull-Up Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Pull-Up Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Pull-Up Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Pull-Up Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Pull-Up Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Pull-Up Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Pull-Up Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Pull-Up Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Pull-Up Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Pull-Up Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Pull-Up Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Pull-Up Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Pull-Up Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Pull-Up Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Pull-Up Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Pull-Up Disable
impl W<u32, Reg<u32, _PUER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Pull-Up Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Pull-Up Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Pull-Up Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Pull-Up Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Pull-Up Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Pull-Up Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Pull-Up Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Pull-Up Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Pull-Up Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Pull-Up Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Pull-Up Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Pull-Up Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Pull-Up Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Pull-Up Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Pull-Up Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Pull-Up Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Pull-Up Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Pull-Up Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Pull-Up Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Pull-Up Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Pull-Up Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Pull-Up Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Pull-Up Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Pull-Up Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Pull-Up Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Pull-Up Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Pull-Up Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Pull-Up Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Pull-Up Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Pull-Up Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Pull-Up Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Pull-Up Enable
impl W<u32, Reg<u32, _ABCDSR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Peripheral Select
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Peripheral Select
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Peripheral Select
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Peripheral Select
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Peripheral Select
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Peripheral Select
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Peripheral Select
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Peripheral Select
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Peripheral Select
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Peripheral Select
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Peripheral Select
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Peripheral Select
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Peripheral Select
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Peripheral Select
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Peripheral Select
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Peripheral Select
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Peripheral Select
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Peripheral Select
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Peripheral Select
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Peripheral Select
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Peripheral Select
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Peripheral Select
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Peripheral Select
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Peripheral Select
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Peripheral Select
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Peripheral Select
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Peripheral Select
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Peripheral Select
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Peripheral Select
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Peripheral Select
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Peripheral Select
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Peripheral Select
impl W<u32, Reg<u32, _IFSCDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - PIO Clock Glitch Filtering Select
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - PIO Clock Glitch Filtering Select
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - PIO Clock Glitch Filtering Select
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - PIO Clock Glitch Filtering Select
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - PIO Clock Glitch Filtering Select
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - PIO Clock Glitch Filtering Select
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - PIO Clock Glitch Filtering Select
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - PIO Clock Glitch Filtering Select
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - PIO Clock Glitch Filtering Select
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - PIO Clock Glitch Filtering Select
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - PIO Clock Glitch Filtering Select
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - PIO Clock Glitch Filtering Select
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - PIO Clock Glitch Filtering Select
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - PIO Clock Glitch Filtering Select
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - PIO Clock Glitch Filtering Select
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - PIO Clock Glitch Filtering Select
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - PIO Clock Glitch Filtering Select
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - PIO Clock Glitch Filtering Select
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - PIO Clock Glitch Filtering Select
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - PIO Clock Glitch Filtering Select
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - PIO Clock Glitch Filtering Select
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - PIO Clock Glitch Filtering Select
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - PIO Clock Glitch Filtering Select
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - PIO Clock Glitch Filtering Select
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - PIO Clock Glitch Filtering Select
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - PIO Clock Glitch Filtering Select
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - PIO Clock Glitch Filtering Select
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - PIO Clock Glitch Filtering Select
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - PIO Clock Glitch Filtering Select
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - PIO Clock Glitch Filtering Select
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - PIO Clock Glitch Filtering Select
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - PIO Clock Glitch Filtering Select
impl W<u32, Reg<u32, _IFSCER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Debouncing Filtering Select
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Debouncing Filtering Select
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Debouncing Filtering Select
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Debouncing Filtering Select
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Debouncing Filtering Select
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Debouncing Filtering Select
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Debouncing Filtering Select
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Debouncing Filtering Select
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Debouncing Filtering Select
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Debouncing Filtering Select
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Debouncing Filtering Select
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Debouncing Filtering Select
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Debouncing Filtering Select
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Debouncing Filtering Select
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Debouncing Filtering Select
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Debouncing Filtering Select
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Debouncing Filtering Select
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Debouncing Filtering Select
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Debouncing Filtering Select
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Debouncing Filtering Select
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Debouncing Filtering Select
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Debouncing Filtering Select
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Debouncing Filtering Select
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Debouncing Filtering Select
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Debouncing Filtering Select
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Debouncing Filtering Select
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Debouncing Filtering Select
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Debouncing Filtering Select
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Debouncing Filtering Select
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Debouncing Filtering Select
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Debouncing Filtering Select
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Debouncing Filtering Select
impl W<u32, Reg<u32, _SCDR>>[src]
impl W<u32, Reg<u32, _PPDDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Pull-Down Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Pull-Down Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Pull-Down Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Pull-Down Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Pull-Down Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Pull-Down Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Pull-Down Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Pull-Down Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Pull-Down Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Pull-Down Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Pull-Down Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Pull-Down Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Pull-Down Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Pull-Down Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Pull-Down Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Pull-Down Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Pull-Down Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Pull-Down Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Pull-Down Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Pull-Down Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Pull-Down Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Pull-Down Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Pull-Down Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Pull-Down Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Pull-Down Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Pull-Down Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Pull-Down Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Pull-Down Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Pull-Down Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Pull-Down Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Pull-Down Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Pull-Down Disable
impl W<u32, Reg<u32, _PPDER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Pull-Down Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Pull-Down Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Pull-Down Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Pull-Down Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Pull-Down Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Pull-Down Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Pull-Down Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Pull-Down Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Pull-Down Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Pull-Down Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Pull-Down Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Pull-Down Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Pull-Down Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Pull-Down Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Pull-Down Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Pull-Down Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Pull-Down Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Pull-Down Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Pull-Down Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Pull-Down Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Pull-Down Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Pull-Down Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Pull-Down Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Pull-Down Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Pull-Down Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Pull-Down Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Pull-Down Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Pull-Down Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Pull-Down Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Pull-Down Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Pull-Down Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Pull-Down Enable
impl W<u32, Reg<u32, _OWER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Output Write Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Output Write Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Output Write Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Output Write Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Output Write Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Output Write Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Output Write Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Output Write Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Output Write Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Output Write Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Output Write Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Output Write Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Output Write Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Output Write Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Output Write Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Output Write Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Output Write Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Output Write Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Output Write Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Output Write Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Output Write Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Output Write Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Output Write Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Output Write Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Output Write Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Output Write Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Output Write Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Output Write Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Output Write Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Output Write Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Output Write Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Output Write Enable
impl W<u32, Reg<u32, _OWDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Output Write Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Output Write Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Output Write Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Output Write Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Output Write Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Output Write Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Output Write Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Output Write Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Output Write Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Output Write Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Output Write Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Output Write Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Output Write Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Output Write Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Output Write Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Output Write Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Output Write Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Output Write Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Output Write Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Output Write Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Output Write Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Output Write Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Output Write Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Output Write Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Output Write Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Output Write Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Output Write Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Output Write Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Output Write Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Output Write Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Output Write Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Output Write Disable
impl W<u32, Reg<u32, _AIMER>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Additional Interrupt Modes Enable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Additional Interrupt Modes Enable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Additional Interrupt Modes Enable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Additional Interrupt Modes Enable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Additional Interrupt Modes Enable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Additional Interrupt Modes Enable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Additional Interrupt Modes Enable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Additional Interrupt Modes Enable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Additional Interrupt Modes Enable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Additional Interrupt Modes Enable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Additional Interrupt Modes Enable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Additional Interrupt Modes Enable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Additional Interrupt Modes Enable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Additional Interrupt Modes Enable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Additional Interrupt Modes Enable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Additional Interrupt Modes Enable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Additional Interrupt Modes Enable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Additional Interrupt Modes Enable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Additional Interrupt Modes Enable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Additional Interrupt Modes Enable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Additional Interrupt Modes Enable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Additional Interrupt Modes Enable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Additional Interrupt Modes Enable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Additional Interrupt Modes Enable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Additional Interrupt Modes Enable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Additional Interrupt Modes Enable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Additional Interrupt Modes Enable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Additional Interrupt Modes Enable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Additional Interrupt Modes Enable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Additional Interrupt Modes Enable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Additional Interrupt Modes Enable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Additional Interrupt Modes Enable
impl W<u32, Reg<u32, _AIMDR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Additional Interrupt Modes Disable
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Additional Interrupt Modes Disable
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Additional Interrupt Modes Disable
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Additional Interrupt Modes Disable
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Additional Interrupt Modes Disable
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Additional Interrupt Modes Disable
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Additional Interrupt Modes Disable
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Additional Interrupt Modes Disable
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Additional Interrupt Modes Disable
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Additional Interrupt Modes Disable
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Additional Interrupt Modes Disable
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Additional Interrupt Modes Disable
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Additional Interrupt Modes Disable
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Additional Interrupt Modes Disable
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Additional Interrupt Modes Disable
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Additional Interrupt Modes Disable
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Additional Interrupt Modes Disable
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Additional Interrupt Modes Disable
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Additional Interrupt Modes Disable
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Additional Interrupt Modes Disable
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Additional Interrupt Modes Disable
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Additional Interrupt Modes Disable
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Additional Interrupt Modes Disable
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Additional Interrupt Modes Disable
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Additional Interrupt Modes Disable
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Additional Interrupt Modes Disable
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Additional Interrupt Modes Disable
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Additional Interrupt Modes Disable
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Additional Interrupt Modes Disable
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Additional Interrupt Modes Disable
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Additional Interrupt Modes Disable
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Additional Interrupt Modes Disable
impl W<u32, Reg<u32, _ESR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Edge Interrupt Selection
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Edge Interrupt Selection
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Edge Interrupt Selection
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Edge Interrupt Selection
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Edge Interrupt Selection
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Edge Interrupt Selection
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Edge Interrupt Selection
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Edge Interrupt Selection
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Edge Interrupt Selection
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Edge Interrupt Selection
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Edge Interrupt Selection
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Edge Interrupt Selection
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Edge Interrupt Selection
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Edge Interrupt Selection
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Edge Interrupt Selection
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Edge Interrupt Selection
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Edge Interrupt Selection
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Edge Interrupt Selection
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Edge Interrupt Selection
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Edge Interrupt Selection
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Edge Interrupt Selection
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Edge Interrupt Selection
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Edge Interrupt Selection
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Edge Interrupt Selection
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Edge Interrupt Selection
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Edge Interrupt Selection
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Edge Interrupt Selection
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Edge Interrupt Selection
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Edge Interrupt Selection
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Edge Interrupt Selection
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Edge Interrupt Selection
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Edge Interrupt Selection
impl W<u32, Reg<u32, _LSR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Level Interrupt Selection
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Level Interrupt Selection
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Level Interrupt Selection
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Level Interrupt Selection
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Level Interrupt Selection
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Level Interrupt Selection
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Level Interrupt Selection
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Level Interrupt Selection
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Level Interrupt Selection
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Level Interrupt Selection
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Level Interrupt Selection
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Level Interrupt Selection
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Level Interrupt Selection
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Level Interrupt Selection
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Level Interrupt Selection
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Level Interrupt Selection
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Level Interrupt Selection
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Level Interrupt Selection
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Level Interrupt Selection
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Level Interrupt Selection
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Level Interrupt Selection
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Level Interrupt Selection
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Level Interrupt Selection
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Level Interrupt Selection
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Level Interrupt Selection
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Level Interrupt Selection
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Level Interrupt Selection
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Level Interrupt Selection
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Level Interrupt Selection
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Level Interrupt Selection
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Level Interrupt Selection
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Level Interrupt Selection
impl W<u32, Reg<u32, _FELLSR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Falling Edge/Low-Level Interrupt Selection
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Falling Edge/Low-Level Interrupt Selection
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Falling Edge/Low-Level Interrupt Selection
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Falling Edge/Low-Level Interrupt Selection
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Falling Edge/Low-Level Interrupt Selection
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Falling Edge/Low-Level Interrupt Selection
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Falling Edge/Low-Level Interrupt Selection
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Falling Edge/Low-Level Interrupt Selection
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Falling Edge/Low-Level Interrupt Selection
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Falling Edge/Low-Level Interrupt Selection
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Falling Edge/Low-Level Interrupt Selection
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Falling Edge/Low-Level Interrupt Selection
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Falling Edge/Low-Level Interrupt Selection
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Falling Edge/Low-Level Interrupt Selection
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Falling Edge/Low-Level Interrupt Selection
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Falling Edge/Low-Level Interrupt Selection
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Falling Edge/Low-Level Interrupt Selection
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Falling Edge/Low-Level Interrupt Selection
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Falling Edge/Low-Level Interrupt Selection
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Falling Edge/Low-Level Interrupt Selection
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Falling Edge/Low-Level Interrupt Selection
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Falling Edge/Low-Level Interrupt Selection
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Falling Edge/Low-Level Interrupt Selection
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Falling Edge/Low-Level Interrupt Selection
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Falling Edge/Low-Level Interrupt Selection
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Falling Edge/Low-Level Interrupt Selection
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Falling Edge/Low-Level Interrupt Selection
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Falling Edge/Low-Level Interrupt Selection
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Falling Edge/Low-Level Interrupt Selection
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Falling Edge/Low-Level Interrupt Selection
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Falling Edge/Low-Level Interrupt Selection
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Falling Edge/Low-Level Interrupt Selection
impl W<u32, Reg<u32, _REHLSR>>[src]
pub fn p0(&mut self) -> P0_W<'_>[src]
Bit 0 - Rising Edge /High-Level Interrupt Selection
pub fn p1(&mut self) -> P1_W<'_>[src]
Bit 1 - Rising Edge /High-Level Interrupt Selection
pub fn p2(&mut self) -> P2_W<'_>[src]
Bit 2 - Rising Edge /High-Level Interrupt Selection
pub fn p3(&mut self) -> P3_W<'_>[src]
Bit 3 - Rising Edge /High-Level Interrupt Selection
pub fn p4(&mut self) -> P4_W<'_>[src]
Bit 4 - Rising Edge /High-Level Interrupt Selection
pub fn p5(&mut self) -> P5_W<'_>[src]
Bit 5 - Rising Edge /High-Level Interrupt Selection
pub fn p6(&mut self) -> P6_W<'_>[src]
Bit 6 - Rising Edge /High-Level Interrupt Selection
pub fn p7(&mut self) -> P7_W<'_>[src]
Bit 7 - Rising Edge /High-Level Interrupt Selection
pub fn p8(&mut self) -> P8_W<'_>[src]
Bit 8 - Rising Edge /High-Level Interrupt Selection
pub fn p9(&mut self) -> P9_W<'_>[src]
Bit 9 - Rising Edge /High-Level Interrupt Selection
pub fn p10(&mut self) -> P10_W<'_>[src]
Bit 10 - Rising Edge /High-Level Interrupt Selection
pub fn p11(&mut self) -> P11_W<'_>[src]
Bit 11 - Rising Edge /High-Level Interrupt Selection
pub fn p12(&mut self) -> P12_W<'_>[src]
Bit 12 - Rising Edge /High-Level Interrupt Selection
pub fn p13(&mut self) -> P13_W<'_>[src]
Bit 13 - Rising Edge /High-Level Interrupt Selection
pub fn p14(&mut self) -> P14_W<'_>[src]
Bit 14 - Rising Edge /High-Level Interrupt Selection
pub fn p15(&mut self) -> P15_W<'_>[src]
Bit 15 - Rising Edge /High-Level Interrupt Selection
pub fn p16(&mut self) -> P16_W<'_>[src]
Bit 16 - Rising Edge /High-Level Interrupt Selection
pub fn p17(&mut self) -> P17_W<'_>[src]
Bit 17 - Rising Edge /High-Level Interrupt Selection
pub fn p18(&mut self) -> P18_W<'_>[src]
Bit 18 - Rising Edge /High-Level Interrupt Selection
pub fn p19(&mut self) -> P19_W<'_>[src]
Bit 19 - Rising Edge /High-Level Interrupt Selection
pub fn p20(&mut self) -> P20_W<'_>[src]
Bit 20 - Rising Edge /High-Level Interrupt Selection
pub fn p21(&mut self) -> P21_W<'_>[src]
Bit 21 - Rising Edge /High-Level Interrupt Selection
pub fn p22(&mut self) -> P22_W<'_>[src]
Bit 22 - Rising Edge /High-Level Interrupt Selection
pub fn p23(&mut self) -> P23_W<'_>[src]
Bit 23 - Rising Edge /High-Level Interrupt Selection
pub fn p24(&mut self) -> P24_W<'_>[src]
Bit 24 - Rising Edge /High-Level Interrupt Selection
pub fn p25(&mut self) -> P25_W<'_>[src]
Bit 25 - Rising Edge /High-Level Interrupt Selection
pub fn p26(&mut self) -> P26_W<'_>[src]
Bit 26 - Rising Edge /High-Level Interrupt Selection
pub fn p27(&mut self) -> P27_W<'_>[src]
Bit 27 - Rising Edge /High-Level Interrupt Selection
pub fn p28(&mut self) -> P28_W<'_>[src]
Bit 28 - Rising Edge /High-Level Interrupt Selection
pub fn p29(&mut self) -> P29_W<'_>[src]
Bit 29 - Rising Edge /High-Level Interrupt Selection
pub fn p30(&mut self) -> P30_W<'_>[src]
Bit 30 - Rising Edge /High-Level Interrupt Selection
pub fn p31(&mut self) -> P31_W<'_>[src]
Bit 31 - Rising Edge /High-Level Interrupt Selection
impl W<u32, Reg<u32, _WPMR>>[src]
pub fn wpen(&mut self) -> WPEN_W<'_>[src]
Bit 0 - Write Protection Enable
pub fn wpkey(&mut self) -> WPKEY_W<'_>[src]
Bits 8:31 - Write Protection Key.
impl W<u32, Reg<u32, _SCHMITT>>[src]
pub fn schmitt0(&mut self) -> SCHMITT0_W<'_>[src]
Bit 0 - Schmitt Trigger Control
pub fn schmitt1(&mut self) -> SCHMITT1_W<'_>[src]
Bit 1 - Schmitt Trigger Control
pub fn schmitt2(&mut self) -> SCHMITT2_W<'_>[src]
Bit 2 - Schmitt Trigger Control
pub fn schmitt3(&mut self) -> SCHMITT3_W<'_>[src]
Bit 3 - Schmitt Trigger Control
pub fn schmitt4(&mut self) -> SCHMITT4_W<'_>[src]
Bit 4 - Schmitt Trigger Control
pub fn schmitt5(&mut self) -> SCHMITT5_W<'_>[src]
Bit 5 - Schmitt Trigger Control
pub fn schmitt6(&mut self) -> SCHMITT6_W<'_>[src]
Bit 6 - Schmitt Trigger Control
pub fn schmitt7(&mut self) -> SCHMITT7_W<'_>[src]
Bit 7 - Schmitt Trigger Control
pub fn schmitt8(&mut self) -> SCHMITT8_W<'_>[src]
Bit 8 - Schmitt Trigger Control
pub fn schmitt9(&mut self) -> SCHMITT9_W<'_>[src]
Bit 9 - Schmitt Trigger Control
pub fn schmitt10(&mut self) -> SCHMITT10_W<'_>[src]
Bit 10 - Schmitt Trigger Control
pub fn schmitt11(&mut self) -> SCHMITT11_W<'_>[src]
Bit 11 - Schmitt Trigger Control
pub fn schmitt12(&mut self) -> SCHMITT12_W<'_>[src]
Bit 12 - Schmitt Trigger Control
pub fn schmitt13(&mut self) -> SCHMITT13_W<'_>[src]
Bit 13 - Schmitt Trigger Control
pub fn schmitt14(&mut self) -> SCHMITT14_W<'_>[src]
Bit 14 - Schmitt Trigger Control
pub fn schmitt15(&mut self) -> SCHMITT15_W<'_>[src]
Bit 15 - Schmitt Trigger Control
pub fn schmitt16(&mut self) -> SCHMITT16_W<'_>[src]
Bit 16 - Schmitt Trigger Control
pub fn schmitt17(&mut self) -> SCHMITT17_W<'_>[src]
Bit 17 - Schmitt Trigger Control
pub fn schmitt18(&mut self) -> SCHMITT18_W<'_>[src]
Bit 18 - Schmitt Trigger Control
pub fn schmitt19(&mut self) -> SCHMITT19_W<'_>[src]
Bit 19 - Schmitt Trigger Control
pub fn schmitt20(&mut self) -> SCHMITT20_W<'_>[src]
Bit 20 - Schmitt Trigger Control
pub fn schmitt21(&mut self) -> SCHMITT21_W<'_>[src]
Bit 21 - Schmitt Trigger Control
pub fn schmitt22(&mut self) -> SCHMITT22_W<'_>[src]
Bit 22 - Schmitt Trigger Control
pub fn schmitt23(&mut self) -> SCHMITT23_W<'_>[src]
Bit 23 - Schmitt Trigger Control
pub fn schmitt24(&mut self) -> SCHMITT24_W<'_>[src]
Bit 24 - Schmitt Trigger Control
pub fn schmitt25(&mut self) -> SCHMITT25_W<'_>[src]
Bit 25 - Schmitt Trigger Control
pub fn schmitt26(&mut self) -> SCHMITT26_W<'_>[src]
Bit 26 - Schmitt Trigger Control
pub fn schmitt27(&mut self) -> SCHMITT27_W<'_>[src]
Bit 27 - Schmitt Trigger Control
pub fn schmitt28(&mut self) -> SCHMITT28_W<'_>[src]
Bit 28 - Schmitt Trigger Control
pub fn schmitt29(&mut self) -> SCHMITT29_W<'_>[src]
Bit 29 - Schmitt Trigger Control
pub fn schmitt30(&mut self) -> SCHMITT30_W<'_>[src]
Bit 30 - Schmitt Trigger Control
pub fn schmitt31(&mut self) -> SCHMITT31_W<'_>[src]
Bit 31 - Schmitt Trigger Control
impl W<u32, Reg<u32, _PCMR>>[src]
pub fn pcen(&mut self) -> PCEN_W<'_>[src]
Bit 0 - Parallel Capture Mode Enable
pub fn dsize(&mut self) -> DSIZE_W<'_>[src]
Bits 4:5 - Parallel Capture Mode Data Size
pub fn alwys(&mut self) -> ALWYS_W<'_>[src]
Bit 9 - Parallel Capture Mode Always Sampling
pub fn halfs(&mut self) -> HALFS_W<'_>[src]
Bit 10 - Parallel Capture Mode Half Sampling
pub fn frsts(&mut self) -> FRSTS_W<'_>[src]
Bit 11 - Parallel Capture Mode First Sample
impl W<u32, Reg<u32, _PCIER>>[src]
pub fn drdy(&mut self) -> DRDY_W<'_>[src]
Bit 0 - Parallel Capture Mode Data Ready Interrupt Enable
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 1 - Parallel Capture Mode Overrun Error Interrupt Enable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 2 - End of Reception Transfer Interrupt Enable
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 3 - Reception Buffer Full Interrupt Enable
impl W<u32, Reg<u32, _PCIDR>>[src]
pub fn drdy(&mut self) -> DRDY_W<'_>[src]
Bit 0 - Parallel Capture Mode Data Ready Interrupt Disable
pub fn ovre(&mut self) -> OVRE_W<'_>[src]
Bit 1 - Parallel Capture Mode Overrun Error Interrupt Disable
pub fn endrx(&mut self) -> ENDRX_W<'_>[src]
Bit 2 - End of Reception Transfer Interrupt Disable
pub fn rxbuff(&mut self) -> RXBUFF_W<'_>[src]
Bit 3 - Reception Buffer Full Interrupt Disable
impl W<u32, Reg<u32, _CR>>[src]
pub fn procrst(&mut self) -> PROCRST_W<'_>[src]
Bit 0 - Processor Reset
pub fn perrst(&mut self) -> PERRST_W<'_>[src]
Bit 2 - Peripheral Reset
pub fn extrst(&mut self) -> EXTRST_W<'_>[src]
Bit 3 - External Reset
pub fn key(&mut self) -> KEY_W<'_>[src]
Bits 24:31 - System Reset Key
impl W<u32, Reg<u32, _MR>>[src]
pub fn ursten(&mut self) -> URSTEN_W<'_>[src]
Bit 0 - User Reset Enable
pub fn urstien(&mut self) -> URSTIEN_W<'_>[src]
Bit 4 - User Reset Interrupt Enable
pub fn erstl(&mut self) -> ERSTL_W<'_>[src]
Bits 8:11 - External Reset Length
pub fn key(&mut self) -> KEY_W<'_>[src]
Bits 24:31 - Write Access Password
impl W<u32, Reg<u32, _CR>>[src]
pub fn vroff(&mut self) -> VROFF_W<'_>[src]
Bit 2 - Voltage Regulator Off
pub fn xtalsel(&mut self) -> XTALSEL_W<'_>[src]
Bit 3 - Crystal Oscillator Select
pub fn key(&mut self) -> KEY_W<'_>[src]
Bits 24:31 - Password
impl W<u32, Reg<u32, _SMMR>>[src]
pub fn smth(&mut self) -> SMTH_W<'_>[src]
Bits 0:3 - Supply Monitor Threshold
pub fn smsmpl(&mut self) -> SMSMPL_W<'_>[src]
Bits 8:10 - Supply Monitor Sampling Period
pub fn smrsten(&mut self) -> SMRSTEN_W<'_>[src]
Bit 12 - Supply Monitor Reset Enable
pub fn smien(&mut self) -> SMIEN_W<'_>[src]
Bit 13 - Supply Monitor Interrupt Enable
impl W<u32, Reg<u32, _MR>>[src]
pub fn bodrsten(&mut self) -> BODRSTEN_W<'_>[src]
Bit 12 - Brownout Detector Reset Enable
pub fn boddis(&mut self) -> BODDIS_W<'_>[src]
Bit 13 - Brownout Detector Disable
pub fn onreg(&mut self) -> ONREG_W<'_>[src]
Bit 14 - Voltage Regulator Enable
pub fn oscbypass(&mut self) -> OSCBYPASS_W<'_>[src]
Bit 20 - Oscillator Bypass
pub fn key(&mut self) -> KEY_W<'_>[src]
Bits 24:31 - Password Key
impl W<u32, Reg<u32, _WUMR>>[src]
pub fn smen(&mut self) -> SMEN_W<'_>[src]
Bit 1 - Supply Monitor Wake-up Enable
pub fn rtten(&mut self) -> RTTEN_W<'_>[src]
Bit 2 - Real-time Timer Wake-up Enable
pub fn rtcen(&mut self) -> RTCEN_W<'_>[src]
Bit 3 - Real-time Clock Wake-up Enable
pub fn lpdbcen0(&mut self) -> LPDBCEN0_W<'_>[src]
Bit 5 - Low-power Debouncer Enable WKUP0
pub fn lpdbcen1(&mut self) -> LPDBCEN1_W<'_>[src]
Bit 6 - Low-power Debouncer Enable WKUP1
pub fn lpdbcclr(&mut self) -> LPDBCCLR_W<'_>[src]
Bit 7 - Low-power Debouncer Clear
pub fn wkupdbc(&mut self) -> WKUPDBC_W<'_>[src]
Bits 12:14 - Wake-up Inputs Debouncer Period
pub fn lpdbc(&mut self) -> LPDBC_W<'_>[src]
Bits 16:18 - Low-power Debouncer Period
impl W<u32, Reg<u32, _WUIR>>[src]
pub fn wkupen0(&mut self) -> WKUPEN0_W<'_>[src]
Bit 0 - Wake-up Input Enable 0
pub fn wkupen1(&mut self) -> WKUPEN1_W<'_>[src]
Bit 1 - Wake-up Input Enable 1
pub fn wkupen2(&mut self) -> WKUPEN2_W<'_>[src]
Bit 2 - Wake-up Input Enable 2
pub fn wkupen3(&mut self) -> WKUPEN3_W<'_>[src]
Bit 3 - Wake-up Input Enable 3
pub fn wkupen4(&mut self) -> WKUPEN4_W<'_>[src]
Bit 4 - Wake-up Input Enable 4
pub fn wkupen5(&mut self) -> WKUPEN5_W<'_>[src]
Bit 5 - Wake-up Input Enable 5
pub fn wkupen6(&mut self) -> WKUPEN6_W<'_>[src]
Bit 6 - Wake-up Input Enable 6
pub fn wkupen7(&mut self) -> WKUPEN7_W<'_>[src]
Bit 7 - Wake-up Input Enable 7
pub fn wkupen8(&mut self) -> WKUPEN8_W<'_>[src]
Bit 8 - Wake-up Input Enable 8
pub fn wkupen9(&mut self) -> WKUPEN9_W<'_>[src]
Bit 9 - Wake-up Input Enable 9
pub fn wkupen10(&mut self) -> WKUPEN10_W<'_>[src]
Bit 10 - Wake-up Input Enable 10
pub fn wkupen11(&mut self) -> WKUPEN11_W<'_>[src]
Bit 11 - Wake-up Input Enable 11
pub fn wkupen12(&mut self) -> WKUPEN12_W<'_>[src]
Bit 12 - Wake-up Input Enable 12
pub fn wkupen13(&mut self) -> WKUPEN13_W<'_>[src]
Bit 13 - Wake-up Input Enable 13
pub fn wkupen14(&mut self) -> WKUPEN14_W<'_>[src]
Bit 14 - Wake-up Input Enable 14
pub fn wkupen15(&mut self) -> WKUPEN15_W<'_>[src]
Bit 15 - Wake-up Input Enable 15
pub fn wkupt0(&mut self) -> WKUPT0_W<'_>[src]
Bit 16 - Wake-up Input Type 0
pub fn wkupt1(&mut self) -> WKUPT1_W<'_>[src]
Bit 17 - Wake-up Input Type 1
pub fn wkupt2(&mut self) -> WKUPT2_W<'_>[src]
Bit 18 - Wake-up Input Type 2
pub fn wkupt3(&mut self) -> WKUPT3_W<'_>[src]
Bit 19 - Wake-up Input Type 3
pub fn wkupt4(&mut self) -> WKUPT4_W<'_>[src]
Bit 20 - Wake-up Input Type 4
pub fn wkupt5(&mut self) -> WKUPT5_W<'_>[src]
Bit 21 - Wake-up Input Type 5
pub fn wkupt6(&mut self) -> WKUPT6_W<'_>[src]
Bit 22 - Wake-up Input Type 6
pub fn wkupt7(&mut self) -> WKUPT7_W<'_>[src]
Bit 23 - Wake-up Input Type 7
pub fn wkupt8(&mut self) -> WKUPT8_W<'_>[src]
Bit 24 - Wake-up Input Type 8
pub fn wkupt9(&mut self) -> WKUPT9_W<'_>[src]
Bit 25 - Wake-up Input Type 9
pub fn wkupt10(&mut self) -> WKUPT10_W<'_>[src]
Bit 26 - Wake-up Input Type 10
pub fn wkupt11(&mut self) -> WKUPT11_W<'_>[src]
Bit 27 - Wake-up Input Type 11
pub fn wkupt12(&mut self) -> WKUPT12_W<'_>[src]
Bit 28 - Wake-up Input Type 12
pub fn wkupt13(&mut self) -> WKUPT13_W<'_>[src]
Bit 29 - Wake-up Input Type 13
pub fn wkupt14(&mut self) -> WKUPT14_W<'_>[src]
Bit 30 - Wake-up Input Type 14
pub fn wkupt15(&mut self) -> WKUPT15_W<'_>[src]
Bit 31 - Wake-up Input Type 15
impl W<u32, Reg<u32, _MR>>[src]
pub fn rtpres(&mut self) -> RTPRES_W<'_>[src]
Bits 0:15 - Real-time Timer Prescaler Value
pub fn almien(&mut self) -> ALMIEN_W<'_>[src]
Bit 16 - Alarm Interrupt Enable
pub fn rttincien(&mut self) -> RTTINCIEN_W<'_>[src]
Bit 17 - Real-time Timer Increment Interrupt Enable
pub fn rttrst(&mut self) -> RTTRST_W<'_>[src]
Bit 18 - Real-time Timer Restart
pub fn rttdis(&mut self) -> RTTDIS_W<'_>[src]
Bit 20 - Real-time Timer Disable
pub fn rtc1hz(&mut self) -> RTC1HZ_W<'_>[src]
Bit 24 - Real-Time Clock 1 Hz Clock Selection
impl W<u32, Reg<u32, _AR>>[src]
impl W<u32, Reg<u32, _CR>>[src]
pub fn wdrstt(&mut self) -> WDRSTT_W<'_>[src]
Bit 0 - Watchdog Restart
pub fn key(&mut self) -> KEY_W<'_>[src]
Bits 24:31 - Password.
impl W<u32, Reg<u32, _MR>>[src]
pub fn wdv(&mut self) -> WDV_W<'_>[src]
Bits 0:11 - Watchdog Counter Value
pub fn wdfien(&mut self) -> WDFIEN_W<'_>[src]
Bit 12 - Watchdog Fault Interrupt Enable
pub fn wdrsten(&mut self) -> WDRSTEN_W<'_>[src]
Bit 13 - Watchdog Reset Enable
pub fn wdrproc(&mut self) -> WDRPROC_W<'_>[src]
Bit 14 - Watchdog Reset Processor
pub fn wddis(&mut self) -> WDDIS_W<'_>[src]
Bit 15 - Watchdog Disable
pub fn wdd(&mut self) -> WDD_W<'_>[src]
Bits 16:27 - Watchdog Delta Value
pub fn wddbghlt(&mut self) -> WDDBGHLT_W<'_>[src]
Bit 28 - Watchdog Debug Halt
pub fn wdidlehlt(&mut self) -> WDIDLEHLT_W<'_>[src]
Bit 29 - Watchdog Idle Halt
impl W<u32, Reg<u32, _CR>>[src]
pub fn updtim(&mut self) -> UPDTIM_W<'_>[src]
Bit 0 - Update Request Time Register
pub fn updcal(&mut self) -> UPDCAL_W<'_>[src]
Bit 1 - Update Request Calendar Register
pub fn timevsel(&mut self) -> TIMEVSEL_W<'_>[src]
Bits 8:9 - Time Event Selection
pub fn calevsel(&mut self) -> CALEVSEL_W<'_>[src]
Bits 16:17 - Calendar Event Selection
impl W<u32, Reg<u32, _MR>>[src]
pub fn hrmod(&mut self) -> HRMOD_W<'_>[src]
Bit 0 - 12-/24-hour Mode
pub fn persian(&mut self) -> PERSIAN_W<'_>[src]
Bit 1 - PERSIAN Calendar
pub fn negppm(&mut self) -> NEGPPM_W<'_>[src]
Bit 4 - NEGative PPM Correction
pub fn correction(&mut self) -> CORRECTION_W<'_>[src]
Bits 8:14 - Slow Clock Correction
pub fn highppm(&mut self) -> HIGHPPM_W<'_>[src]
Bit 15 - HIGH PPM Correction
pub fn out0(&mut self) -> OUT0_W<'_>[src]
Bits 16:18 - RTCOUT0 OutputSource Selection
pub fn out1(&mut self) -> OUT1_W<'_>[src]
Bits 20:22 - RTCOUT1 Output Source Selection
pub fn thigh(&mut self) -> THIGH_W<'_>[src]
Bits 24:26 - High Duration of the Output Pulse
pub fn tperiod(&mut self) -> TPERIOD_W<'_>[src]
Bits 28:29 - Period of the Output Pulse
impl W<u32, Reg<u32, _TIMR>>[src]
pub fn sec(&mut self) -> SEC_W<'_>[src]
Bits 0:6 - Current Second
pub fn min(&mut self) -> MIN_W<'_>[src]
Bits 8:14 - Current Minute
pub fn hour(&mut self) -> HOUR_W<'_>[src]
Bits 16:21 - Current Hour
pub fn ampm(&mut self) -> AMPM_W<'_>[src]
Bit 22 - Ante Meridiem Post Meridiem Indicator
impl W<u32, Reg<u32, _CALR>>[src]
pub fn cent(&mut self) -> CENT_W<'_>[src]
Bits 0:6 - Current Century
pub fn year(&mut self) -> YEAR_W<'_>[src]
Bits 8:15 - Current Year
pub fn month(&mut self) -> MONTH_W<'_>[src]
Bits 16:20 - Current Month
pub fn day(&mut self) -> DAY_W<'_>[src]
Bits 21:23 - Current Day in Current Week
pub fn date(&mut self) -> DATE_W<'_>[src]
Bits 24:29 - Current Day in Current Month
impl W<u32, Reg<u32, _TIMALR>>[src]
pub fn sec(&mut self) -> SEC_W<'_>[src]
Bits 0:6 - Second Alarm
pub fn secen(&mut self) -> SECEN_W<'_>[src]
Bit 7 - Second Alarm Enable
pub fn min(&mut self) -> MIN_W<'_>[src]
Bits 8:14 - Minute Alarm
pub fn minen(&mut self) -> MINEN_W<'_>[src]
Bit 15 - Minute Alarm Enable
pub fn hour(&mut self) -> HOUR_W<'_>[src]
Bits 16:21 - Hour Alarm
pub fn ampm(&mut self) -> AMPM_W<'_>[src]
Bit 22 - AM/PM Indicator
pub fn houren(&mut self) -> HOUREN_W<'_>[src]
Bit 23 - Hour Alarm Enable
impl W<u32, Reg<u32, _CALALR>>[src]
pub fn month(&mut self) -> MONTH_W<'_>[src]
Bits 16:20 - Month Alarm
pub fn mthen(&mut self) -> MTHEN_W<'_>[src]
Bit 23 - Month Alarm Enable
pub fn date(&mut self) -> DATE_W<'_>[src]
Bits 24:29 - Date Alarm
pub fn dateen(&mut self) -> DATEEN_W<'_>[src]
Bit 31 - Date Alarm Enable
impl W<u32, Reg<u32, _SCCR>>[src]
pub fn ackclr(&mut self) -> ACKCLR_W<'_>[src]
Bit 0 - Acknowledge Clear
pub fn alrclr(&mut self) -> ALRCLR_W<'_>[src]
Bit 1 - Alarm Clear
pub fn secclr(&mut self) -> SECCLR_W<'_>[src]
Bit 2 - Second Clear
pub fn timclr(&mut self) -> TIMCLR_W<'_>[src]
Bit 3 - Time Clear
pub fn calclr(&mut self) -> CALCLR_W<'_>[src]
Bit 4 - Calendar Clear
pub fn tderrclr(&mut self) -> TDERRCLR_W<'_>[src]
Bit 5 - Time and/or Date Free Running Error Clear
impl W<u32, Reg<u32, _IER>>[src]
pub fn acken(&mut self) -> ACKEN_W<'_>[src]
Bit 0 - Acknowledge Update Interrupt Enable
pub fn alren(&mut self) -> ALREN_W<'_>[src]
Bit 1 - Alarm Interrupt Enable
pub fn secen(&mut self) -> SECEN_W<'_>[src]
Bit 2 - Second Event Interrupt Enable
pub fn timen(&mut self) -> TIMEN_W<'_>[src]
Bit 3 - Time Event Interrupt Enable
pub fn calen(&mut self) -> CALEN_W<'_>[src]
Bit 4 - Calendar Event Interrupt Enable
pub fn tderren(&mut self) -> TDERREN_W<'_>[src]
Bit 5 - Time and/or Date Error Interrupt Enable
impl W<u32, Reg<u32, _IDR>>[src]
pub fn ackdis(&mut self) -> ACKDIS_W<'_>[src]
Bit 0 - Acknowledge Update Interrupt Disable
pub fn alrdis(&mut self) -> ALRDIS_W<'_>[src]
Bit 1 - Alarm Interrupt Disable
pub fn secdis(&mut self) -> SECDIS_W<'_>[src]
Bit 2 - Second Event Interrupt Disable
pub fn timdis(&mut self) -> TIMDIS_W<'_>[src]
Bit 3 - Time Event Interrupt Disable
pub fn caldis(&mut self) -> CALDIS_W<'_>[src]
Bit 4 - Calendar Event Interrupt Disable
pub fn tderrdis(&mut self) -> TDERRDIS_W<'_>[src]
Bit 5 - Time and/or Date Error Interrupt Disable
impl W<u32, Reg<u32, _GPBR>>[src]
pub fn gpbr_value(&mut self) -> GPBR_VALUE_W<'_>[src]
Bits 0:31 - Value of GPBR x
Auto Trait Implementations
impl<U, REG> Send for W<U, REG> where
REG: Send,
U: Send,
REG: Send,
U: Send,
impl<U, REG> Sync for W<U, REG> where
REG: Sync,
U: Sync,
REG: Sync,
U: Sync,
impl<U, REG> Unpin for W<U, REG> where
REG: Unpin,
U: Unpin,
REG: Unpin,
U: Unpin,
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized, [src]
T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized, [src]
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized, [src]
T: ?Sized,
pub fn borrow_mut(&mut self) -> &mut T[src]
impl<T> From<T> for T[src]
impl<T, U> Into<U> for T where
U: From<T>, [src]
U: From<T>,
impl<T> Same<T> for T
type Output = T
Should always be Self
impl<T, U> TryFrom<U> for T where
U: Into<T>, [src]
U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
pub fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>[src]
impl<T, U> TryInto<U> for T where
U: TryFrom<T>, [src]
U: TryFrom<T>,