atsam4sd16c_pac/pmc/
pmc_scdr.rs

1#[doc = "Register `PMC_SCDR` writer"]
2pub struct W(crate::W<PMC_SCDR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<PMC_SCDR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<PMC_SCDR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<PMC_SCDR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `UDP` writer - USB Device Port Clock Disable"]
23pub type UDP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PMC_SCDR_SPEC, bool, O>;
24#[doc = "Field `PCK0` writer - Programmable Clock 0 Output Disable"]
25pub type PCK0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PMC_SCDR_SPEC, bool, O>;
26#[doc = "Field `PCK1` writer - Programmable Clock 1 Output Disable"]
27pub type PCK1_W<'a, const O: u8> = crate::BitWriter<'a, u32, PMC_SCDR_SPEC, bool, O>;
28#[doc = "Field `PCK2` writer - Programmable Clock 2 Output Disable"]
29pub type PCK2_W<'a, const O: u8> = crate::BitWriter<'a, u32, PMC_SCDR_SPEC, bool, O>;
30impl W {
31    #[doc = "Bit 7 - USB Device Port Clock Disable"]
32    #[inline(always)]
33    #[must_use]
34    pub fn udp(&mut self) -> UDP_W<7> {
35        UDP_W::new(self)
36    }
37    #[doc = "Bit 8 - Programmable Clock 0 Output Disable"]
38    #[inline(always)]
39    #[must_use]
40    pub fn pck0(&mut self) -> PCK0_W<8> {
41        PCK0_W::new(self)
42    }
43    #[doc = "Bit 9 - Programmable Clock 1 Output Disable"]
44    #[inline(always)]
45    #[must_use]
46    pub fn pck1(&mut self) -> PCK1_W<9> {
47        PCK1_W::new(self)
48    }
49    #[doc = "Bit 10 - Programmable Clock 2 Output Disable"]
50    #[inline(always)]
51    #[must_use]
52    pub fn pck2(&mut self) -> PCK2_W<10> {
53        PCK2_W::new(self)
54    }
55    #[doc = "Writes raw bits to the register."]
56    #[inline(always)]
57    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
58        self.0.bits(bits);
59        self
60    }
61}
62#[doc = "System Clock Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmc_scdr](index.html) module"]
63pub struct PMC_SCDR_SPEC;
64impl crate::RegisterSpec for PMC_SCDR_SPEC {
65    type Ux = u32;
66}
67#[doc = "`write(|w| ..)` method takes [pmc_scdr::W](W) writer structure"]
68impl crate::Writable for PMC_SCDR_SPEC {
69    type Writer = W;
70    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
71    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
72}
atsam4sd16c_pac/pmc/pmc_scdr.rs

atsam4sd16c_pac/pmc/
pmc_scdr.rs
