1#[doc = "Register `IER2` writer"]
2pub struct W(crate::W<IER2_SPEC>);
3impl core::ops::Deref for W {
4 type Target = crate::W<IER2_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl core::ops::DerefMut for W {
11 #[inline(always)]
12 fn deref_mut(&mut self) -> &mut Self::Target {
13 &mut self.0
14 }
15}
16impl From<crate::W<IER2_SPEC>> for W {
17 #[inline(always)]
18 fn from(writer: crate::W<IER2_SPEC>) -> Self {
19 W(writer)
20 }
21}
22#[doc = "Field `WRDY` writer - Write Ready for Synchronous Channels Update Interrupt Enable"]
23pub type WRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
24#[doc = "Field `ENDTX` writer - PDC End of TX Buffer Interrupt Enable"]
25pub type ENDTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
26#[doc = "Field `TXBUFE` writer - PDC TX Buffer Empty Interrupt Enable"]
27pub type TXBUFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
28#[doc = "Field `UNRE` writer - Synchronous Channels Update Underrun Error Interrupt Enable"]
29pub type UNRE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
30#[doc = "Field `CMPM0` writer - Comparison 0 Match Interrupt Enable"]
31pub type CMPM0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
32#[doc = "Field `CMPM1` writer - Comparison 1 Match Interrupt Enable"]
33pub type CMPM1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
34#[doc = "Field `CMPM2` writer - Comparison 2 Match Interrupt Enable"]
35pub type CMPM2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
36#[doc = "Field `CMPM3` writer - Comparison 3 Match Interrupt Enable"]
37pub type CMPM3_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
38#[doc = "Field `CMPM4` writer - Comparison 4 Match Interrupt Enable"]
39pub type CMPM4_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
40#[doc = "Field `CMPM5` writer - Comparison 5 Match Interrupt Enable"]
41pub type CMPM5_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
42#[doc = "Field `CMPM6` writer - Comparison 6 Match Interrupt Enable"]
43pub type CMPM6_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
44#[doc = "Field `CMPM7` writer - Comparison 7 Match Interrupt Enable"]
45pub type CMPM7_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
46#[doc = "Field `CMPU0` writer - Comparison 0 Update Interrupt Enable"]
47pub type CMPU0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
48#[doc = "Field `CMPU1` writer - Comparison 1 Update Interrupt Enable"]
49pub type CMPU1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
50#[doc = "Field `CMPU2` writer - Comparison 2 Update Interrupt Enable"]
51pub type CMPU2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
52#[doc = "Field `CMPU3` writer - Comparison 3 Update Interrupt Enable"]
53pub type CMPU3_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
54#[doc = "Field `CMPU4` writer - Comparison 4 Update Interrupt Enable"]
55pub type CMPU4_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
56#[doc = "Field `CMPU5` writer - Comparison 5 Update Interrupt Enable"]
57pub type CMPU5_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
58#[doc = "Field `CMPU6` writer - Comparison 6 Update Interrupt Enable"]
59pub type CMPU6_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
60#[doc = "Field `CMPU7` writer - Comparison 7 Update Interrupt Enable"]
61pub type CMPU7_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
62impl W {
63 #[doc = "Bit 0 - Write Ready for Synchronous Channels Update Interrupt Enable"]
64 #[inline(always)]
65 #[must_use]
66 pub fn wrdy(&mut self) -> WRDY_W<0> {
67 WRDY_W::new(self)
68 }
69 #[doc = "Bit 1 - PDC End of TX Buffer Interrupt Enable"]
70 #[inline(always)]
71 #[must_use]
72 pub fn endtx(&mut self) -> ENDTX_W<1> {
73 ENDTX_W::new(self)
74 }
75 #[doc = "Bit 2 - PDC TX Buffer Empty Interrupt Enable"]
76 #[inline(always)]
77 #[must_use]
78 pub fn txbufe(&mut self) -> TXBUFE_W<2> {
79 TXBUFE_W::new(self)
80 }
81 #[doc = "Bit 3 - Synchronous Channels Update Underrun Error Interrupt Enable"]
82 #[inline(always)]
83 #[must_use]
84 pub fn unre(&mut self) -> UNRE_W<3> {
85 UNRE_W::new(self)
86 }
87 #[doc = "Bit 8 - Comparison 0 Match Interrupt Enable"]
88 #[inline(always)]
89 #[must_use]
90 pub fn cmpm0(&mut self) -> CMPM0_W<8> {
91 CMPM0_W::new(self)
92 }
93 #[doc = "Bit 9 - Comparison 1 Match Interrupt Enable"]
94 #[inline(always)]
95 #[must_use]
96 pub fn cmpm1(&mut self) -> CMPM1_W<9> {
97 CMPM1_W::new(self)
98 }
99 #[doc = "Bit 10 - Comparison 2 Match Interrupt Enable"]
100 #[inline(always)]
101 #[must_use]
102 pub fn cmpm2(&mut self) -> CMPM2_W<10> {
103 CMPM2_W::new(self)
104 }
105 #[doc = "Bit 11 - Comparison 3 Match Interrupt Enable"]
106 #[inline(always)]
107 #[must_use]
108 pub fn cmpm3(&mut self) -> CMPM3_W<11> {
109 CMPM3_W::new(self)
110 }
111 #[doc = "Bit 12 - Comparison 4 Match Interrupt Enable"]
112 #[inline(always)]
113 #[must_use]
114 pub fn cmpm4(&mut self) -> CMPM4_W<12> {
115 CMPM4_W::new(self)
116 }
117 #[doc = "Bit 13 - Comparison 5 Match Interrupt Enable"]
118 #[inline(always)]
119 #[must_use]
120 pub fn cmpm5(&mut self) -> CMPM5_W<13> {
121 CMPM5_W::new(self)
122 }
123 #[doc = "Bit 14 - Comparison 6 Match Interrupt Enable"]
124 #[inline(always)]
125 #[must_use]
126 pub fn cmpm6(&mut self) -> CMPM6_W<14> {
127 CMPM6_W::new(self)
128 }
129 #[doc = "Bit 15 - Comparison 7 Match Interrupt Enable"]
130 #[inline(always)]
131 #[must_use]
132 pub fn cmpm7(&mut self) -> CMPM7_W<15> {
133 CMPM7_W::new(self)
134 }
135 #[doc = "Bit 16 - Comparison 0 Update Interrupt Enable"]
136 #[inline(always)]
137 #[must_use]
138 pub fn cmpu0(&mut self) -> CMPU0_W<16> {
139 CMPU0_W::new(self)
140 }
141 #[doc = "Bit 17 - Comparison 1 Update Interrupt Enable"]
142 #[inline(always)]
143 #[must_use]
144 pub fn cmpu1(&mut self) -> CMPU1_W<17> {
145 CMPU1_W::new(self)
146 }
147 #[doc = "Bit 18 - Comparison 2 Update Interrupt Enable"]
148 #[inline(always)]
149 #[must_use]
150 pub fn cmpu2(&mut self) -> CMPU2_W<18> {
151 CMPU2_W::new(self)
152 }
153 #[doc = "Bit 19 - Comparison 3 Update Interrupt Enable"]
154 #[inline(always)]
155 #[must_use]
156 pub fn cmpu3(&mut self) -> CMPU3_W<19> {
157 CMPU3_W::new(self)
158 }
159 #[doc = "Bit 20 - Comparison 4 Update Interrupt Enable"]
160 #[inline(always)]
161 #[must_use]
162 pub fn cmpu4(&mut self) -> CMPU4_W<20> {
163 CMPU4_W::new(self)
164 }
165 #[doc = "Bit 21 - Comparison 5 Update Interrupt Enable"]
166 #[inline(always)]
167 #[must_use]
168 pub fn cmpu5(&mut self) -> CMPU5_W<21> {
169 CMPU5_W::new(self)
170 }
171 #[doc = "Bit 22 - Comparison 6 Update Interrupt Enable"]
172 #[inline(always)]
173 #[must_use]
174 pub fn cmpu6(&mut self) -> CMPU6_W<22> {
175 CMPU6_W::new(self)
176 }
177 #[doc = "Bit 23 - Comparison 7 Update Interrupt Enable"]
178 #[inline(always)]
179 #[must_use]
180 pub fn cmpu7(&mut self) -> CMPU7_W<23> {
181 CMPU7_W::new(self)
182 }
183 #[doc = "Writes raw bits to the register."]
184 #[inline(always)]
185 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
186 self.0.bits(bits);
187 self
188 }
189}
190#[doc = "PWM Interrupt Enable Register 2\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier2](index.html) module"]
191pub struct IER2_SPEC;
192impl crate::RegisterSpec for IER2_SPEC {
193 type Ux = u32;
194}
195#[doc = "`write(|w| ..)` method takes [ier2::W](W) writer structure"]
196impl crate::Writable for IER2_SPEC {
197 type Writer = W;
198 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
199 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
200}