atsam4sd16b_pac/rtc/
ier.rs

1#[doc = "Register `IER` writer"]
2pub struct W(crate::W<IER_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<IER_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<IER_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<IER_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `ACKEN` writer - Acknowledge Update Interrupt Enable"]
23pub type ACKEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
24#[doc = "Field `ALREN` writer - Alarm Interrupt Enable"]
25pub type ALREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
26#[doc = "Field `SECEN` writer - Second Event Interrupt Enable"]
27pub type SECEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
28#[doc = "Field `TIMEN` writer - Time Event Interrupt Enable"]
29pub type TIMEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
30#[doc = "Field `CALEN` writer - Calendar Event Interrupt Enable"]
31pub type CALEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
32#[doc = "Field `TDERREN` writer - Time and/or Date Error Interrupt Enable"]
33pub type TDERREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
34impl W {
35    #[doc = "Bit 0 - Acknowledge Update Interrupt Enable"]
36    #[inline(always)]
37    #[must_use]
38    pub fn acken(&mut self) -> ACKEN_W<0> {
39        ACKEN_W::new(self)
40    }
41    #[doc = "Bit 1 - Alarm Interrupt Enable"]
42    #[inline(always)]
43    #[must_use]
44    pub fn alren(&mut self) -> ALREN_W<1> {
45        ALREN_W::new(self)
46    }
47    #[doc = "Bit 2 - Second Event Interrupt Enable"]
48    #[inline(always)]
49    #[must_use]
50    pub fn secen(&mut self) -> SECEN_W<2> {
51        SECEN_W::new(self)
52    }
53    #[doc = "Bit 3 - Time Event Interrupt Enable"]
54    #[inline(always)]
55    #[must_use]
56    pub fn timen(&mut self) -> TIMEN_W<3> {
57        TIMEN_W::new(self)
58    }
59    #[doc = "Bit 4 - Calendar Event Interrupt Enable"]
60    #[inline(always)]
61    #[must_use]
62    pub fn calen(&mut self) -> CALEN_W<4> {
63        CALEN_W::new(self)
64    }
65    #[doc = "Bit 5 - Time and/or Date Error Interrupt Enable"]
66    #[inline(always)]
67    #[must_use]
68    pub fn tderren(&mut self) -> TDERREN_W<5> {
69        TDERREN_W::new(self)
70    }
71    #[doc = "Writes raw bits to the register."]
72    #[inline(always)]
73    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
74        self.0.bits(bits);
75        self
76    }
77}
78#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"]
79pub struct IER_SPEC;
80impl crate::RegisterSpec for IER_SPEC {
81    type Ux = u32;
82}
83#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"]
84impl crate::Writable for IER_SPEC {
85    type Writer = W;
86    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
87    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
88}
atsam4sd16b_pac/rtc/ier.rs

atsam4sd16b_pac/rtc/
ier.rs
