atsam4sa16c_pac/ssc/
imr.rs1#[doc = "Register `IMR` reader"]
2pub struct R(crate::R<IMR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<IMR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<IMR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<IMR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Field `TXRDY` reader - Transmit Ready Interrupt Mask"]
17pub type TXRDY_R = crate::BitReader<bool>;
18#[doc = "Field `TXEMPTY` reader - Transmit Empty Interrupt Mask"]
19pub type TXEMPTY_R = crate::BitReader<bool>;
20#[doc = "Field `ENDTX` reader - End of Transmission Interrupt Mask"]
21pub type ENDTX_R = crate::BitReader<bool>;
22#[doc = "Field `TXBUFE` reader - "]
23pub type TXBUFE_R = crate::BitReader<bool>;
24#[doc = "Field `RXRDY` reader - Receive Ready Interrupt Mask"]
25pub type RXRDY_R = crate::BitReader<bool>;
26#[doc = "Field `OVRUN` reader - Receive Overrun Interrupt Mask"]
27pub type OVRUN_R = crate::BitReader<bool>;
28#[doc = "Field `ENDRX` reader - End of Reception Interrupt Mask"]
29pub type ENDRX_R = crate::BitReader<bool>;
30#[doc = "Field `RXBUFF` reader - "]
31pub type RXBUFF_R = crate::BitReader<bool>;
32#[doc = "Field `CP0` reader - Compare 0 Interrupt Mask"]
33pub type CP0_R = crate::BitReader<bool>;
34#[doc = "Field `CP1` reader - Compare 1 Interrupt Mask"]
35pub type CP1_R = crate::BitReader<bool>;
36#[doc = "Field `TXSYN` reader - Tx Sync Interrupt Mask"]
37pub type TXSYN_R = crate::BitReader<bool>;
38#[doc = "Field `RXSYN` reader - Rx Sync Interrupt Mask"]
39pub type RXSYN_R = crate::BitReader<bool>;
40impl R {
41 #[doc = "Bit 0 - Transmit Ready Interrupt Mask"]
42 #[inline(always)]
43 pub fn txrdy(&self) -> TXRDY_R {
44 TXRDY_R::new((self.bits & 1) != 0)
45 }
46 #[doc = "Bit 1 - Transmit Empty Interrupt Mask"]
47 #[inline(always)]
48 pub fn txempty(&self) -> TXEMPTY_R {
49 TXEMPTY_R::new(((self.bits >> 1) & 1) != 0)
50 }
51 #[doc = "Bit 2 - End of Transmission Interrupt Mask"]
52 #[inline(always)]
53 pub fn endtx(&self) -> ENDTX_R {
54 ENDTX_R::new(((self.bits >> 2) & 1) != 0)
55 }
56 #[doc = "Bit 3"]
57 #[inline(always)]
58 pub fn txbufe(&self) -> TXBUFE_R {
59 TXBUFE_R::new(((self.bits >> 3) & 1) != 0)
60 }
61 #[doc = "Bit 4 - Receive Ready Interrupt Mask"]
62 #[inline(always)]
63 pub fn rxrdy(&self) -> RXRDY_R {
64 RXRDY_R::new(((self.bits >> 4) & 1) != 0)
65 }
66 #[doc = "Bit 5 - Receive Overrun Interrupt Mask"]
67 #[inline(always)]
68 pub fn ovrun(&self) -> OVRUN_R {
69 OVRUN_R::new(((self.bits >> 5) & 1) != 0)
70 }
71 #[doc = "Bit 6 - End of Reception Interrupt Mask"]
72 #[inline(always)]
73 pub fn endrx(&self) -> ENDRX_R {
74 ENDRX_R::new(((self.bits >> 6) & 1) != 0)
75 }
76 #[doc = "Bit 7"]
77 #[inline(always)]
78 pub fn rxbuff(&self) -> RXBUFF_R {
79 RXBUFF_R::new(((self.bits >> 7) & 1) != 0)
80 }
81 #[doc = "Bit 8 - Compare 0 Interrupt Mask"]
82 #[inline(always)]
83 pub fn cp0(&self) -> CP0_R {
84 CP0_R::new(((self.bits >> 8) & 1) != 0)
85 }
86 #[doc = "Bit 9 - Compare 1 Interrupt Mask"]
87 #[inline(always)]
88 pub fn cp1(&self) -> CP1_R {
89 CP1_R::new(((self.bits >> 9) & 1) != 0)
90 }
91 #[doc = "Bit 10 - Tx Sync Interrupt Mask"]
92 #[inline(always)]
93 pub fn txsyn(&self) -> TXSYN_R {
94 TXSYN_R::new(((self.bits >> 10) & 1) != 0)
95 }
96 #[doc = "Bit 11 - Rx Sync Interrupt Mask"]
97 #[inline(always)]
98 pub fn rxsyn(&self) -> RXSYN_R {
99 RXSYN_R::new(((self.bits >> 11) & 1) != 0)
100 }
101}
102#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"]
103pub struct IMR_SPEC;
104impl crate::RegisterSpec for IMR_SPEC {
105 type Ux = u32;
106}
107#[doc = "`read()` method returns [imr::R](R) reader structure"]
108impl crate::Readable for IMR_SPEC {
109 type Reader = R;
110}
111#[doc = "`reset()` method sets IMR to value 0"]
112impl crate::Resettable for IMR_SPEC {
113 const RESET_VALUE: Self::Ux = 0;
114}