atsam4sa16b_pac/usart0/
imr.rs

1#[doc = "Register `IMR` reader"]
2pub struct R(crate::R<IMR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IMR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IMR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IMR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `RXRDY` reader - RXRDY Interrupt Mask"]
17pub type RXRDY_R = crate::BitReader<bool>;
18#[doc = "Field `TXRDY` reader - TXRDY Interrupt Mask"]
19pub type TXRDY_R = crate::BitReader<bool>;
20#[doc = "Field `RXBRK` reader - Receiver Break Interrupt Mask"]
21pub type RXBRK_R = crate::BitReader<bool>;
22#[doc = "Field `ENDRX` reader - End of Receive Transfer Interrupt Mask (available in all USART modes of operation)"]
23pub type ENDRX_R = crate::BitReader<bool>;
24#[doc = "Field `ENDTX` reader - End of Transmit Interrupt Mask (available in all USART modes of operation)"]
25pub type ENDTX_R = crate::BitReader<bool>;
26#[doc = "Field `OVRE` reader - Overrun Error Interrupt Mask"]
27pub type OVRE_R = crate::BitReader<bool>;
28#[doc = "Field `FRAME` reader - Framing Error Interrupt Mask"]
29pub type FRAME_R = crate::BitReader<bool>;
30#[doc = "Field `PARE` reader - Parity Error Interrupt Mask"]
31pub type PARE_R = crate::BitReader<bool>;
32#[doc = "Field `TIMEOUT` reader - Time-out Interrupt Mask"]
33pub type TIMEOUT_R = crate::BitReader<bool>;
34#[doc = "Field `TXEMPTY` reader - TXEMPTY Interrupt Mask"]
35pub type TXEMPTY_R = crate::BitReader<bool>;
36#[doc = "Field `ITER` reader - Max Number of Repetitions Reached Interrupt Mask"]
37pub type ITER_R = crate::BitReader<bool>;
38#[doc = "Field `TXBUFE` reader - Buffer Empty Interrupt Mask (available in all USART modes of operation)"]
39pub type TXBUFE_R = crate::BitReader<bool>;
40#[doc = "Field `RXBUFF` reader - Buffer Full Interrupt Mask (available in all USART modes of operation)"]
41pub type RXBUFF_R = crate::BitReader<bool>;
42#[doc = "Field `NACK` reader - Non AcknowledgeInterrupt Mask"]
43pub type NACK_R = crate::BitReader<bool>;
44#[doc = "Field `RIIC` reader - Ring Indicator Input Change Mask"]
45pub type RIIC_R = crate::BitReader<bool>;
46#[doc = "Field `DSRIC` reader - Data Set Ready Input Change Mask"]
47pub type DSRIC_R = crate::BitReader<bool>;
48#[doc = "Field `DCDIC` reader - Data Carrier Detect Input Change Interrupt Mask"]
49pub type DCDIC_R = crate::BitReader<bool>;
50#[doc = "Field `CTSIC` reader - Clear to Send Input Change Interrupt Mask"]
51pub type CTSIC_R = crate::BitReader<bool>;
52#[doc = "Field `MANE` reader - Manchester Error Interrupt Mask"]
53pub type MANE_R = crate::BitReader<bool>;
54impl R {
55    #[doc = "Bit 0 - RXRDY Interrupt Mask"]
56    #[inline(always)]
57    pub fn rxrdy(&self) -> RXRDY_R {
58        RXRDY_R::new((self.bits & 1) != 0)
59    }
60    #[doc = "Bit 1 - TXRDY Interrupt Mask"]
61    #[inline(always)]
62    pub fn txrdy(&self) -> TXRDY_R {
63        TXRDY_R::new(((self.bits >> 1) & 1) != 0)
64    }
65    #[doc = "Bit 2 - Receiver Break Interrupt Mask"]
66    #[inline(always)]
67    pub fn rxbrk(&self) -> RXBRK_R {
68        RXBRK_R::new(((self.bits >> 2) & 1) != 0)
69    }
70    #[doc = "Bit 3 - End of Receive Transfer Interrupt Mask (available in all USART modes of operation)"]
71    #[inline(always)]
72    pub fn endrx(&self) -> ENDRX_R {
73        ENDRX_R::new(((self.bits >> 3) & 1) != 0)
74    }
75    #[doc = "Bit 4 - End of Transmit Interrupt Mask (available in all USART modes of operation)"]
76    #[inline(always)]
77    pub fn endtx(&self) -> ENDTX_R {
78        ENDTX_R::new(((self.bits >> 4) & 1) != 0)
79    }
80    #[doc = "Bit 5 - Overrun Error Interrupt Mask"]
81    #[inline(always)]
82    pub fn ovre(&self) -> OVRE_R {
83        OVRE_R::new(((self.bits >> 5) & 1) != 0)
84    }
85    #[doc = "Bit 6 - Framing Error Interrupt Mask"]
86    #[inline(always)]
87    pub fn frame(&self) -> FRAME_R {
88        FRAME_R::new(((self.bits >> 6) & 1) != 0)
89    }
90    #[doc = "Bit 7 - Parity Error Interrupt Mask"]
91    #[inline(always)]
92    pub fn pare(&self) -> PARE_R {
93        PARE_R::new(((self.bits >> 7) & 1) != 0)
94    }
95    #[doc = "Bit 8 - Time-out Interrupt Mask"]
96    #[inline(always)]
97    pub fn timeout(&self) -> TIMEOUT_R {
98        TIMEOUT_R::new(((self.bits >> 8) & 1) != 0)
99    }
100    #[doc = "Bit 9 - TXEMPTY Interrupt Mask"]
101    #[inline(always)]
102    pub fn txempty(&self) -> TXEMPTY_R {
103        TXEMPTY_R::new(((self.bits >> 9) & 1) != 0)
104    }
105    #[doc = "Bit 10 - Max Number of Repetitions Reached Interrupt Mask"]
106    #[inline(always)]
107    pub fn iter(&self) -> ITER_R {
108        ITER_R::new(((self.bits >> 10) & 1) != 0)
109    }
110    #[doc = "Bit 11 - Buffer Empty Interrupt Mask (available in all USART modes of operation)"]
111    #[inline(always)]
112    pub fn txbufe(&self) -> TXBUFE_R {
113        TXBUFE_R::new(((self.bits >> 11) & 1) != 0)
114    }
115    #[doc = "Bit 12 - Buffer Full Interrupt Mask (available in all USART modes of operation)"]
116    #[inline(always)]
117    pub fn rxbuff(&self) -> RXBUFF_R {
118        RXBUFF_R::new(((self.bits >> 12) & 1) != 0)
119    }
120    #[doc = "Bit 13 - Non AcknowledgeInterrupt Mask"]
121    #[inline(always)]
122    pub fn nack(&self) -> NACK_R {
123        NACK_R::new(((self.bits >> 13) & 1) != 0)
124    }
125    #[doc = "Bit 16 - Ring Indicator Input Change Mask"]
126    #[inline(always)]
127    pub fn riic(&self) -> RIIC_R {
128        RIIC_R::new(((self.bits >> 16) & 1) != 0)
129    }
130    #[doc = "Bit 17 - Data Set Ready Input Change Mask"]
131    #[inline(always)]
132    pub fn dsric(&self) -> DSRIC_R {
133        DSRIC_R::new(((self.bits >> 17) & 1) != 0)
134    }
135    #[doc = "Bit 18 - Data Carrier Detect Input Change Interrupt Mask"]
136    #[inline(always)]
137    pub fn dcdic(&self) -> DCDIC_R {
138        DCDIC_R::new(((self.bits >> 18) & 1) != 0)
139    }
140    #[doc = "Bit 19 - Clear to Send Input Change Interrupt Mask"]
141    #[inline(always)]
142    pub fn ctsic(&self) -> CTSIC_R {
143        CTSIC_R::new(((self.bits >> 19) & 1) != 0)
144    }
145    #[doc = "Bit 24 - Manchester Error Interrupt Mask"]
146    #[inline(always)]
147    pub fn mane(&self) -> MANE_R {
148        MANE_R::new(((self.bits >> 24) & 1) != 0)
149    }
150}
151#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"]
152pub struct IMR_SPEC;
153impl crate::RegisterSpec for IMR_SPEC {
154    type Ux = u32;
155}
156#[doc = "`read()` method returns [imr::R](R) reader structure"]
157impl crate::Readable for IMR_SPEC {
158    type Reader = R;
159}
160#[doc = "`reset()` method sets IMR to value 0"]
161impl crate::Resettable for IMR_SPEC {
162    const RESET_VALUE: Self::Ux = 0;
163}
atsam4sa16b_pac/usart0/imr.rs

atsam4sa16b_pac/usart0/
imr.rs
