atsam4sa16b_pac/spi/
sr.rs1#[doc = "Register `SR` reader"]
2pub struct R(crate::R<SR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<SR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<SR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<SR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Field `RDRF` reader - Receive Data Register Full"]
17pub type RDRF_R = crate::BitReader<bool>;
18#[doc = "Field `TDRE` reader - Transmit Data Register Empty"]
19pub type TDRE_R = crate::BitReader<bool>;
20#[doc = "Field `MODF` reader - Mode Fault Error"]
21pub type MODF_R = crate::BitReader<bool>;
22#[doc = "Field `OVRES` reader - Overrun Error Status"]
23pub type OVRES_R = crate::BitReader<bool>;
24#[doc = "Field `ENDRX` reader - End of RX buffer"]
25pub type ENDRX_R = crate::BitReader<bool>;
26#[doc = "Field `ENDTX` reader - End of TX buffer"]
27pub type ENDTX_R = crate::BitReader<bool>;
28#[doc = "Field `RXBUFF` reader - RX Buffer Full"]
29pub type RXBUFF_R = crate::BitReader<bool>;
30#[doc = "Field `TXBUFE` reader - TX Buffer Empty"]
31pub type TXBUFE_R = crate::BitReader<bool>;
32#[doc = "Field `NSSR` reader - NSS Rising"]
33pub type NSSR_R = crate::BitReader<bool>;
34#[doc = "Field `TXEMPTY` reader - Transmission Registers Empty"]
35pub type TXEMPTY_R = crate::BitReader<bool>;
36#[doc = "Field `UNDES` reader - Underrun Error Status (Slave mode Only)"]
37pub type UNDES_R = crate::BitReader<bool>;
38#[doc = "Field `SPIENS` reader - SPI Enable Status"]
39pub type SPIENS_R = crate::BitReader<bool>;
40impl R {
41 #[doc = "Bit 0 - Receive Data Register Full"]
42 #[inline(always)]
43 pub fn rdrf(&self) -> RDRF_R {
44 RDRF_R::new((self.bits & 1) != 0)
45 }
46 #[doc = "Bit 1 - Transmit Data Register Empty"]
47 #[inline(always)]
48 pub fn tdre(&self) -> TDRE_R {
49 TDRE_R::new(((self.bits >> 1) & 1) != 0)
50 }
51 #[doc = "Bit 2 - Mode Fault Error"]
52 #[inline(always)]
53 pub fn modf(&self) -> MODF_R {
54 MODF_R::new(((self.bits >> 2) & 1) != 0)
55 }
56 #[doc = "Bit 3 - Overrun Error Status"]
57 #[inline(always)]
58 pub fn ovres(&self) -> OVRES_R {
59 OVRES_R::new(((self.bits >> 3) & 1) != 0)
60 }
61 #[doc = "Bit 4 - End of RX buffer"]
62 #[inline(always)]
63 pub fn endrx(&self) -> ENDRX_R {
64 ENDRX_R::new(((self.bits >> 4) & 1) != 0)
65 }
66 #[doc = "Bit 5 - End of TX buffer"]
67 #[inline(always)]
68 pub fn endtx(&self) -> ENDTX_R {
69 ENDTX_R::new(((self.bits >> 5) & 1) != 0)
70 }
71 #[doc = "Bit 6 - RX Buffer Full"]
72 #[inline(always)]
73 pub fn rxbuff(&self) -> RXBUFF_R {
74 RXBUFF_R::new(((self.bits >> 6) & 1) != 0)
75 }
76 #[doc = "Bit 7 - TX Buffer Empty"]
77 #[inline(always)]
78 pub fn txbufe(&self) -> TXBUFE_R {
79 TXBUFE_R::new(((self.bits >> 7) & 1) != 0)
80 }
81 #[doc = "Bit 8 - NSS Rising"]
82 #[inline(always)]
83 pub fn nssr(&self) -> NSSR_R {
84 NSSR_R::new(((self.bits >> 8) & 1) != 0)
85 }
86 #[doc = "Bit 9 - Transmission Registers Empty"]
87 #[inline(always)]
88 pub fn txempty(&self) -> TXEMPTY_R {
89 TXEMPTY_R::new(((self.bits >> 9) & 1) != 0)
90 }
91 #[doc = "Bit 10 - Underrun Error Status (Slave mode Only)"]
92 #[inline(always)]
93 pub fn undes(&self) -> UNDES_R {
94 UNDES_R::new(((self.bits >> 10) & 1) != 0)
95 }
96 #[doc = "Bit 16 - SPI Enable Status"]
97 #[inline(always)]
98 pub fn spiens(&self) -> SPIENS_R {
99 SPIENS_R::new(((self.bits >> 16) & 1) != 0)
100 }
101}
102#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"]
103pub struct SR_SPEC;
104impl crate::RegisterSpec for SR_SPEC {
105 type Ux = u32;
106}
107#[doc = "`read()` method returns [sr::R](R) reader structure"]
108impl crate::Readable for SR_SPEC {
109 type Reader = R;
110}
111#[doc = "`reset()` method sets SR to value 0xf0"]
112impl crate::Resettable for SR_SPEC {
113 const RESET_VALUE: Self::Ux = 0xf0;
114}