atsam4s8c_pac/adc/
mr.rs

1#[doc = "Register `MR` reader"]
2pub struct R(crate::R<MR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MR` writer"]
17pub struct W(crate::W<MR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TRGEN` reader - Trigger Enable"]
38pub type TRGEN_R = crate::BitReader<TRGEN_A>;
39#[doc = "Trigger Enable\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum TRGEN_A {
42    #[doc = "0: Hardware triggers are disabled. Starting a conversion is only possible by software."]
43    DIS = 0,
44    #[doc = "1: Hardware trigger selected by TRGSEL field is enabled."]
45    EN = 1,
46}
47impl From<TRGEN_A> for bool {
48    #[inline(always)]
49    fn from(variant: TRGEN_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl TRGEN_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> TRGEN_A {
57        match self.bits {
58            false => TRGEN_A::DIS,
59            true => TRGEN_A::EN,
60        }
61    }
62    #[doc = "Checks if the value of the field is `DIS`"]
63    #[inline(always)]
64    pub fn is_dis(&self) -> bool {
65        *self == TRGEN_A::DIS
66    }
67    #[doc = "Checks if the value of the field is `EN`"]
68    #[inline(always)]
69    pub fn is_en(&self) -> bool {
70        *self == TRGEN_A::EN
71    }
72}
73#[doc = "Field `TRGEN` writer - Trigger Enable"]
74pub type TRGEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, TRGEN_A, O>;
75impl<'a, const O: u8> TRGEN_W<'a, O> {
76    #[doc = "Hardware triggers are disabled. Starting a conversion is only possible by software."]
77    #[inline(always)]
78    pub fn dis(self) -> &'a mut W {
79        self.variant(TRGEN_A::DIS)
80    }
81    #[doc = "Hardware trigger selected by TRGSEL field is enabled."]
82    #[inline(always)]
83    pub fn en(self) -> &'a mut W {
84        self.variant(TRGEN_A::EN)
85    }
86}
87#[doc = "Field `TRGSEL` reader - Trigger Selection"]
88pub type TRGSEL_R = crate::FieldReader<u8, TRGSEL_A>;
89#[doc = "Trigger Selection\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91#[repr(u8)]
92pub enum TRGSEL_A {
93    #[doc = "0: External trigger"]
94    ADC_TRIG0 = 0,
95    #[doc = "1: TIO Output of the Timer Counter Channel 0"]
96    ADC_TRIG1 = 1,
97    #[doc = "2: TIO Output of the Timer Counter Channel 1"]
98    ADC_TRIG2 = 2,
99    #[doc = "3: TIO Output of the Timer Counter Channel 2"]
100    ADC_TRIG3 = 3,
101    #[doc = "4: PWM Event Line 0"]
102    ADC_TRIG4 = 4,
103    #[doc = "5: PWM Event Line 1"]
104    ADC_TRIG5 = 5,
105}
106impl From<TRGSEL_A> for u8 {
107    #[inline(always)]
108    fn from(variant: TRGSEL_A) -> Self {
109        variant as _
110    }
111}
112impl TRGSEL_R {
113    #[doc = "Get enumerated values variant"]
114    #[inline(always)]
115    pub fn variant(&self) -> Option<TRGSEL_A> {
116        match self.bits {
117            0 => Some(TRGSEL_A::ADC_TRIG0),
118            1 => Some(TRGSEL_A::ADC_TRIG1),
119            2 => Some(TRGSEL_A::ADC_TRIG2),
120            3 => Some(TRGSEL_A::ADC_TRIG3),
121            4 => Some(TRGSEL_A::ADC_TRIG4),
122            5 => Some(TRGSEL_A::ADC_TRIG5),
123            _ => None,
124        }
125    }
126    #[doc = "Checks if the value of the field is `ADC_TRIG0`"]
127    #[inline(always)]
128    pub fn is_adc_trig0(&self) -> bool {
129        *self == TRGSEL_A::ADC_TRIG0
130    }
131    #[doc = "Checks if the value of the field is `ADC_TRIG1`"]
132    #[inline(always)]
133    pub fn is_adc_trig1(&self) -> bool {
134        *self == TRGSEL_A::ADC_TRIG1
135    }
136    #[doc = "Checks if the value of the field is `ADC_TRIG2`"]
137    #[inline(always)]
138    pub fn is_adc_trig2(&self) -> bool {
139        *self == TRGSEL_A::ADC_TRIG2
140    }
141    #[doc = "Checks if the value of the field is `ADC_TRIG3`"]
142    #[inline(always)]
143    pub fn is_adc_trig3(&self) -> bool {
144        *self == TRGSEL_A::ADC_TRIG3
145    }
146    #[doc = "Checks if the value of the field is `ADC_TRIG4`"]
147    #[inline(always)]
148    pub fn is_adc_trig4(&self) -> bool {
149        *self == TRGSEL_A::ADC_TRIG4
150    }
151    #[doc = "Checks if the value of the field is `ADC_TRIG5`"]
152    #[inline(always)]
153    pub fn is_adc_trig5(&self) -> bool {
154        *self == TRGSEL_A::ADC_TRIG5
155    }
156}
157#[doc = "Field `TRGSEL` writer - Trigger Selection"]
158pub type TRGSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MR_SPEC, u8, TRGSEL_A, 3, O>;
159impl<'a, const O: u8> TRGSEL_W<'a, O> {
160    #[doc = "External trigger"]
161    #[inline(always)]
162    pub fn adc_trig0(self) -> &'a mut W {
163        self.variant(TRGSEL_A::ADC_TRIG0)
164    }
165    #[doc = "TIO Output of the Timer Counter Channel 0"]
166    #[inline(always)]
167    pub fn adc_trig1(self) -> &'a mut W {
168        self.variant(TRGSEL_A::ADC_TRIG1)
169    }
170    #[doc = "TIO Output of the Timer Counter Channel 1"]
171    #[inline(always)]
172    pub fn adc_trig2(self) -> &'a mut W {
173        self.variant(TRGSEL_A::ADC_TRIG2)
174    }
175    #[doc = "TIO Output of the Timer Counter Channel 2"]
176    #[inline(always)]
177    pub fn adc_trig3(self) -> &'a mut W {
178        self.variant(TRGSEL_A::ADC_TRIG3)
179    }
180    #[doc = "PWM Event Line 0"]
181    #[inline(always)]
182    pub fn adc_trig4(self) -> &'a mut W {
183        self.variant(TRGSEL_A::ADC_TRIG4)
184    }
185    #[doc = "PWM Event Line 1"]
186    #[inline(always)]
187    pub fn adc_trig5(self) -> &'a mut W {
188        self.variant(TRGSEL_A::ADC_TRIG5)
189    }
190}
191#[doc = "Field `SLEEP` reader - Sleep Mode"]
192pub type SLEEP_R = crate::BitReader<SLEEP_A>;
193#[doc = "Sleep Mode\n\nValue on reset: 0"]
194#[derive(Clone, Copy, Debug, PartialEq, Eq)]
195pub enum SLEEP_A {
196    #[doc = "0: Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions"]
197    NORMAL = 0,
198    #[doc = "1: Sleep Mode: The wake-up time can be modified by programming FWUP bit"]
199    SLEEP = 1,
200}
201impl From<SLEEP_A> for bool {
202    #[inline(always)]
203    fn from(variant: SLEEP_A) -> Self {
204        variant as u8 != 0
205    }
206}
207impl SLEEP_R {
208    #[doc = "Get enumerated values variant"]
209    #[inline(always)]
210    pub fn variant(&self) -> SLEEP_A {
211        match self.bits {
212            false => SLEEP_A::NORMAL,
213            true => SLEEP_A::SLEEP,
214        }
215    }
216    #[doc = "Checks if the value of the field is `NORMAL`"]
217    #[inline(always)]
218    pub fn is_normal(&self) -> bool {
219        *self == SLEEP_A::NORMAL
220    }
221    #[doc = "Checks if the value of the field is `SLEEP`"]
222    #[inline(always)]
223    pub fn is_sleep(&self) -> bool {
224        *self == SLEEP_A::SLEEP
225    }
226}
227#[doc = "Field `SLEEP` writer - Sleep Mode"]
228pub type SLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, SLEEP_A, O>;
229impl<'a, const O: u8> SLEEP_W<'a, O> {
230    #[doc = "Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions"]
231    #[inline(always)]
232    pub fn normal(self) -> &'a mut W {
233        self.variant(SLEEP_A::NORMAL)
234    }
235    #[doc = "Sleep Mode: The wake-up time can be modified by programming FWUP bit"]
236    #[inline(always)]
237    pub fn sleep(self) -> &'a mut W {
238        self.variant(SLEEP_A::SLEEP)
239    }
240}
241#[doc = "Field `FWUP` reader - Fast Wake Up"]
242pub type FWUP_R = crate::BitReader<FWUP_A>;
243#[doc = "Fast Wake Up\n\nValue on reset: 0"]
244#[derive(Clone, Copy, Debug, PartialEq, Eq)]
245pub enum FWUP_A {
246    #[doc = "0: If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions"]
247    OFF = 0,
248    #[doc = "1: If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF"]
249    ON = 1,
250}
251impl From<FWUP_A> for bool {
252    #[inline(always)]
253    fn from(variant: FWUP_A) -> Self {
254        variant as u8 != 0
255    }
256}
257impl FWUP_R {
258    #[doc = "Get enumerated values variant"]
259    #[inline(always)]
260    pub fn variant(&self) -> FWUP_A {
261        match self.bits {
262            false => FWUP_A::OFF,
263            true => FWUP_A::ON,
264        }
265    }
266    #[doc = "Checks if the value of the field is `OFF`"]
267    #[inline(always)]
268    pub fn is_off(&self) -> bool {
269        *self == FWUP_A::OFF
270    }
271    #[doc = "Checks if the value of the field is `ON`"]
272    #[inline(always)]
273    pub fn is_on(&self) -> bool {
274        *self == FWUP_A::ON
275    }
276}
277#[doc = "Field `FWUP` writer - Fast Wake Up"]
278pub type FWUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, FWUP_A, O>;
279impl<'a, const O: u8> FWUP_W<'a, O> {
280    #[doc = "If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions"]
281    #[inline(always)]
282    pub fn off(self) -> &'a mut W {
283        self.variant(FWUP_A::OFF)
284    }
285    #[doc = "If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF"]
286    #[inline(always)]
287    pub fn on(self) -> &'a mut W {
288        self.variant(FWUP_A::ON)
289    }
290}
291#[doc = "Field `FREERUN` reader - Free Run Mode"]
292pub type FREERUN_R = crate::BitReader<FREERUN_A>;
293#[doc = "Free Run Mode\n\nValue on reset: 0"]
294#[derive(Clone, Copy, Debug, PartialEq, Eq)]
295pub enum FREERUN_A {
296    #[doc = "0: Normal Mode"]
297    OFF = 0,
298    #[doc = "1: Free Run Mode: Never wait for any trigger."]
299    ON = 1,
300}
301impl From<FREERUN_A> for bool {
302    #[inline(always)]
303    fn from(variant: FREERUN_A) -> Self {
304        variant as u8 != 0
305    }
306}
307impl FREERUN_R {
308    #[doc = "Get enumerated values variant"]
309    #[inline(always)]
310    pub fn variant(&self) -> FREERUN_A {
311        match self.bits {
312            false => FREERUN_A::OFF,
313            true => FREERUN_A::ON,
314        }
315    }
316    #[doc = "Checks if the value of the field is `OFF`"]
317    #[inline(always)]
318    pub fn is_off(&self) -> bool {
319        *self == FREERUN_A::OFF
320    }
321    #[doc = "Checks if the value of the field is `ON`"]
322    #[inline(always)]
323    pub fn is_on(&self) -> bool {
324        *self == FREERUN_A::ON
325    }
326}
327#[doc = "Field `FREERUN` writer - Free Run Mode"]
328pub type FREERUN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, FREERUN_A, O>;
329impl<'a, const O: u8> FREERUN_W<'a, O> {
330    #[doc = "Normal Mode"]
331    #[inline(always)]
332    pub fn off(self) -> &'a mut W {
333        self.variant(FREERUN_A::OFF)
334    }
335    #[doc = "Free Run Mode: Never wait for any trigger."]
336    #[inline(always)]
337    pub fn on(self) -> &'a mut W {
338        self.variant(FREERUN_A::ON)
339    }
340}
341#[doc = "Field `PRESCAL` reader - Prescaler Rate Selection"]
342pub type PRESCAL_R = crate::FieldReader<u8, u8>;
343#[doc = "Field `PRESCAL` writer - Prescaler Rate Selection"]
344pub type PRESCAL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MR_SPEC, u8, u8, 8, O>;
345#[doc = "Field `STARTUP` reader - Start Up Time"]
346pub type STARTUP_R = crate::FieldReader<u8, STARTUP_A>;
347#[doc = "Start Up Time\n\nValue on reset: 0"]
348#[derive(Clone, Copy, Debug, PartialEq, Eq)]
349#[repr(u8)]
350pub enum STARTUP_A {
351    #[doc = "0: 0 periods of ADCClock"]
352    SUT0 = 0,
353    #[doc = "1: 8 periods of ADCClock"]
354    SUT8 = 1,
355    #[doc = "2: 16 periods of ADCClock"]
356    SUT16 = 2,
357    #[doc = "3: 24 periods of ADCClock"]
358    SUT24 = 3,
359    #[doc = "4: 64 periods of ADCClock"]
360    SUT64 = 4,
361    #[doc = "5: 80 periods of ADCClock"]
362    SUT80 = 5,
363    #[doc = "6: 96 periods of ADCClock"]
364    SUT96 = 6,
365    #[doc = "7: 112 periods of ADCClock"]
366    SUT112 = 7,
367    #[doc = "8: 512 periods of ADCClock"]
368    SUT512 = 8,
369    #[doc = "9: 576 periods of ADCClock"]
370    SUT576 = 9,
371    #[doc = "10: 640 periods of ADCClock"]
372    SUT640 = 10,
373    #[doc = "11: 704 periods of ADCClock"]
374    SUT704 = 11,
375    #[doc = "12: 768 periods of ADCClock"]
376    SUT768 = 12,
377    #[doc = "13: 832 periods of ADCClock"]
378    SUT832 = 13,
379    #[doc = "14: 896 periods of ADCClock"]
380    SUT896 = 14,
381    #[doc = "15: 960 periods of ADCClock"]
382    SUT960 = 15,
383}
384impl From<STARTUP_A> for u8 {
385    #[inline(always)]
386    fn from(variant: STARTUP_A) -> Self {
387        variant as _
388    }
389}
390impl STARTUP_R {
391    #[doc = "Get enumerated values variant"]
392    #[inline(always)]
393    pub fn variant(&self) -> STARTUP_A {
394        match self.bits {
395            0 => STARTUP_A::SUT0,
396            1 => STARTUP_A::SUT8,
397            2 => STARTUP_A::SUT16,
398            3 => STARTUP_A::SUT24,
399            4 => STARTUP_A::SUT64,
400            5 => STARTUP_A::SUT80,
401            6 => STARTUP_A::SUT96,
402            7 => STARTUP_A::SUT112,
403            8 => STARTUP_A::SUT512,
404            9 => STARTUP_A::SUT576,
405            10 => STARTUP_A::SUT640,
406            11 => STARTUP_A::SUT704,
407            12 => STARTUP_A::SUT768,
408            13 => STARTUP_A::SUT832,
409            14 => STARTUP_A::SUT896,
410            15 => STARTUP_A::SUT960,
411            _ => unreachable!(),
412        }
413    }
414    #[doc = "Checks if the value of the field is `SUT0`"]
415    #[inline(always)]
416    pub fn is_sut0(&self) -> bool {
417        *self == STARTUP_A::SUT0
418    }
419    #[doc = "Checks if the value of the field is `SUT8`"]
420    #[inline(always)]
421    pub fn is_sut8(&self) -> bool {
422        *self == STARTUP_A::SUT8
423    }
424    #[doc = "Checks if the value of the field is `SUT16`"]
425    #[inline(always)]
426    pub fn is_sut16(&self) -> bool {
427        *self == STARTUP_A::SUT16
428    }
429    #[doc = "Checks if the value of the field is `SUT24`"]
430    #[inline(always)]
431    pub fn is_sut24(&self) -> bool {
432        *self == STARTUP_A::SUT24
433    }
434    #[doc = "Checks if the value of the field is `SUT64`"]
435    #[inline(always)]
436    pub fn is_sut64(&self) -> bool {
437        *self == STARTUP_A::SUT64
438    }
439    #[doc = "Checks if the value of the field is `SUT80`"]
440    #[inline(always)]
441    pub fn is_sut80(&self) -> bool {
442        *self == STARTUP_A::SUT80
443    }
444    #[doc = "Checks if the value of the field is `SUT96`"]
445    #[inline(always)]
446    pub fn is_sut96(&self) -> bool {
447        *self == STARTUP_A::SUT96
448    }
449    #[doc = "Checks if the value of the field is `SUT112`"]
450    #[inline(always)]
451    pub fn is_sut112(&self) -> bool {
452        *self == STARTUP_A::SUT112
453    }
454    #[doc = "Checks if the value of the field is `SUT512`"]
455    #[inline(always)]
456    pub fn is_sut512(&self) -> bool {
457        *self == STARTUP_A::SUT512
458    }
459    #[doc = "Checks if the value of the field is `SUT576`"]
460    #[inline(always)]
461    pub fn is_sut576(&self) -> bool {
462        *self == STARTUP_A::SUT576
463    }
464    #[doc = "Checks if the value of the field is `SUT640`"]
465    #[inline(always)]
466    pub fn is_sut640(&self) -> bool {
467        *self == STARTUP_A::SUT640
468    }
469    #[doc = "Checks if the value of the field is `SUT704`"]
470    #[inline(always)]
471    pub fn is_sut704(&self) -> bool {
472        *self == STARTUP_A::SUT704
473    }
474    #[doc = "Checks if the value of the field is `SUT768`"]
475    #[inline(always)]
476    pub fn is_sut768(&self) -> bool {
477        *self == STARTUP_A::SUT768
478    }
479    #[doc = "Checks if the value of the field is `SUT832`"]
480    #[inline(always)]
481    pub fn is_sut832(&self) -> bool {
482        *self == STARTUP_A::SUT832
483    }
484    #[doc = "Checks if the value of the field is `SUT896`"]
485    #[inline(always)]
486    pub fn is_sut896(&self) -> bool {
487        *self == STARTUP_A::SUT896
488    }
489    #[doc = "Checks if the value of the field is `SUT960`"]
490    #[inline(always)]
491    pub fn is_sut960(&self) -> bool {
492        *self == STARTUP_A::SUT960
493    }
494}
495#[doc = "Field `STARTUP` writer - Start Up Time"]
496pub type STARTUP_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, MR_SPEC, u8, STARTUP_A, 4, O>;
497impl<'a, const O: u8> STARTUP_W<'a, O> {
498    #[doc = "0 periods of ADCClock"]
499    #[inline(always)]
500    pub fn sut0(self) -> &'a mut W {
501        self.variant(STARTUP_A::SUT0)
502    }
503    #[doc = "8 periods of ADCClock"]
504    #[inline(always)]
505    pub fn sut8(self) -> &'a mut W {
506        self.variant(STARTUP_A::SUT8)
507    }
508    #[doc = "16 periods of ADCClock"]
509    #[inline(always)]
510    pub fn sut16(self) -> &'a mut W {
511        self.variant(STARTUP_A::SUT16)
512    }
513    #[doc = "24 periods of ADCClock"]
514    #[inline(always)]
515    pub fn sut24(self) -> &'a mut W {
516        self.variant(STARTUP_A::SUT24)
517    }
518    #[doc = "64 periods of ADCClock"]
519    #[inline(always)]
520    pub fn sut64(self) -> &'a mut W {
521        self.variant(STARTUP_A::SUT64)
522    }
523    #[doc = "80 periods of ADCClock"]
524    #[inline(always)]
525    pub fn sut80(self) -> &'a mut W {
526        self.variant(STARTUP_A::SUT80)
527    }
528    #[doc = "96 periods of ADCClock"]
529    #[inline(always)]
530    pub fn sut96(self) -> &'a mut W {
531        self.variant(STARTUP_A::SUT96)
532    }
533    #[doc = "112 periods of ADCClock"]
534    #[inline(always)]
535    pub fn sut112(self) -> &'a mut W {
536        self.variant(STARTUP_A::SUT112)
537    }
538    #[doc = "512 periods of ADCClock"]
539    #[inline(always)]
540    pub fn sut512(self) -> &'a mut W {
541        self.variant(STARTUP_A::SUT512)
542    }
543    #[doc = "576 periods of ADCClock"]
544    #[inline(always)]
545    pub fn sut576(self) -> &'a mut W {
546        self.variant(STARTUP_A::SUT576)
547    }
548    #[doc = "640 periods of ADCClock"]
549    #[inline(always)]
550    pub fn sut640(self) -> &'a mut W {
551        self.variant(STARTUP_A::SUT640)
552    }
553    #[doc = "704 periods of ADCClock"]
554    #[inline(always)]
555    pub fn sut704(self) -> &'a mut W {
556        self.variant(STARTUP_A::SUT704)
557    }
558    #[doc = "768 periods of ADCClock"]
559    #[inline(always)]
560    pub fn sut768(self) -> &'a mut W {
561        self.variant(STARTUP_A::SUT768)
562    }
563    #[doc = "832 periods of ADCClock"]
564    #[inline(always)]
565    pub fn sut832(self) -> &'a mut W {
566        self.variant(STARTUP_A::SUT832)
567    }
568    #[doc = "896 periods of ADCClock"]
569    #[inline(always)]
570    pub fn sut896(self) -> &'a mut W {
571        self.variant(STARTUP_A::SUT896)
572    }
573    #[doc = "960 periods of ADCClock"]
574    #[inline(always)]
575    pub fn sut960(self) -> &'a mut W {
576        self.variant(STARTUP_A::SUT960)
577    }
578}
579#[doc = "Field `SETTLING` reader - Analog Settling Time"]
580pub type SETTLING_R = crate::FieldReader<u8, SETTLING_A>;
581#[doc = "Analog Settling Time\n\nValue on reset: 0"]
582#[derive(Clone, Copy, Debug, PartialEq, Eq)]
583#[repr(u8)]
584pub enum SETTLING_A {
585    #[doc = "0: 3 periods of ADCClock"]
586    AST3 = 0,
587    #[doc = "1: 5 periods of ADCClock"]
588    AST5 = 1,
589    #[doc = "2: 9 periods of ADCClock"]
590    AST9 = 2,
591    #[doc = "3: 17 periods of ADCClock"]
592    AST17 = 3,
593}
594impl From<SETTLING_A> for u8 {
595    #[inline(always)]
596    fn from(variant: SETTLING_A) -> Self {
597        variant as _
598    }
599}
600impl SETTLING_R {
601    #[doc = "Get enumerated values variant"]
602    #[inline(always)]
603    pub fn variant(&self) -> SETTLING_A {
604        match self.bits {
605            0 => SETTLING_A::AST3,
606            1 => SETTLING_A::AST5,
607            2 => SETTLING_A::AST9,
608            3 => SETTLING_A::AST17,
609            _ => unreachable!(),
610        }
611    }
612    #[doc = "Checks if the value of the field is `AST3`"]
613    #[inline(always)]
614    pub fn is_ast3(&self) -> bool {
615        *self == SETTLING_A::AST3
616    }
617    #[doc = "Checks if the value of the field is `AST5`"]
618    #[inline(always)]
619    pub fn is_ast5(&self) -> bool {
620        *self == SETTLING_A::AST5
621    }
622    #[doc = "Checks if the value of the field is `AST9`"]
623    #[inline(always)]
624    pub fn is_ast9(&self) -> bool {
625        *self == SETTLING_A::AST9
626    }
627    #[doc = "Checks if the value of the field is `AST17`"]
628    #[inline(always)]
629    pub fn is_ast17(&self) -> bool {
630        *self == SETTLING_A::AST17
631    }
632}
633#[doc = "Field `SETTLING` writer - Analog Settling Time"]
634pub type SETTLING_W<'a, const O: u8> =
635    crate::FieldWriterSafe<'a, u32, MR_SPEC, u8, SETTLING_A, 2, O>;
636impl<'a, const O: u8> SETTLING_W<'a, O> {
637    #[doc = "3 periods of ADCClock"]
638    #[inline(always)]
639    pub fn ast3(self) -> &'a mut W {
640        self.variant(SETTLING_A::AST3)
641    }
642    #[doc = "5 periods of ADCClock"]
643    #[inline(always)]
644    pub fn ast5(self) -> &'a mut W {
645        self.variant(SETTLING_A::AST5)
646    }
647    #[doc = "9 periods of ADCClock"]
648    #[inline(always)]
649    pub fn ast9(self) -> &'a mut W {
650        self.variant(SETTLING_A::AST9)
651    }
652    #[doc = "17 periods of ADCClock"]
653    #[inline(always)]
654    pub fn ast17(self) -> &'a mut W {
655        self.variant(SETTLING_A::AST17)
656    }
657}
658#[doc = "Field `ANACH` reader - Analog Change"]
659pub type ANACH_R = crate::BitReader<ANACH_A>;
660#[doc = "Analog Change\n\nValue on reset: 0"]
661#[derive(Clone, Copy, Debug, PartialEq, Eq)]
662pub enum ANACH_A {
663    #[doc = "0: No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels"]
664    NONE = 0,
665    #[doc = "1: Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers"]
666    ALLOWED = 1,
667}
668impl From<ANACH_A> for bool {
669    #[inline(always)]
670    fn from(variant: ANACH_A) -> Self {
671        variant as u8 != 0
672    }
673}
674impl ANACH_R {
675    #[doc = "Get enumerated values variant"]
676    #[inline(always)]
677    pub fn variant(&self) -> ANACH_A {
678        match self.bits {
679            false => ANACH_A::NONE,
680            true => ANACH_A::ALLOWED,
681        }
682    }
683    #[doc = "Checks if the value of the field is `NONE`"]
684    #[inline(always)]
685    pub fn is_none(&self) -> bool {
686        *self == ANACH_A::NONE
687    }
688    #[doc = "Checks if the value of the field is `ALLOWED`"]
689    #[inline(always)]
690    pub fn is_allowed(&self) -> bool {
691        *self == ANACH_A::ALLOWED
692    }
693}
694#[doc = "Field `ANACH` writer - Analog Change"]
695pub type ANACH_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, ANACH_A, O>;
696impl<'a, const O: u8> ANACH_W<'a, O> {
697    #[doc = "No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels"]
698    #[inline(always)]
699    pub fn none(self) -> &'a mut W {
700        self.variant(ANACH_A::NONE)
701    }
702    #[doc = "Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers"]
703    #[inline(always)]
704    pub fn allowed(self) -> &'a mut W {
705        self.variant(ANACH_A::ALLOWED)
706    }
707}
708#[doc = "Field `TRACKTIM` reader - Tracking Time"]
709pub type TRACKTIM_R = crate::FieldReader<u8, u8>;
710#[doc = "Field `TRACKTIM` writer - Tracking Time"]
711pub type TRACKTIM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MR_SPEC, u8, u8, 4, O>;
712#[doc = "Field `TRANSFER` reader - Transfer Period"]
713pub type TRANSFER_R = crate::FieldReader<u8, u8>;
714#[doc = "Field `TRANSFER` writer - Transfer Period"]
715pub type TRANSFER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MR_SPEC, u8, u8, 2, O>;
716#[doc = "Field `USEQ` reader - Use Sequence Enable"]
717pub type USEQ_R = crate::BitReader<USEQ_A>;
718#[doc = "Use Sequence Enable\n\nValue on reset: 0"]
719#[derive(Clone, Copy, Debug, PartialEq, Eq)]
720pub enum USEQ_A {
721    #[doc = "0: Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index."]
722    NUM_ORDER = 0,
723    #[doc = "1: User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel."]
724    REG_ORDER = 1,
725}
726impl From<USEQ_A> for bool {
727    #[inline(always)]
728    fn from(variant: USEQ_A) -> Self {
729        variant as u8 != 0
730    }
731}
732impl USEQ_R {
733    #[doc = "Get enumerated values variant"]
734    #[inline(always)]
735    pub fn variant(&self) -> USEQ_A {
736        match self.bits {
737            false => USEQ_A::NUM_ORDER,
738            true => USEQ_A::REG_ORDER,
739        }
740    }
741    #[doc = "Checks if the value of the field is `NUM_ORDER`"]
742    #[inline(always)]
743    pub fn is_num_order(&self) -> bool {
744        *self == USEQ_A::NUM_ORDER
745    }
746    #[doc = "Checks if the value of the field is `REG_ORDER`"]
747    #[inline(always)]
748    pub fn is_reg_order(&self) -> bool {
749        *self == USEQ_A::REG_ORDER
750    }
751}
752#[doc = "Field `USEQ` writer - Use Sequence Enable"]
753pub type USEQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, USEQ_A, O>;
754impl<'a, const O: u8> USEQ_W<'a, O> {
755    #[doc = "Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index."]
756    #[inline(always)]
757    pub fn num_order(self) -> &'a mut W {
758        self.variant(USEQ_A::NUM_ORDER)
759    }
760    #[doc = "User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel."]
761    #[inline(always)]
762    pub fn reg_order(self) -> &'a mut W {
763        self.variant(USEQ_A::REG_ORDER)
764    }
765}
766impl R {
767    #[doc = "Bit 0 - Trigger Enable"]
768    #[inline(always)]
769    pub fn trgen(&self) -> TRGEN_R {
770        TRGEN_R::new((self.bits & 1) != 0)
771    }
772    #[doc = "Bits 1:3 - Trigger Selection"]
773    #[inline(always)]
774    pub fn trgsel(&self) -> TRGSEL_R {
775        TRGSEL_R::new(((self.bits >> 1) & 7) as u8)
776    }
777    #[doc = "Bit 5 - Sleep Mode"]
778    #[inline(always)]
779    pub fn sleep(&self) -> SLEEP_R {
780        SLEEP_R::new(((self.bits >> 5) & 1) != 0)
781    }
782    #[doc = "Bit 6 - Fast Wake Up"]
783    #[inline(always)]
784    pub fn fwup(&self) -> FWUP_R {
785        FWUP_R::new(((self.bits >> 6) & 1) != 0)
786    }
787    #[doc = "Bit 7 - Free Run Mode"]
788    #[inline(always)]
789    pub fn freerun(&self) -> FREERUN_R {
790        FREERUN_R::new(((self.bits >> 7) & 1) != 0)
791    }
792    #[doc = "Bits 8:15 - Prescaler Rate Selection"]
793    #[inline(always)]
794    pub fn prescal(&self) -> PRESCAL_R {
795        PRESCAL_R::new(((self.bits >> 8) & 0xff) as u8)
796    }
797    #[doc = "Bits 16:19 - Start Up Time"]
798    #[inline(always)]
799    pub fn startup(&self) -> STARTUP_R {
800        STARTUP_R::new(((self.bits >> 16) & 0x0f) as u8)
801    }
802    #[doc = "Bits 20:21 - Analog Settling Time"]
803    #[inline(always)]
804    pub fn settling(&self) -> SETTLING_R {
805        SETTLING_R::new(((self.bits >> 20) & 3) as u8)
806    }
807    #[doc = "Bit 23 - Analog Change"]
808    #[inline(always)]
809    pub fn anach(&self) -> ANACH_R {
810        ANACH_R::new(((self.bits >> 23) & 1) != 0)
811    }
812    #[doc = "Bits 24:27 - Tracking Time"]
813    #[inline(always)]
814    pub fn tracktim(&self) -> TRACKTIM_R {
815        TRACKTIM_R::new(((self.bits >> 24) & 0x0f) as u8)
816    }
817    #[doc = "Bits 28:29 - Transfer Period"]
818    #[inline(always)]
819    pub fn transfer(&self) -> TRANSFER_R {
820        TRANSFER_R::new(((self.bits >> 28) & 3) as u8)
821    }
822    #[doc = "Bit 31 - Use Sequence Enable"]
823    #[inline(always)]
824    pub fn useq(&self) -> USEQ_R {
825        USEQ_R::new(((self.bits >> 31) & 1) != 0)
826    }
827}
828impl W {
829    #[doc = "Bit 0 - Trigger Enable"]
830    #[inline(always)]
831    #[must_use]
832    pub fn trgen(&mut self) -> TRGEN_W<0> {
833        TRGEN_W::new(self)
834    }
835    #[doc = "Bits 1:3 - Trigger Selection"]
836    #[inline(always)]
837    #[must_use]
838    pub fn trgsel(&mut self) -> TRGSEL_W<1> {
839        TRGSEL_W::new(self)
840    }
841    #[doc = "Bit 5 - Sleep Mode"]
842    #[inline(always)]
843    #[must_use]
844    pub fn sleep(&mut self) -> SLEEP_W<5> {
845        SLEEP_W::new(self)
846    }
847    #[doc = "Bit 6 - Fast Wake Up"]
848    #[inline(always)]
849    #[must_use]
850    pub fn fwup(&mut self) -> FWUP_W<6> {
851        FWUP_W::new(self)
852    }
853    #[doc = "Bit 7 - Free Run Mode"]
854    #[inline(always)]
855    #[must_use]
856    pub fn freerun(&mut self) -> FREERUN_W<7> {
857        FREERUN_W::new(self)
858    }
859    #[doc = "Bits 8:15 - Prescaler Rate Selection"]
860    #[inline(always)]
861    #[must_use]
862    pub fn prescal(&mut self) -> PRESCAL_W<8> {
863        PRESCAL_W::new(self)
864    }
865    #[doc = "Bits 16:19 - Start Up Time"]
866    #[inline(always)]
867    #[must_use]
868    pub fn startup(&mut self) -> STARTUP_W<16> {
869        STARTUP_W::new(self)
870    }
871    #[doc = "Bits 20:21 - Analog Settling Time"]
872    #[inline(always)]
873    #[must_use]
874    pub fn settling(&mut self) -> SETTLING_W<20> {
875        SETTLING_W::new(self)
876    }
877    #[doc = "Bit 23 - Analog Change"]
878    #[inline(always)]
879    #[must_use]
880    pub fn anach(&mut self) -> ANACH_W<23> {
881        ANACH_W::new(self)
882    }
883    #[doc = "Bits 24:27 - Tracking Time"]
884    #[inline(always)]
885    #[must_use]
886    pub fn tracktim(&mut self) -> TRACKTIM_W<24> {
887        TRACKTIM_W::new(self)
888    }
889    #[doc = "Bits 28:29 - Transfer Period"]
890    #[inline(always)]
891    #[must_use]
892    pub fn transfer(&mut self) -> TRANSFER_W<28> {
893        TRANSFER_W::new(self)
894    }
895    #[doc = "Bit 31 - Use Sequence Enable"]
896    #[inline(always)]
897    #[must_use]
898    pub fn useq(&mut self) -> USEQ_W<31> {
899        USEQ_W::new(self)
900    }
901    #[doc = "Writes raw bits to the register."]
902    #[inline(always)]
903    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
904        self.0.bits(bits);
905        self
906    }
907}
908#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"]
909pub struct MR_SPEC;
910impl crate::RegisterSpec for MR_SPEC {
911    type Ux = u32;
912}
913#[doc = "`read()` method returns [mr::R](R) reader structure"]
914impl crate::Readable for MR_SPEC {
915    type Reader = R;
916}
917#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"]
918impl crate::Writable for MR_SPEC {
919    type Writer = W;
920    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
921    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
922}
923#[doc = "`reset()` method sets MR to value 0"]
924impl crate::Resettable for MR_SPEC {
925    const RESET_VALUE: Self::Ux = 0;
926}
atsam4s8c_pac/adc/mr.rs

atsam4s8c_pac/adc/
mr.rs
