atsam4s8b_pac/spi/
mr.rs

1#[doc = "Register `MR` reader"]
2pub struct R(crate::R<MR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MR` writer"]
17pub struct W(crate::W<MR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MSTR` reader - Master/Slave Mode"]
38pub type MSTR_R = crate::BitReader<bool>;
39#[doc = "Field `MSTR` writer - Master/Slave Mode"]
40pub type MSTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, bool, O>;
41#[doc = "Field `PS` reader - Peripheral Select"]
42pub type PS_R = crate::BitReader<bool>;
43#[doc = "Field `PS` writer - Peripheral Select"]
44pub type PS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, bool, O>;
45#[doc = "Field `PCSDEC` reader - Chip Select Decode"]
46pub type PCSDEC_R = crate::BitReader<bool>;
47#[doc = "Field `PCSDEC` writer - Chip Select Decode"]
48pub type PCSDEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, bool, O>;
49#[doc = "Field `MODFDIS` reader - Mode Fault Detection"]
50pub type MODFDIS_R = crate::BitReader<bool>;
51#[doc = "Field `MODFDIS` writer - Mode Fault Detection"]
52pub type MODFDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, bool, O>;
53#[doc = "Field `WDRBT` reader - Wait Data Read Before Transfer"]
54pub type WDRBT_R = crate::BitReader<bool>;
55#[doc = "Field `WDRBT` writer - Wait Data Read Before Transfer"]
56pub type WDRBT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, bool, O>;
57#[doc = "Field `LLB` reader - Local Loopback Enable"]
58pub type LLB_R = crate::BitReader<bool>;
59#[doc = "Field `LLB` writer - Local Loopback Enable"]
60pub type LLB_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, bool, O>;
61#[doc = "Field `PCS` reader - Peripheral Chip Select"]
62pub type PCS_R = crate::FieldReader<u8, u8>;
63#[doc = "Field `PCS` writer - Peripheral Chip Select"]
64pub type PCS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MR_SPEC, u8, u8, 4, O>;
65#[doc = "Field `DLYBCS` reader - Delay Between Chip Selects"]
66pub type DLYBCS_R = crate::FieldReader<u8, u8>;
67#[doc = "Field `DLYBCS` writer - Delay Between Chip Selects"]
68pub type DLYBCS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MR_SPEC, u8, u8, 8, O>;
69impl R {
70    #[doc = "Bit 0 - Master/Slave Mode"]
71    #[inline(always)]
72    pub fn mstr(&self) -> MSTR_R {
73        MSTR_R::new((self.bits & 1) != 0)
74    }
75    #[doc = "Bit 1 - Peripheral Select"]
76    #[inline(always)]
77    pub fn ps(&self) -> PS_R {
78        PS_R::new(((self.bits >> 1) & 1) != 0)
79    }
80    #[doc = "Bit 2 - Chip Select Decode"]
81    #[inline(always)]
82    pub fn pcsdec(&self) -> PCSDEC_R {
83        PCSDEC_R::new(((self.bits >> 2) & 1) != 0)
84    }
85    #[doc = "Bit 4 - Mode Fault Detection"]
86    #[inline(always)]
87    pub fn modfdis(&self) -> MODFDIS_R {
88        MODFDIS_R::new(((self.bits >> 4) & 1) != 0)
89    }
90    #[doc = "Bit 5 - Wait Data Read Before Transfer"]
91    #[inline(always)]
92    pub fn wdrbt(&self) -> WDRBT_R {
93        WDRBT_R::new(((self.bits >> 5) & 1) != 0)
94    }
95    #[doc = "Bit 7 - Local Loopback Enable"]
96    #[inline(always)]
97    pub fn llb(&self) -> LLB_R {
98        LLB_R::new(((self.bits >> 7) & 1) != 0)
99    }
100    #[doc = "Bits 16:19 - Peripheral Chip Select"]
101    #[inline(always)]
102    pub fn pcs(&self) -> PCS_R {
103        PCS_R::new(((self.bits >> 16) & 0x0f) as u8)
104    }
105    #[doc = "Bits 24:31 - Delay Between Chip Selects"]
106    #[inline(always)]
107    pub fn dlybcs(&self) -> DLYBCS_R {
108        DLYBCS_R::new(((self.bits >> 24) & 0xff) as u8)
109    }
110}
111impl W {
112    #[doc = "Bit 0 - Master/Slave Mode"]
113    #[inline(always)]
114    #[must_use]
115    pub fn mstr(&mut self) -> MSTR_W<0> {
116        MSTR_W::new(self)
117    }
118    #[doc = "Bit 1 - Peripheral Select"]
119    #[inline(always)]
120    #[must_use]
121    pub fn ps(&mut self) -> PS_W<1> {
122        PS_W::new(self)
123    }
124    #[doc = "Bit 2 - Chip Select Decode"]
125    #[inline(always)]
126    #[must_use]
127    pub fn pcsdec(&mut self) -> PCSDEC_W<2> {
128        PCSDEC_W::new(self)
129    }
130    #[doc = "Bit 4 - Mode Fault Detection"]
131    #[inline(always)]
132    #[must_use]
133    pub fn modfdis(&mut self) -> MODFDIS_W<4> {
134        MODFDIS_W::new(self)
135    }
136    #[doc = "Bit 5 - Wait Data Read Before Transfer"]
137    #[inline(always)]
138    #[must_use]
139    pub fn wdrbt(&mut self) -> WDRBT_W<5> {
140        WDRBT_W::new(self)
141    }
142    #[doc = "Bit 7 - Local Loopback Enable"]
143    #[inline(always)]
144    #[must_use]
145    pub fn llb(&mut self) -> LLB_W<7> {
146        LLB_W::new(self)
147    }
148    #[doc = "Bits 16:19 - Peripheral Chip Select"]
149    #[inline(always)]
150    #[must_use]
151    pub fn pcs(&mut self) -> PCS_W<16> {
152        PCS_W::new(self)
153    }
154    #[doc = "Bits 24:31 - Delay Between Chip Selects"]
155    #[inline(always)]
156    #[must_use]
157    pub fn dlybcs(&mut self) -> DLYBCS_W<24> {
158        DLYBCS_W::new(self)
159    }
160    #[doc = "Writes raw bits to the register."]
161    #[inline(always)]
162    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
163        self.0.bits(bits);
164        self
165    }
166}
167#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"]
168pub struct MR_SPEC;
169impl crate::RegisterSpec for MR_SPEC {
170    type Ux = u32;
171}
172#[doc = "`read()` method returns [mr::R](R) reader structure"]
173impl crate::Readable for MR_SPEC {
174    type Reader = R;
175}
176#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"]
177impl crate::Writable for MR_SPEC {
178    type Writer = W;
179    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
180    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
181}
182#[doc = "`reset()` method sets MR to value 0"]
183impl crate::Resettable for MR_SPEC {
184    const RESET_VALUE: Self::Ux = 0;
185}