atsam4s4c_pac/pwm/
cmr3.rs

1#[doc = "Register `CMR3` reader"]
2pub struct R(crate::R<CMR3_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CMR3_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CMR3_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CMR3_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CMR3` writer"]
17pub struct W(crate::W<CMR3_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CMR3_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CMR3_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CMR3_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CPRE` reader - Channel Pre-scaler"]
38pub type CPRE_R = crate::FieldReader<u8, CPRE_A>;
39#[doc = "Channel Pre-scaler\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CPRE_A {
43    #[doc = "0: Master clock"]
44    MCK = 0,
45    #[doc = "1: Master clock/2"]
46    MCK_DIV_2 = 1,
47    #[doc = "2: Master clock/4"]
48    MCK_DIV_4 = 2,
49    #[doc = "3: Master clock/8"]
50    MCK_DIV_8 = 3,
51    #[doc = "4: Master clock/16"]
52    MCK_DIV_16 = 4,
53    #[doc = "5: Master clock/32"]
54    MCK_DIV_32 = 5,
55    #[doc = "6: Master clock/64"]
56    MCK_DIV_64 = 6,
57    #[doc = "7: Master clock/128"]
58    MCK_DIV_128 = 7,
59    #[doc = "8: Master clock/256"]
60    MCK_DIV_256 = 8,
61    #[doc = "9: Master clock/512"]
62    MCK_DIV_512 = 9,
63    #[doc = "10: Master clock/1024"]
64    MCK_DIV_1024 = 10,
65    #[doc = "11: Clock A"]
66    CLKA = 11,
67    #[doc = "12: Clock B"]
68    CLKB = 12,
69}
70impl From<CPRE_A> for u8 {
71    #[inline(always)]
72    fn from(variant: CPRE_A) -> Self {
73        variant as _
74    }
75}
76impl CPRE_R {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub fn variant(&self) -> Option<CPRE_A> {
80        match self.bits {
81            0 => Some(CPRE_A::MCK),
82            1 => Some(CPRE_A::MCK_DIV_2),
83            2 => Some(CPRE_A::MCK_DIV_4),
84            3 => Some(CPRE_A::MCK_DIV_8),
85            4 => Some(CPRE_A::MCK_DIV_16),
86            5 => Some(CPRE_A::MCK_DIV_32),
87            6 => Some(CPRE_A::MCK_DIV_64),
88            7 => Some(CPRE_A::MCK_DIV_128),
89            8 => Some(CPRE_A::MCK_DIV_256),
90            9 => Some(CPRE_A::MCK_DIV_512),
91            10 => Some(CPRE_A::MCK_DIV_1024),
92            11 => Some(CPRE_A::CLKA),
93            12 => Some(CPRE_A::CLKB),
94            _ => None,
95        }
96    }
97    #[doc = "Checks if the value of the field is `MCK`"]
98    #[inline(always)]
99    pub fn is_mck(&self) -> bool {
100        *self == CPRE_A::MCK
101    }
102    #[doc = "Checks if the value of the field is `MCK_DIV_2`"]
103    #[inline(always)]
104    pub fn is_mck_div_2(&self) -> bool {
105        *self == CPRE_A::MCK_DIV_2
106    }
107    #[doc = "Checks if the value of the field is `MCK_DIV_4`"]
108    #[inline(always)]
109    pub fn is_mck_div_4(&self) -> bool {
110        *self == CPRE_A::MCK_DIV_4
111    }
112    #[doc = "Checks if the value of the field is `MCK_DIV_8`"]
113    #[inline(always)]
114    pub fn is_mck_div_8(&self) -> bool {
115        *self == CPRE_A::MCK_DIV_8
116    }
117    #[doc = "Checks if the value of the field is `MCK_DIV_16`"]
118    #[inline(always)]
119    pub fn is_mck_div_16(&self) -> bool {
120        *self == CPRE_A::MCK_DIV_16
121    }
122    #[doc = "Checks if the value of the field is `MCK_DIV_32`"]
123    #[inline(always)]
124    pub fn is_mck_div_32(&self) -> bool {
125        *self == CPRE_A::MCK_DIV_32
126    }
127    #[doc = "Checks if the value of the field is `MCK_DIV_64`"]
128    #[inline(always)]
129    pub fn is_mck_div_64(&self) -> bool {
130        *self == CPRE_A::MCK_DIV_64
131    }
132    #[doc = "Checks if the value of the field is `MCK_DIV_128`"]
133    #[inline(always)]
134    pub fn is_mck_div_128(&self) -> bool {
135        *self == CPRE_A::MCK_DIV_128
136    }
137    #[doc = "Checks if the value of the field is `MCK_DIV_256`"]
138    #[inline(always)]
139    pub fn is_mck_div_256(&self) -> bool {
140        *self == CPRE_A::MCK_DIV_256
141    }
142    #[doc = "Checks if the value of the field is `MCK_DIV_512`"]
143    #[inline(always)]
144    pub fn is_mck_div_512(&self) -> bool {
145        *self == CPRE_A::MCK_DIV_512
146    }
147    #[doc = "Checks if the value of the field is `MCK_DIV_1024`"]
148    #[inline(always)]
149    pub fn is_mck_div_1024(&self) -> bool {
150        *self == CPRE_A::MCK_DIV_1024
151    }
152    #[doc = "Checks if the value of the field is `CLKA`"]
153    #[inline(always)]
154    pub fn is_clka(&self) -> bool {
155        *self == CPRE_A::CLKA
156    }
157    #[doc = "Checks if the value of the field is `CLKB`"]
158    #[inline(always)]
159    pub fn is_clkb(&self) -> bool {
160        *self == CPRE_A::CLKB
161    }
162}
163#[doc = "Field `CPRE` writer - Channel Pre-scaler"]
164pub type CPRE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMR3_SPEC, u8, CPRE_A, 4, O>;
165impl<'a, const O: u8> CPRE_W<'a, O> {
166    #[doc = "Master clock"]
167    #[inline(always)]
168    pub fn mck(self) -> &'a mut W {
169        self.variant(CPRE_A::MCK)
170    }
171    #[doc = "Master clock/2"]
172    #[inline(always)]
173    pub fn mck_div_2(self) -> &'a mut W {
174        self.variant(CPRE_A::MCK_DIV_2)
175    }
176    #[doc = "Master clock/4"]
177    #[inline(always)]
178    pub fn mck_div_4(self) -> &'a mut W {
179        self.variant(CPRE_A::MCK_DIV_4)
180    }
181    #[doc = "Master clock/8"]
182    #[inline(always)]
183    pub fn mck_div_8(self) -> &'a mut W {
184        self.variant(CPRE_A::MCK_DIV_8)
185    }
186    #[doc = "Master clock/16"]
187    #[inline(always)]
188    pub fn mck_div_16(self) -> &'a mut W {
189        self.variant(CPRE_A::MCK_DIV_16)
190    }
191    #[doc = "Master clock/32"]
192    #[inline(always)]
193    pub fn mck_div_32(self) -> &'a mut W {
194        self.variant(CPRE_A::MCK_DIV_32)
195    }
196    #[doc = "Master clock/64"]
197    #[inline(always)]
198    pub fn mck_div_64(self) -> &'a mut W {
199        self.variant(CPRE_A::MCK_DIV_64)
200    }
201    #[doc = "Master clock/128"]
202    #[inline(always)]
203    pub fn mck_div_128(self) -> &'a mut W {
204        self.variant(CPRE_A::MCK_DIV_128)
205    }
206    #[doc = "Master clock/256"]
207    #[inline(always)]
208    pub fn mck_div_256(self) -> &'a mut W {
209        self.variant(CPRE_A::MCK_DIV_256)
210    }
211    #[doc = "Master clock/512"]
212    #[inline(always)]
213    pub fn mck_div_512(self) -> &'a mut W {
214        self.variant(CPRE_A::MCK_DIV_512)
215    }
216    #[doc = "Master clock/1024"]
217    #[inline(always)]
218    pub fn mck_div_1024(self) -> &'a mut W {
219        self.variant(CPRE_A::MCK_DIV_1024)
220    }
221    #[doc = "Clock A"]
222    #[inline(always)]
223    pub fn clka(self) -> &'a mut W {
224        self.variant(CPRE_A::CLKA)
225    }
226    #[doc = "Clock B"]
227    #[inline(always)]
228    pub fn clkb(self) -> &'a mut W {
229        self.variant(CPRE_A::CLKB)
230    }
231}
232#[doc = "Field `CALG` reader - Channel Alignment"]
233pub type CALG_R = crate::BitReader<bool>;
234#[doc = "Field `CALG` writer - Channel Alignment"]
235pub type CALG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMR3_SPEC, bool, O>;
236#[doc = "Field `CPOL` reader - Channel Polarity"]
237pub type CPOL_R = crate::BitReader<bool>;
238#[doc = "Field `CPOL` writer - Channel Polarity"]
239pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMR3_SPEC, bool, O>;
240#[doc = "Field `CES` reader - Counter Event Selection"]
241pub type CES_R = crate::BitReader<bool>;
242#[doc = "Field `CES` writer - Counter Event Selection"]
243pub type CES_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMR3_SPEC, bool, O>;
244#[doc = "Field `DTE` reader - Dead-Time Generator Enable"]
245pub type DTE_R = crate::BitReader<bool>;
246#[doc = "Field `DTE` writer - Dead-Time Generator Enable"]
247pub type DTE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMR3_SPEC, bool, O>;
248#[doc = "Field `DTHI` reader - Dead-Time PWMHx Output Inverted"]
249pub type DTHI_R = crate::BitReader<bool>;
250#[doc = "Field `DTHI` writer - Dead-Time PWMHx Output Inverted"]
251pub type DTHI_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMR3_SPEC, bool, O>;
252#[doc = "Field `DTLI` reader - Dead-Time PWMLx Output Inverted"]
253pub type DTLI_R = crate::BitReader<bool>;
254#[doc = "Field `DTLI` writer - Dead-Time PWMLx Output Inverted"]
255pub type DTLI_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMR3_SPEC, bool, O>;
256impl R {
257    #[doc = "Bits 0:3 - Channel Pre-scaler"]
258    #[inline(always)]
259    pub fn cpre(&self) -> CPRE_R {
260        CPRE_R::new((self.bits & 0x0f) as u8)
261    }
262    #[doc = "Bit 8 - Channel Alignment"]
263    #[inline(always)]
264    pub fn calg(&self) -> CALG_R {
265        CALG_R::new(((self.bits >> 8) & 1) != 0)
266    }
267    #[doc = "Bit 9 - Channel Polarity"]
268    #[inline(always)]
269    pub fn cpol(&self) -> CPOL_R {
270        CPOL_R::new(((self.bits >> 9) & 1) != 0)
271    }
272    #[doc = "Bit 10 - Counter Event Selection"]
273    #[inline(always)]
274    pub fn ces(&self) -> CES_R {
275        CES_R::new(((self.bits >> 10) & 1) != 0)
276    }
277    #[doc = "Bit 16 - Dead-Time Generator Enable"]
278    #[inline(always)]
279    pub fn dte(&self) -> DTE_R {
280        DTE_R::new(((self.bits >> 16) & 1) != 0)
281    }
282    #[doc = "Bit 17 - Dead-Time PWMHx Output Inverted"]
283    #[inline(always)]
284    pub fn dthi(&self) -> DTHI_R {
285        DTHI_R::new(((self.bits >> 17) & 1) != 0)
286    }
287    #[doc = "Bit 18 - Dead-Time PWMLx Output Inverted"]
288    #[inline(always)]
289    pub fn dtli(&self) -> DTLI_R {
290        DTLI_R::new(((self.bits >> 18) & 1) != 0)
291    }
292}
293impl W {
294    #[doc = "Bits 0:3 - Channel Pre-scaler"]
295    #[inline(always)]
296    #[must_use]
297    pub fn cpre(&mut self) -> CPRE_W<0> {
298        CPRE_W::new(self)
299    }
300    #[doc = "Bit 8 - Channel Alignment"]
301    #[inline(always)]
302    #[must_use]
303    pub fn calg(&mut self) -> CALG_W<8> {
304        CALG_W::new(self)
305    }
306    #[doc = "Bit 9 - Channel Polarity"]
307    #[inline(always)]
308    #[must_use]
309    pub fn cpol(&mut self) -> CPOL_W<9> {
310        CPOL_W::new(self)
311    }
312    #[doc = "Bit 10 - Counter Event Selection"]
313    #[inline(always)]
314    #[must_use]
315    pub fn ces(&mut self) -> CES_W<10> {
316        CES_W::new(self)
317    }
318    #[doc = "Bit 16 - Dead-Time Generator Enable"]
319    #[inline(always)]
320    #[must_use]
321    pub fn dte(&mut self) -> DTE_W<16> {
322        DTE_W::new(self)
323    }
324    #[doc = "Bit 17 - Dead-Time PWMHx Output Inverted"]
325    #[inline(always)]
326    #[must_use]
327    pub fn dthi(&mut self) -> DTHI_W<17> {
328        DTHI_W::new(self)
329    }
330    #[doc = "Bit 18 - Dead-Time PWMLx Output Inverted"]
331    #[inline(always)]
332    #[must_use]
333    pub fn dtli(&mut self) -> DTLI_W<18> {
334        DTLI_W::new(self)
335    }
336    #[doc = "Writes raw bits to the register."]
337    #[inline(always)]
338    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
339        self.0.bits(bits);
340        self
341    }
342}
343#[doc = "PWM Channel Mode Register (ch_num = 3)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmr3](index.html) module"]
344pub struct CMR3_SPEC;
345impl crate::RegisterSpec for CMR3_SPEC {
346    type Ux = u32;
347}
348#[doc = "`read()` method returns [cmr3::R](R) reader structure"]
349impl crate::Readable for CMR3_SPEC {
350    type Reader = R;
351}
352#[doc = "`write(|w| ..)` method takes [cmr3::W](W) writer structure"]
353impl crate::Writable for CMR3_SPEC {
354    type Writer = W;
355    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
356    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
357}
358#[doc = "`reset()` method sets CMR3 to value 0"]
359impl crate::Resettable for CMR3_SPEC {
360    const RESET_VALUE: Self::Ux = 0;
361}
atsam4s4c_pac/pwm/cmr3.rs

atsam4s4c_pac/pwm/
cmr3.rs
