atsam4s2c_pac/spi/
csr.rs

1#[doc = "Register `CSR[%s]` reader"]
2pub struct R(crate::R<CSR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CSR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CSR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CSR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CSR[%s]` writer"]
17pub struct W(crate::W<CSR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CSR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CSR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CSR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CPOL` reader - Clock Polarity"]
38pub type CPOL_R = crate::BitReader<bool>;
39#[doc = "Field `CPOL` writer - Clock Polarity"]
40pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
41#[doc = "Field `NCPHA` reader - Clock Phase"]
42pub type NCPHA_R = crate::BitReader<bool>;
43#[doc = "Field `NCPHA` writer - Clock Phase"]
44pub type NCPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
45#[doc = "Field `CSNAAT` reader - Chip Select Not Active After Transfer (Ignored if CSAAT = 1)"]
46pub type CSNAAT_R = crate::BitReader<bool>;
47#[doc = "Field `CSNAAT` writer - Chip Select Not Active After Transfer (Ignored if CSAAT = 1)"]
48pub type CSNAAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
49#[doc = "Field `CSAAT` reader - Chip Select Active After Transfer"]
50pub type CSAAT_R = crate::BitReader<bool>;
51#[doc = "Field `CSAAT` writer - Chip Select Active After Transfer"]
52pub type CSAAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
53#[doc = "Field `BITS` reader - Bits Per Transfer"]
54pub type BITS_R = crate::FieldReader<u8, BITS_A>;
55#[doc = "Bits Per Transfer"]
56#[derive(Clone, Copy, Debug, PartialEq, Eq)]
57#[repr(u8)]
58pub enum BITS_A {
59    #[doc = "0: 8 bits for transfer"]
60    _8_BIT = 0,
61    #[doc = "1: 9 bits for transfer"]
62    _9_BIT = 1,
63    #[doc = "2: 10 bits for transfer"]
64    _10_BIT = 2,
65    #[doc = "3: 11 bits for transfer"]
66    _11_BIT = 3,
67    #[doc = "4: 12 bits for transfer"]
68    _12_BIT = 4,
69    #[doc = "5: 13 bits for transfer"]
70    _13_BIT = 5,
71    #[doc = "6: 14 bits for transfer"]
72    _14_BIT = 6,
73    #[doc = "7: 15 bits for transfer"]
74    _15_BIT = 7,
75    #[doc = "8: 16 bits for transfer"]
76    _16_BIT = 8,
77}
78impl From<BITS_A> for u8 {
79    #[inline(always)]
80    fn from(variant: BITS_A) -> Self {
81        variant as _
82    }
83}
84impl BITS_R {
85    #[doc = "Get enumerated values variant"]
86    #[inline(always)]
87    pub fn variant(&self) -> Option<BITS_A> {
88        match self.bits {
89            0 => Some(BITS_A::_8_BIT),
90            1 => Some(BITS_A::_9_BIT),
91            2 => Some(BITS_A::_10_BIT),
92            3 => Some(BITS_A::_11_BIT),
93            4 => Some(BITS_A::_12_BIT),
94            5 => Some(BITS_A::_13_BIT),
95            6 => Some(BITS_A::_14_BIT),
96            7 => Some(BITS_A::_15_BIT),
97            8 => Some(BITS_A::_16_BIT),
98            _ => None,
99        }
100    }
101    #[doc = "Checks if the value of the field is `_8_BIT`"]
102    #[inline(always)]
103    pub fn is_8_bit(&self) -> bool {
104        *self == BITS_A::_8_BIT
105    }
106    #[doc = "Checks if the value of the field is `_9_BIT`"]
107    #[inline(always)]
108    pub fn is_9_bit(&self) -> bool {
109        *self == BITS_A::_9_BIT
110    }
111    #[doc = "Checks if the value of the field is `_10_BIT`"]
112    #[inline(always)]
113    pub fn is_10_bit(&self) -> bool {
114        *self == BITS_A::_10_BIT
115    }
116    #[doc = "Checks if the value of the field is `_11_BIT`"]
117    #[inline(always)]
118    pub fn is_11_bit(&self) -> bool {
119        *self == BITS_A::_11_BIT
120    }
121    #[doc = "Checks if the value of the field is `_12_BIT`"]
122    #[inline(always)]
123    pub fn is_12_bit(&self) -> bool {
124        *self == BITS_A::_12_BIT
125    }
126    #[doc = "Checks if the value of the field is `_13_BIT`"]
127    #[inline(always)]
128    pub fn is_13_bit(&self) -> bool {
129        *self == BITS_A::_13_BIT
130    }
131    #[doc = "Checks if the value of the field is `_14_BIT`"]
132    #[inline(always)]
133    pub fn is_14_bit(&self) -> bool {
134        *self == BITS_A::_14_BIT
135    }
136    #[doc = "Checks if the value of the field is `_15_BIT`"]
137    #[inline(always)]
138    pub fn is_15_bit(&self) -> bool {
139        *self == BITS_A::_15_BIT
140    }
141    #[doc = "Checks if the value of the field is `_16_BIT`"]
142    #[inline(always)]
143    pub fn is_16_bit(&self) -> bool {
144        *self == BITS_A::_16_BIT
145    }
146}
147#[doc = "Field `BITS` writer - Bits Per Transfer"]
148pub type BITS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSR_SPEC, u8, BITS_A, 4, O>;
149impl<'a, const O: u8> BITS_W<'a, O> {
150    #[doc = "8 bits for transfer"]
151    #[inline(always)]
152    pub fn _8_bit(self) -> &'a mut W {
153        self.variant(BITS_A::_8_BIT)
154    }
155    #[doc = "9 bits for transfer"]
156    #[inline(always)]
157    pub fn _9_bit(self) -> &'a mut W {
158        self.variant(BITS_A::_9_BIT)
159    }
160    #[doc = "10 bits for transfer"]
161    #[inline(always)]
162    pub fn _10_bit(self) -> &'a mut W {
163        self.variant(BITS_A::_10_BIT)
164    }
165    #[doc = "11 bits for transfer"]
166    #[inline(always)]
167    pub fn _11_bit(self) -> &'a mut W {
168        self.variant(BITS_A::_11_BIT)
169    }
170    #[doc = "12 bits for transfer"]
171    #[inline(always)]
172    pub fn _12_bit(self) -> &'a mut W {
173        self.variant(BITS_A::_12_BIT)
174    }
175    #[doc = "13 bits for transfer"]
176    #[inline(always)]
177    pub fn _13_bit(self) -> &'a mut W {
178        self.variant(BITS_A::_13_BIT)
179    }
180    #[doc = "14 bits for transfer"]
181    #[inline(always)]
182    pub fn _14_bit(self) -> &'a mut W {
183        self.variant(BITS_A::_14_BIT)
184    }
185    #[doc = "15 bits for transfer"]
186    #[inline(always)]
187    pub fn _15_bit(self) -> &'a mut W {
188        self.variant(BITS_A::_15_BIT)
189    }
190    #[doc = "16 bits for transfer"]
191    #[inline(always)]
192    pub fn _16_bit(self) -> &'a mut W {
193        self.variant(BITS_A::_16_BIT)
194    }
195}
196#[doc = "Field `SCBR` reader - Serial Clock Baud Rate"]
197pub type SCBR_R = crate::FieldReader<u8, u8>;
198#[doc = "Field `SCBR` writer - Serial Clock Baud Rate"]
199pub type SCBR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSR_SPEC, u8, u8, 8, O>;
200#[doc = "Field `DLYBS` reader - Delay Before SPCK"]
201pub type DLYBS_R = crate::FieldReader<u8, u8>;
202#[doc = "Field `DLYBS` writer - Delay Before SPCK"]
203pub type DLYBS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSR_SPEC, u8, u8, 8, O>;
204#[doc = "Field `DLYBCT` reader - Delay Between Consecutive Transfers"]
205pub type DLYBCT_R = crate::FieldReader<u8, u8>;
206#[doc = "Field `DLYBCT` writer - Delay Between Consecutive Transfers"]
207pub type DLYBCT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSR_SPEC, u8, u8, 8, O>;
208impl R {
209    #[doc = "Bit 0 - Clock Polarity"]
210    #[inline(always)]
211    pub fn cpol(&self) -> CPOL_R {
212        CPOL_R::new((self.bits & 1) != 0)
213    }
214    #[doc = "Bit 1 - Clock Phase"]
215    #[inline(always)]
216    pub fn ncpha(&self) -> NCPHA_R {
217        NCPHA_R::new(((self.bits >> 1) & 1) != 0)
218    }
219    #[doc = "Bit 2 - Chip Select Not Active After Transfer (Ignored if CSAAT = 1)"]
220    #[inline(always)]
221    pub fn csnaat(&self) -> CSNAAT_R {
222        CSNAAT_R::new(((self.bits >> 2) & 1) != 0)
223    }
224    #[doc = "Bit 3 - Chip Select Active After Transfer"]
225    #[inline(always)]
226    pub fn csaat(&self) -> CSAAT_R {
227        CSAAT_R::new(((self.bits >> 3) & 1) != 0)
228    }
229    #[doc = "Bits 4:7 - Bits Per Transfer"]
230    #[inline(always)]
231    pub fn bits_(&self) -> BITS_R {
232        BITS_R::new(((self.bits >> 4) & 0x0f) as u8)
233    }
234    #[doc = "Bits 8:15 - Serial Clock Baud Rate"]
235    #[inline(always)]
236    pub fn scbr(&self) -> SCBR_R {
237        SCBR_R::new(((self.bits >> 8) & 0xff) as u8)
238    }
239    #[doc = "Bits 16:23 - Delay Before SPCK"]
240    #[inline(always)]
241    pub fn dlybs(&self) -> DLYBS_R {
242        DLYBS_R::new(((self.bits >> 16) & 0xff) as u8)
243    }
244    #[doc = "Bits 24:31 - Delay Between Consecutive Transfers"]
245    #[inline(always)]
246    pub fn dlybct(&self) -> DLYBCT_R {
247        DLYBCT_R::new(((self.bits >> 24) & 0xff) as u8)
248    }
249}
250impl W {
251    #[doc = "Bit 0 - Clock Polarity"]
252    #[inline(always)]
253    #[must_use]
254    pub fn cpol(&mut self) -> CPOL_W<0> {
255        CPOL_W::new(self)
256    }
257    #[doc = "Bit 1 - Clock Phase"]
258    #[inline(always)]
259    #[must_use]
260    pub fn ncpha(&mut self) -> NCPHA_W<1> {
261        NCPHA_W::new(self)
262    }
263    #[doc = "Bit 2 - Chip Select Not Active After Transfer (Ignored if CSAAT = 1)"]
264    #[inline(always)]
265    #[must_use]
266    pub fn csnaat(&mut self) -> CSNAAT_W<2> {
267        CSNAAT_W::new(self)
268    }
269    #[doc = "Bit 3 - Chip Select Active After Transfer"]
270    #[inline(always)]
271    #[must_use]
272    pub fn csaat(&mut self) -> CSAAT_W<3> {
273        CSAAT_W::new(self)
274    }
275    #[doc = "Bits 4:7 - Bits Per Transfer"]
276    #[inline(always)]
277    #[must_use]
278    pub fn bits_(&mut self) -> BITS_W<4> {
279        BITS_W::new(self)
280    }
281    #[doc = "Bits 8:15 - Serial Clock Baud Rate"]
282    #[inline(always)]
283    #[must_use]
284    pub fn scbr(&mut self) -> SCBR_W<8> {
285        SCBR_W::new(self)
286    }
287    #[doc = "Bits 16:23 - Delay Before SPCK"]
288    #[inline(always)]
289    #[must_use]
290    pub fn dlybs(&mut self) -> DLYBS_W<16> {
291        DLYBS_W::new(self)
292    }
293    #[doc = "Bits 24:31 - Delay Between Consecutive Transfers"]
294    #[inline(always)]
295    #[must_use]
296    pub fn dlybct(&mut self) -> DLYBCT_W<24> {
297        DLYBCT_W::new(self)
298    }
299    #[doc = "Writes raw bits to the register."]
300    #[inline(always)]
301    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
302        self.0.bits(bits);
303        self
304    }
305}
306#[doc = "Chip Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"]
307pub struct CSR_SPEC;
308impl crate::RegisterSpec for CSR_SPEC {
309    type Ux = u32;
310}
311#[doc = "`read()` method returns [csr::R](R) reader structure"]
312impl crate::Readable for CSR_SPEC {
313    type Reader = R;
314}
315#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"]
316impl crate::Writable for CSR_SPEC {
317    type Writer = W;
318    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
319    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
320}
atsam4s2c_pac/spi/csr.rs

atsam4s2c_pac/spi/
csr.rs
