atsam4n8a_pac/pwm/
cmr3.rs

1#[doc = "Register `CMR3` reader"]
2pub struct R(crate::R<CMR3_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CMR3_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CMR3_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CMR3_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CMR3` writer"]
17pub struct W(crate::W<CMR3_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CMR3_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CMR3_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CMR3_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CPRE` reader - Channel Pre-scaler"]
38pub type CPRE_R = crate::FieldReader<u8, CPRE_A>;
39#[doc = "Channel Pre-scaler\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CPRE_A {
43    #[doc = "0: Master Clock"]
44    MCK = 0,
45    #[doc = "1: Master Clock divided by 2"]
46    MCKDIV2 = 1,
47    #[doc = "2: Master Clock divided by 4"]
48    MCKDIV4 = 2,
49    #[doc = "3: Master Clock divided by 8"]
50    MCKDIV8 = 3,
51    #[doc = "4: Master Clock divided by 16"]
52    MCKDIV16 = 4,
53    #[doc = "5: Master Clock divided by 32"]
54    MCKDIV32 = 5,
55    #[doc = "6: Master Clock divided by 64"]
56    MCKDIV64 = 6,
57    #[doc = "7: Master Clock divided by 128"]
58    MCKDIV128 = 7,
59    #[doc = "8: Master Clock divided by 256"]
60    MCKDIV256 = 8,
61    #[doc = "9: Master Clock divided by 512"]
62    MCKDIV512 = 9,
63    #[doc = "10: Master Clock divided by 1024"]
64    MCKDIV1024 = 10,
65    #[doc = "11: Clock A"]
66    CLKA = 11,
67    #[doc = "12: Clock B"]
68    CLKB = 12,
69}
70impl From<CPRE_A> for u8 {
71    #[inline(always)]
72    fn from(variant: CPRE_A) -> Self {
73        variant as _
74    }
75}
76impl CPRE_R {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub fn variant(&self) -> Option<CPRE_A> {
80        match self.bits {
81            0 => Some(CPRE_A::MCK),
82            1 => Some(CPRE_A::MCKDIV2),
83            2 => Some(CPRE_A::MCKDIV4),
84            3 => Some(CPRE_A::MCKDIV8),
85            4 => Some(CPRE_A::MCKDIV16),
86            5 => Some(CPRE_A::MCKDIV32),
87            6 => Some(CPRE_A::MCKDIV64),
88            7 => Some(CPRE_A::MCKDIV128),
89            8 => Some(CPRE_A::MCKDIV256),
90            9 => Some(CPRE_A::MCKDIV512),
91            10 => Some(CPRE_A::MCKDIV1024),
92            11 => Some(CPRE_A::CLKA),
93            12 => Some(CPRE_A::CLKB),
94            _ => None,
95        }
96    }
97    #[doc = "Checks if the value of the field is `MCK`"]
98    #[inline(always)]
99    pub fn is_mck(&self) -> bool {
100        *self == CPRE_A::MCK
101    }
102    #[doc = "Checks if the value of the field is `MCKDIV2`"]
103    #[inline(always)]
104    pub fn is_mckdiv2(&self) -> bool {
105        *self == CPRE_A::MCKDIV2
106    }
107    #[doc = "Checks if the value of the field is `MCKDIV4`"]
108    #[inline(always)]
109    pub fn is_mckdiv4(&self) -> bool {
110        *self == CPRE_A::MCKDIV4
111    }
112    #[doc = "Checks if the value of the field is `MCKDIV8`"]
113    #[inline(always)]
114    pub fn is_mckdiv8(&self) -> bool {
115        *self == CPRE_A::MCKDIV8
116    }
117    #[doc = "Checks if the value of the field is `MCKDIV16`"]
118    #[inline(always)]
119    pub fn is_mckdiv16(&self) -> bool {
120        *self == CPRE_A::MCKDIV16
121    }
122    #[doc = "Checks if the value of the field is `MCKDIV32`"]
123    #[inline(always)]
124    pub fn is_mckdiv32(&self) -> bool {
125        *self == CPRE_A::MCKDIV32
126    }
127    #[doc = "Checks if the value of the field is `MCKDIV64`"]
128    #[inline(always)]
129    pub fn is_mckdiv64(&self) -> bool {
130        *self == CPRE_A::MCKDIV64
131    }
132    #[doc = "Checks if the value of the field is `MCKDIV128`"]
133    #[inline(always)]
134    pub fn is_mckdiv128(&self) -> bool {
135        *self == CPRE_A::MCKDIV128
136    }
137    #[doc = "Checks if the value of the field is `MCKDIV256`"]
138    #[inline(always)]
139    pub fn is_mckdiv256(&self) -> bool {
140        *self == CPRE_A::MCKDIV256
141    }
142    #[doc = "Checks if the value of the field is `MCKDIV512`"]
143    #[inline(always)]
144    pub fn is_mckdiv512(&self) -> bool {
145        *self == CPRE_A::MCKDIV512
146    }
147    #[doc = "Checks if the value of the field is `MCKDIV1024`"]
148    #[inline(always)]
149    pub fn is_mckdiv1024(&self) -> bool {
150        *self == CPRE_A::MCKDIV1024
151    }
152    #[doc = "Checks if the value of the field is `CLKA`"]
153    #[inline(always)]
154    pub fn is_clka(&self) -> bool {
155        *self == CPRE_A::CLKA
156    }
157    #[doc = "Checks if the value of the field is `CLKB`"]
158    #[inline(always)]
159    pub fn is_clkb(&self) -> bool {
160        *self == CPRE_A::CLKB
161    }
162}
163#[doc = "Field `CPRE` writer - Channel Pre-scaler"]
164pub type CPRE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMR3_SPEC, u8, CPRE_A, 4, O>;
165impl<'a, const O: u8> CPRE_W<'a, O> {
166    #[doc = "Master Clock"]
167    #[inline(always)]
168    pub fn mck(self) -> &'a mut W {
169        self.variant(CPRE_A::MCK)
170    }
171    #[doc = "Master Clock divided by 2"]
172    #[inline(always)]
173    pub fn mckdiv2(self) -> &'a mut W {
174        self.variant(CPRE_A::MCKDIV2)
175    }
176    #[doc = "Master Clock divided by 4"]
177    #[inline(always)]
178    pub fn mckdiv4(self) -> &'a mut W {
179        self.variant(CPRE_A::MCKDIV4)
180    }
181    #[doc = "Master Clock divided by 8"]
182    #[inline(always)]
183    pub fn mckdiv8(self) -> &'a mut W {
184        self.variant(CPRE_A::MCKDIV8)
185    }
186    #[doc = "Master Clock divided by 16"]
187    #[inline(always)]
188    pub fn mckdiv16(self) -> &'a mut W {
189        self.variant(CPRE_A::MCKDIV16)
190    }
191    #[doc = "Master Clock divided by 32"]
192    #[inline(always)]
193    pub fn mckdiv32(self) -> &'a mut W {
194        self.variant(CPRE_A::MCKDIV32)
195    }
196    #[doc = "Master Clock divided by 64"]
197    #[inline(always)]
198    pub fn mckdiv64(self) -> &'a mut W {
199        self.variant(CPRE_A::MCKDIV64)
200    }
201    #[doc = "Master Clock divided by 128"]
202    #[inline(always)]
203    pub fn mckdiv128(self) -> &'a mut W {
204        self.variant(CPRE_A::MCKDIV128)
205    }
206    #[doc = "Master Clock divided by 256"]
207    #[inline(always)]
208    pub fn mckdiv256(self) -> &'a mut W {
209        self.variant(CPRE_A::MCKDIV256)
210    }
211    #[doc = "Master Clock divided by 512"]
212    #[inline(always)]
213    pub fn mckdiv512(self) -> &'a mut W {
214        self.variant(CPRE_A::MCKDIV512)
215    }
216    #[doc = "Master Clock divided by 1024"]
217    #[inline(always)]
218    pub fn mckdiv1024(self) -> &'a mut W {
219        self.variant(CPRE_A::MCKDIV1024)
220    }
221    #[doc = "Clock A"]
222    #[inline(always)]
223    pub fn clka(self) -> &'a mut W {
224        self.variant(CPRE_A::CLKA)
225    }
226    #[doc = "Clock B"]
227    #[inline(always)]
228    pub fn clkb(self) -> &'a mut W {
229        self.variant(CPRE_A::CLKB)
230    }
231}
232#[doc = "Field `CALG` reader - Channel Alignment"]
233pub type CALG_R = crate::BitReader<bool>;
234#[doc = "Field `CALG` writer - Channel Alignment"]
235pub type CALG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMR3_SPEC, bool, O>;
236#[doc = "Field `CPOL` reader - Channel Polarity"]
237pub type CPOL_R = crate::BitReader<bool>;
238#[doc = "Field `CPOL` writer - Channel Polarity"]
239pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMR3_SPEC, bool, O>;
240#[doc = "Field `CPD` reader - Channel Update Period"]
241pub type CPD_R = crate::BitReader<bool>;
242#[doc = "Field `CPD` writer - Channel Update Period"]
243pub type CPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMR3_SPEC, bool, O>;
244impl R {
245    #[doc = "Bits 0:3 - Channel Pre-scaler"]
246    #[inline(always)]
247    pub fn cpre(&self) -> CPRE_R {
248        CPRE_R::new((self.bits & 0x0f) as u8)
249    }
250    #[doc = "Bit 8 - Channel Alignment"]
251    #[inline(always)]
252    pub fn calg(&self) -> CALG_R {
253        CALG_R::new(((self.bits >> 8) & 1) != 0)
254    }
255    #[doc = "Bit 9 - Channel Polarity"]
256    #[inline(always)]
257    pub fn cpol(&self) -> CPOL_R {
258        CPOL_R::new(((self.bits >> 9) & 1) != 0)
259    }
260    #[doc = "Bit 10 - Channel Update Period"]
261    #[inline(always)]
262    pub fn cpd(&self) -> CPD_R {
263        CPD_R::new(((self.bits >> 10) & 1) != 0)
264    }
265}
266impl W {
267    #[doc = "Bits 0:3 - Channel Pre-scaler"]
268    #[inline(always)]
269    #[must_use]
270    pub fn cpre(&mut self) -> CPRE_W<0> {
271        CPRE_W::new(self)
272    }
273    #[doc = "Bit 8 - Channel Alignment"]
274    #[inline(always)]
275    #[must_use]
276    pub fn calg(&mut self) -> CALG_W<8> {
277        CALG_W::new(self)
278    }
279    #[doc = "Bit 9 - Channel Polarity"]
280    #[inline(always)]
281    #[must_use]
282    pub fn cpol(&mut self) -> CPOL_W<9> {
283        CPOL_W::new(self)
284    }
285    #[doc = "Bit 10 - Channel Update Period"]
286    #[inline(always)]
287    #[must_use]
288    pub fn cpd(&mut self) -> CPD_W<10> {
289        CPD_W::new(self)
290    }
291    #[doc = "Writes raw bits to the register."]
292    #[inline(always)]
293    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
294        self.0.bits(bits);
295        self
296    }
297}
298#[doc = "PWM Channel Mode Register (ch_num = 3)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmr3](index.html) module"]
299pub struct CMR3_SPEC;
300impl crate::RegisterSpec for CMR3_SPEC {
301    type Ux = u32;
302}
303#[doc = "`read()` method returns [cmr3::R](R) reader structure"]
304impl crate::Readable for CMR3_SPEC {
305    type Reader = R;
306}
307#[doc = "`write(|w| ..)` method takes [cmr3::W](W) writer structure"]
308impl crate::Writable for CMR3_SPEC {
309    type Writer = W;
310    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
311    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
312}
313#[doc = "`reset()` method sets CMR3 to value 0"]
314impl crate::Resettable for CMR3_SPEC {
315    const RESET_VALUE: Self::Ux = 0;
316}
atsam4n8a_pac/pwm/cmr3.rs

atsam4n8a_pac/pwm/
cmr3.rs
