atsam4n16c_pac/uart3/
ier.rs

1#[doc = "Register `IER` writer"]
2pub struct W(crate::W<IER_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<IER_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<IER_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<IER_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `RXRDY` writer - Enable RXRDY Interrupt"]
23pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
24#[doc = "Field `TXRDY` writer - Enable TXRDY Interrupt"]
25pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
26#[doc = "Field `ENDRX` writer - Enable End of Receive Transfer Interrupt"]
27pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
28#[doc = "Field `ENDTX` writer - Enable End of Transmit Interrupt"]
29pub type ENDTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
30#[doc = "Field `OVRE` writer - Enable Overrun Error Interrupt"]
31pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
32#[doc = "Field `FRAME` writer - Enable Framing Error Interrupt"]
33pub type FRAME_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
34#[doc = "Field `PARE` writer - Enable Parity Error Interrupt"]
35pub type PARE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
36#[doc = "Field `TXEMPTY` writer - Enable TXEMPTY Interrupt"]
37pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
38#[doc = "Field `TXBUFE` writer - Enable Buffer Empty Interrupt"]
39pub type TXBUFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
40#[doc = "Field `RXBUFF` writer - Enable Buffer Full Interrupt"]
41pub type RXBUFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
42impl W {
43    #[doc = "Bit 0 - Enable RXRDY Interrupt"]
44    #[inline(always)]
45    #[must_use]
46    pub fn rxrdy(&mut self) -> RXRDY_W<0> {
47        RXRDY_W::new(self)
48    }
49    #[doc = "Bit 1 - Enable TXRDY Interrupt"]
50    #[inline(always)]
51    #[must_use]
52    pub fn txrdy(&mut self) -> TXRDY_W<1> {
53        TXRDY_W::new(self)
54    }
55    #[doc = "Bit 3 - Enable End of Receive Transfer Interrupt"]
56    #[inline(always)]
57    #[must_use]
58    pub fn endrx(&mut self) -> ENDRX_W<3> {
59        ENDRX_W::new(self)
60    }
61    #[doc = "Bit 4 - Enable End of Transmit Interrupt"]
62    #[inline(always)]
63    #[must_use]
64    pub fn endtx(&mut self) -> ENDTX_W<4> {
65        ENDTX_W::new(self)
66    }
67    #[doc = "Bit 5 - Enable Overrun Error Interrupt"]
68    #[inline(always)]
69    #[must_use]
70    pub fn ovre(&mut self) -> OVRE_W<5> {
71        OVRE_W::new(self)
72    }
73    #[doc = "Bit 6 - Enable Framing Error Interrupt"]
74    #[inline(always)]
75    #[must_use]
76    pub fn frame(&mut self) -> FRAME_W<6> {
77        FRAME_W::new(self)
78    }
79    #[doc = "Bit 7 - Enable Parity Error Interrupt"]
80    #[inline(always)]
81    #[must_use]
82    pub fn pare(&mut self) -> PARE_W<7> {
83        PARE_W::new(self)
84    }
85    #[doc = "Bit 9 - Enable TXEMPTY Interrupt"]
86    #[inline(always)]
87    #[must_use]
88    pub fn txempty(&mut self) -> TXEMPTY_W<9> {
89        TXEMPTY_W::new(self)
90    }
91    #[doc = "Bit 11 - Enable Buffer Empty Interrupt"]
92    #[inline(always)]
93    #[must_use]
94    pub fn txbufe(&mut self) -> TXBUFE_W<11> {
95        TXBUFE_W::new(self)
96    }
97    #[doc = "Bit 12 - Enable Buffer Full Interrupt"]
98    #[inline(always)]
99    #[must_use]
100    pub fn rxbuff(&mut self) -> RXBUFF_W<12> {
101        RXBUFF_W::new(self)
102    }
103    #[doc = "Writes raw bits to the register."]
104    #[inline(always)]
105    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
106        self.0.bits(bits);
107        self
108    }
109}
110#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"]
111pub struct IER_SPEC;
112impl crate::RegisterSpec for IER_SPEC {
113    type Ux = u32;
114}
115#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"]
116impl crate::Writable for IER_SPEC {
117    type Writer = W;
118    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
119    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
120}
atsam4n16c_pac/uart3/ier.rs

atsam4n16c_pac/uart3/
ier.rs
