atsam4ls8c_pac/twim0/
imr.rs

1#[doc = "Register `IMR` reader"]
2pub struct R(crate::R<IMR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IMR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IMR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IMR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `RXRDY` reader - RHR Data Ready"]
17pub type RXRDY_R = crate::BitReader<bool>;
18#[doc = "Field `TXRDY` reader - THR Data Ready"]
19pub type TXRDY_R = crate::BitReader<bool>;
20#[doc = "Field `CRDY` reader - Ready for More Commands"]
21pub type CRDY_R = crate::BitReader<bool>;
22#[doc = "Field `CCOMP` reader - Command Complete"]
23pub type CCOMP_R = crate::BitReader<bool>;
24#[doc = "Field `IDLE` reader - Master Interface is Idle"]
25pub type IDLE_R = crate::BitReader<bool>;
26#[doc = "Field `BUSFREE` reader - Two-wire Bus is Free"]
27pub type BUSFREE_R = crate::BitReader<bool>;
28#[doc = "Field `ANAK` reader - NAK in Address Phase Received"]
29pub type ANAK_R = crate::BitReader<bool>;
30#[doc = "Field `DNAK` reader - NAK in Data Phase Received"]
31pub type DNAK_R = crate::BitReader<bool>;
32#[doc = "Field `ARBLST` reader - Arbitration Lost"]
33pub type ARBLST_R = crate::BitReader<bool>;
34#[doc = "Field `SMBALERT` reader - SMBus Alert"]
35pub type SMBALERT_R = crate::BitReader<bool>;
36#[doc = "Field `TOUT` reader - Timeout"]
37pub type TOUT_R = crate::BitReader<bool>;
38#[doc = "Field `PECERR` reader - PEC Error"]
39pub type PECERR_R = crate::BitReader<bool>;
40#[doc = "Field `STOP` reader - Stop Request Accepted"]
41pub type STOP_R = crate::BitReader<bool>;
42#[doc = "Field `HSMCACK` reader - ACK in HS-mode Master Code Phase Received"]
43pub type HSMCACK_R = crate::BitReader<bool>;
44impl R {
45    #[doc = "Bit 0 - RHR Data Ready"]
46    #[inline(always)]
47    pub fn rxrdy(&self) -> RXRDY_R {
48        RXRDY_R::new((self.bits & 1) != 0)
49    }
50    #[doc = "Bit 1 - THR Data Ready"]
51    #[inline(always)]
52    pub fn txrdy(&self) -> TXRDY_R {
53        TXRDY_R::new(((self.bits >> 1) & 1) != 0)
54    }
55    #[doc = "Bit 2 - Ready for More Commands"]
56    #[inline(always)]
57    pub fn crdy(&self) -> CRDY_R {
58        CRDY_R::new(((self.bits >> 2) & 1) != 0)
59    }
60    #[doc = "Bit 3 - Command Complete"]
61    #[inline(always)]
62    pub fn ccomp(&self) -> CCOMP_R {
63        CCOMP_R::new(((self.bits >> 3) & 1) != 0)
64    }
65    #[doc = "Bit 4 - Master Interface is Idle"]
66    #[inline(always)]
67    pub fn idle(&self) -> IDLE_R {
68        IDLE_R::new(((self.bits >> 4) & 1) != 0)
69    }
70    #[doc = "Bit 5 - Two-wire Bus is Free"]
71    #[inline(always)]
72    pub fn busfree(&self) -> BUSFREE_R {
73        BUSFREE_R::new(((self.bits >> 5) & 1) != 0)
74    }
75    #[doc = "Bit 8 - NAK in Address Phase Received"]
76    #[inline(always)]
77    pub fn anak(&self) -> ANAK_R {
78        ANAK_R::new(((self.bits >> 8) & 1) != 0)
79    }
80    #[doc = "Bit 9 - NAK in Data Phase Received"]
81    #[inline(always)]
82    pub fn dnak(&self) -> DNAK_R {
83        DNAK_R::new(((self.bits >> 9) & 1) != 0)
84    }
85    #[doc = "Bit 10 - Arbitration Lost"]
86    #[inline(always)]
87    pub fn arblst(&self) -> ARBLST_R {
88        ARBLST_R::new(((self.bits >> 10) & 1) != 0)
89    }
90    #[doc = "Bit 11 - SMBus Alert"]
91    #[inline(always)]
92    pub fn smbalert(&self) -> SMBALERT_R {
93        SMBALERT_R::new(((self.bits >> 11) & 1) != 0)
94    }
95    #[doc = "Bit 12 - Timeout"]
96    #[inline(always)]
97    pub fn tout(&self) -> TOUT_R {
98        TOUT_R::new(((self.bits >> 12) & 1) != 0)
99    }
100    #[doc = "Bit 13 - PEC Error"]
101    #[inline(always)]
102    pub fn pecerr(&self) -> PECERR_R {
103        PECERR_R::new(((self.bits >> 13) & 1) != 0)
104    }
105    #[doc = "Bit 14 - Stop Request Accepted"]
106    #[inline(always)]
107    pub fn stop(&self) -> STOP_R {
108        STOP_R::new(((self.bits >> 14) & 1) != 0)
109    }
110    #[doc = "Bit 17 - ACK in HS-mode Master Code Phase Received"]
111    #[inline(always)]
112    pub fn hsmcack(&self) -> HSMCACK_R {
113        HSMCACK_R::new(((self.bits >> 17) & 1) != 0)
114    }
115}
116#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"]
117pub struct IMR_SPEC;
118impl crate::RegisterSpec for IMR_SPEC {
119    type Ux = u32;
120}
121#[doc = "`read()` method returns [imr::R](R) reader structure"]
122impl crate::Readable for IMR_SPEC {
123    type Reader = R;
124}
125#[doc = "`reset()` method sets IMR to value 0"]
126impl crate::Resettable for IMR_SPEC {
127    const RESET_VALUE: Self::Ux = 0;
128}
atsam4ls8c_pac/twim0/imr.rs

atsam4ls8c_pac/twim0/
imr.rs
