1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - Memory Address Register"]
5 pub mar0: MAR,
6 #[doc = "0x04 - Peripheral Select Register"]
7 pub psr0: PSR,
8 #[doc = "0x08 - Transfer Counter Register"]
9 pub tcr0: TCR,
10 #[doc = "0x0c - Memory Address Reload Register"]
11 pub marr0: MARR,
12 #[doc = "0x10 - Transfer Counter Reload Register"]
13 pub tcrr0: TCRR,
14 #[doc = "0x14 - Control Register"]
15 pub cr0: CR,
16 #[doc = "0x18 - Mode Register"]
17 pub mr0: MR,
18 #[doc = "0x1c - Status Register"]
19 pub sr0: SR,
20 #[doc = "0x20 - Interrupt Enable Register"]
21 pub ier0: IER,
22 #[doc = "0x24 - Interrupt Disable Register"]
23 pub idr0: IDR,
24 #[doc = "0x28 - Interrupt Mask Register"]
25 pub imr0: IMR,
26 #[doc = "0x2c - Interrupt Status Register"]
27 pub isr0: ISR,
28 _reserved12: [u8; 0x10],
29 #[doc = "0x40 - Memory Address Register"]
30 pub mar1: MAR,
31 #[doc = "0x44 - Peripheral Select Register"]
32 pub psr1: PSR,
33 #[doc = "0x48 - Transfer Counter Register"]
34 pub tcr1: TCR,
35 #[doc = "0x4c - Memory Address Reload Register"]
36 pub marr1: MARR,
37 #[doc = "0x50 - Transfer Counter Reload Register"]
38 pub tcrr1: TCRR,
39 #[doc = "0x54 - Control Register"]
40 pub cr1: CR,
41 #[doc = "0x58 - Mode Register"]
42 pub mr1: MR,
43 #[doc = "0x5c - Status Register"]
44 pub sr1: SR,
45 #[doc = "0x60 - Interrupt Enable Register"]
46 pub ier1: IER,
47 #[doc = "0x64 - Interrupt Disable Register"]
48 pub idr1: IDR,
49 #[doc = "0x68 - Interrupt Mask Register"]
50 pub imr1: IMR,
51 #[doc = "0x6c - Interrupt Status Register"]
52 pub isr1: ISR,
53 _reserved24: [u8; 0x10],
54 #[doc = "0x80 - Memory Address Register"]
55 pub mar2: MAR,
56 #[doc = "0x84 - Peripheral Select Register"]
57 pub psr2: PSR,
58 #[doc = "0x88 - Transfer Counter Register"]
59 pub tcr2: TCR,
60 #[doc = "0x8c - Memory Address Reload Register"]
61 pub marr2: MARR,
62 #[doc = "0x90 - Transfer Counter Reload Register"]
63 pub tcrr2: TCRR,
64 #[doc = "0x94 - Control Register"]
65 pub cr2: CR,
66 #[doc = "0x98 - Mode Register"]
67 pub mr2: MR,
68 #[doc = "0x9c - Status Register"]
69 pub sr2: SR,
70 #[doc = "0xa0 - Interrupt Enable Register"]
71 pub ier2: IER,
72 #[doc = "0xa4 - Interrupt Disable Register"]
73 pub idr2: IDR,
74 #[doc = "0xa8 - Interrupt Mask Register"]
75 pub imr2: IMR,
76 #[doc = "0xac - Interrupt Status Register"]
77 pub isr2: ISR,
78 _reserved36: [u8; 0x10],
79 #[doc = "0xc0 - Memory Address Register"]
80 pub mar3: MAR,
81 #[doc = "0xc4 - Peripheral Select Register"]
82 pub psr3: PSR,
83 #[doc = "0xc8 - Transfer Counter Register"]
84 pub tcr3: TCR,
85 #[doc = "0xcc - Memory Address Reload Register"]
86 pub marr3: MARR,
87 #[doc = "0xd0 - Transfer Counter Reload Register"]
88 pub tcrr3: TCRR,
89 #[doc = "0xd4 - Control Register"]
90 pub cr3: CR,
91 #[doc = "0xd8 - Mode Register"]
92 pub mr3: MR,
93 #[doc = "0xdc - Status Register"]
94 pub sr3: SR,
95 #[doc = "0xe0 - Interrupt Enable Register"]
96 pub ier3: IER,
97 #[doc = "0xe4 - Interrupt Disable Register"]
98 pub idr3: IDR,
99 #[doc = "0xe8 - Interrupt Mask Register"]
100 pub imr3: IMR,
101 #[doc = "0xec - Interrupt Status Register"]
102 pub isr3: ISR,
103 _reserved48: [u8; 0x10],
104 #[doc = "0x100 - Memory Address Register"]
105 pub mar4: MAR,
106 #[doc = "0x104 - Peripheral Select Register"]
107 pub psr4: PSR,
108 #[doc = "0x108 - Transfer Counter Register"]
109 pub tcr4: TCR,
110 #[doc = "0x10c - Memory Address Reload Register"]
111 pub marr4: MARR,
112 #[doc = "0x110 - Transfer Counter Reload Register"]
113 pub tcrr4: TCRR,
114 #[doc = "0x114 - Control Register"]
115 pub cr4: CR,
116 #[doc = "0x118 - Mode Register"]
117 pub mr4: MR,
118 #[doc = "0x11c - Status Register"]
119 pub sr4: SR,
120 #[doc = "0x120 - Interrupt Enable Register"]
121 pub ier4: IER,
122 #[doc = "0x124 - Interrupt Disable Register"]
123 pub idr4: IDR,
124 #[doc = "0x128 - Interrupt Mask Register"]
125 pub imr4: IMR,
126 #[doc = "0x12c - Interrupt Status Register"]
127 pub isr4: ISR,
128 _reserved60: [u8; 0x10],
129 #[doc = "0x140 - Memory Address Register"]
130 pub mar5: MAR,
131 #[doc = "0x144 - Peripheral Select Register"]
132 pub psr5: PSR,
133 #[doc = "0x148 - Transfer Counter Register"]
134 pub tcr5: TCR,
135 #[doc = "0x14c - Memory Address Reload Register"]
136 pub marr5: MARR,
137 #[doc = "0x150 - Transfer Counter Reload Register"]
138 pub tcrr5: TCRR,
139 #[doc = "0x154 - Control Register"]
140 pub cr5: CR,
141 #[doc = "0x158 - Mode Register"]
142 pub mr5: MR,
143 #[doc = "0x15c - Status Register"]
144 pub sr5: SR,
145 #[doc = "0x160 - Interrupt Enable Register"]
146 pub ier5: IER,
147 #[doc = "0x164 - Interrupt Disable Register"]
148 pub idr5: IDR,
149 #[doc = "0x168 - Interrupt Mask Register"]
150 pub imr5: IMR,
151 #[doc = "0x16c - Interrupt Status Register"]
152 pub isr5: ISR,
153 _reserved72: [u8; 0x10],
154 #[doc = "0x180 - Memory Address Register"]
155 pub mar6: MAR,
156 #[doc = "0x184 - Peripheral Select Register"]
157 pub psr6: PSR,
158 #[doc = "0x188 - Transfer Counter Register"]
159 pub tcr6: TCR,
160 #[doc = "0x18c - Memory Address Reload Register"]
161 pub marr6: MARR,
162 #[doc = "0x190 - Transfer Counter Reload Register"]
163 pub tcrr6: TCRR,
164 #[doc = "0x194 - Control Register"]
165 pub cr6: CR,
166 #[doc = "0x198 - Mode Register"]
167 pub mr6: MR,
168 #[doc = "0x19c - Status Register"]
169 pub sr6: SR,
170 #[doc = "0x1a0 - Interrupt Enable Register"]
171 pub ier6: IER,
172 #[doc = "0x1a4 - Interrupt Disable Register"]
173 pub idr6: IDR,
174 #[doc = "0x1a8 - Interrupt Mask Register"]
175 pub imr6: IMR,
176 #[doc = "0x1ac - Interrupt Status Register"]
177 pub isr6: ISR,
178 _reserved84: [u8; 0x10],
179 #[doc = "0x1c0 - Memory Address Register"]
180 pub mar7: MAR,
181 #[doc = "0x1c4 - Peripheral Select Register"]
182 pub psr7: PSR,
183 #[doc = "0x1c8 - Transfer Counter Register"]
184 pub tcr7: TCR,
185 #[doc = "0x1cc - Memory Address Reload Register"]
186 pub marr7: MARR,
187 #[doc = "0x1d0 - Transfer Counter Reload Register"]
188 pub tcrr7: TCRR,
189 #[doc = "0x1d4 - Control Register"]
190 pub cr7: CR,
191 #[doc = "0x1d8 - Mode Register"]
192 pub mr7: MR,
193 #[doc = "0x1dc - Status Register"]
194 pub sr7: SR,
195 #[doc = "0x1e0 - Interrupt Enable Register"]
196 pub ier7: IER,
197 #[doc = "0x1e4 - Interrupt Disable Register"]
198 pub idr7: IDR,
199 #[doc = "0x1e8 - Interrupt Mask Register"]
200 pub imr7: IMR,
201 #[doc = "0x1ec - Interrupt Status Register"]
202 pub isr7: ISR,
203 _reserved96: [u8; 0x10],
204 #[doc = "0x200 - Memory Address Register"]
205 pub mar8: MAR,
206 #[doc = "0x204 - Peripheral Select Register"]
207 pub psr8: PSR,
208 #[doc = "0x208 - Transfer Counter Register"]
209 pub tcr8: TCR,
210 #[doc = "0x20c - Memory Address Reload Register"]
211 pub marr8: MARR,
212 #[doc = "0x210 - Transfer Counter Reload Register"]
213 pub tcrr8: TCRR,
214 #[doc = "0x214 - Control Register"]
215 pub cr8: CR,
216 #[doc = "0x218 - Mode Register"]
217 pub mr8: MR,
218 #[doc = "0x21c - Status Register"]
219 pub sr8: SR,
220 #[doc = "0x220 - Interrupt Enable Register"]
221 pub ier8: IER,
222 #[doc = "0x224 - Interrupt Disable Register"]
223 pub idr8: IDR,
224 #[doc = "0x228 - Interrupt Mask Register"]
225 pub imr8: IMR,
226 #[doc = "0x22c - Interrupt Status Register"]
227 pub isr8: ISR,
228 _reserved108: [u8; 0x10],
229 #[doc = "0x240 - Memory Address Register"]
230 pub mar9: MAR,
231 #[doc = "0x244 - Peripheral Select Register"]
232 pub psr9: PSR,
233 #[doc = "0x248 - Transfer Counter Register"]
234 pub tcr9: TCR,
235 #[doc = "0x24c - Memory Address Reload Register"]
236 pub marr9: MARR,
237 #[doc = "0x250 - Transfer Counter Reload Register"]
238 pub tcrr9: TCRR,
239 #[doc = "0x254 - Control Register"]
240 pub cr9: CR,
241 #[doc = "0x258 - Mode Register"]
242 pub mr9: MR,
243 #[doc = "0x25c - Status Register"]
244 pub sr9: SR,
245 #[doc = "0x260 - Interrupt Enable Register"]
246 pub ier9: IER,
247 #[doc = "0x264 - Interrupt Disable Register"]
248 pub idr9: IDR,
249 #[doc = "0x268 - Interrupt Mask Register"]
250 pub imr9: IMR,
251 #[doc = "0x26c - Interrupt Status Register"]
252 pub isr9: ISR,
253 _reserved120: [u8; 0x10],
254 #[doc = "0x280 - Memory Address Register"]
255 pub mar10: MAR,
256 #[doc = "0x284 - Peripheral Select Register"]
257 pub psr10: PSR,
258 #[doc = "0x288 - Transfer Counter Register"]
259 pub tcr10: TCR,
260 #[doc = "0x28c - Memory Address Reload Register"]
261 pub marr10: MARR,
262 #[doc = "0x290 - Transfer Counter Reload Register"]
263 pub tcrr10: TCRR,
264 #[doc = "0x294 - Control Register"]
265 pub cr10: CR,
266 #[doc = "0x298 - Mode Register"]
267 pub mr10: MR,
268 #[doc = "0x29c - Status Register"]
269 pub sr10: SR,
270 #[doc = "0x2a0 - Interrupt Enable Register"]
271 pub ier10: IER,
272 #[doc = "0x2a4 - Interrupt Disable Register"]
273 pub idr10: IDR,
274 #[doc = "0x2a8 - Interrupt Mask Register"]
275 pub imr10: IMR,
276 #[doc = "0x2ac - Interrupt Status Register"]
277 pub isr10: ISR,
278 _reserved132: [u8; 0x10],
279 #[doc = "0x2c0 - Memory Address Register"]
280 pub mar11: MAR,
281 #[doc = "0x2c4 - Peripheral Select Register"]
282 pub psr11: PSR,
283 #[doc = "0x2c8 - Transfer Counter Register"]
284 pub tcr11: TCR,
285 #[doc = "0x2cc - Memory Address Reload Register"]
286 pub marr11: MARR,
287 #[doc = "0x2d0 - Transfer Counter Reload Register"]
288 pub tcrr11: TCRR,
289 #[doc = "0x2d4 - Control Register"]
290 pub cr11: CR,
291 #[doc = "0x2d8 - Mode Register"]
292 pub mr11: MR,
293 #[doc = "0x2dc - Status Register"]
294 pub sr11: SR,
295 #[doc = "0x2e0 - Interrupt Enable Register"]
296 pub ier11: IER,
297 #[doc = "0x2e4 - Interrupt Disable Register"]
298 pub idr11: IDR,
299 #[doc = "0x2e8 - Interrupt Mask Register"]
300 pub imr11: IMR,
301 #[doc = "0x2ec - Interrupt Status Register"]
302 pub isr11: ISR,
303 _reserved144: [u8; 0x10],
304 #[doc = "0x300 - Memory Address Register"]
305 pub mar12: MAR,
306 #[doc = "0x304 - Peripheral Select Register"]
307 pub psr12: PSR,
308 #[doc = "0x308 - Transfer Counter Register"]
309 pub tcr12: TCR,
310 #[doc = "0x30c - Memory Address Reload Register"]
311 pub marr12: MARR,
312 #[doc = "0x310 - Transfer Counter Reload Register"]
313 pub tcrr12: TCRR,
314 #[doc = "0x314 - Control Register"]
315 pub cr12: CR,
316 #[doc = "0x318 - Mode Register"]
317 pub mr12: MR,
318 #[doc = "0x31c - Status Register"]
319 pub sr12: SR,
320 #[doc = "0x320 - Interrupt Enable Register"]
321 pub ier12: IER,
322 #[doc = "0x324 - Interrupt Disable Register"]
323 pub idr12: IDR,
324 #[doc = "0x328 - Interrupt Mask Register"]
325 pub imr12: IMR,
326 #[doc = "0x32c - Interrupt Status Register"]
327 pub isr12: ISR,
328 _reserved156: [u8; 0x10],
329 #[doc = "0x340 - Memory Address Register"]
330 pub mar13: MAR,
331 #[doc = "0x344 - Peripheral Select Register"]
332 pub psr13: PSR,
333 #[doc = "0x348 - Transfer Counter Register"]
334 pub tcr13: TCR,
335 #[doc = "0x34c - Memory Address Reload Register"]
336 pub marr13: MARR,
337 #[doc = "0x350 - Transfer Counter Reload Register"]
338 pub tcrr13: TCRR,
339 #[doc = "0x354 - Control Register"]
340 pub cr13: CR,
341 #[doc = "0x358 - Mode Register"]
342 pub mr13: MR,
343 #[doc = "0x35c - Status Register"]
344 pub sr13: SR,
345 #[doc = "0x360 - Interrupt Enable Register"]
346 pub ier13: IER,
347 #[doc = "0x364 - Interrupt Disable Register"]
348 pub idr13: IDR,
349 #[doc = "0x368 - Interrupt Mask Register"]
350 pub imr13: IMR,
351 #[doc = "0x36c - Interrupt Status Register"]
352 pub isr13: ISR,
353 _reserved168: [u8; 0x10],
354 #[doc = "0x380 - Memory Address Register"]
355 pub mar14: MAR,
356 #[doc = "0x384 - Peripheral Select Register"]
357 pub psr14: PSR,
358 #[doc = "0x388 - Transfer Counter Register"]
359 pub tcr14: TCR,
360 #[doc = "0x38c - Memory Address Reload Register"]
361 pub marr14: MARR,
362 #[doc = "0x390 - Transfer Counter Reload Register"]
363 pub tcrr14: TCRR,
364 #[doc = "0x394 - Control Register"]
365 pub cr14: CR,
366 #[doc = "0x398 - Mode Register"]
367 pub mr14: MR,
368 #[doc = "0x39c - Status Register"]
369 pub sr14: SR,
370 #[doc = "0x3a0 - Interrupt Enable Register"]
371 pub ier14: IER,
372 #[doc = "0x3a4 - Interrupt Disable Register"]
373 pub idr14: IDR,
374 #[doc = "0x3a8 - Interrupt Mask Register"]
375 pub imr14: IMR,
376 #[doc = "0x3ac - Interrupt Status Register"]
377 pub isr14: ISR,
378 _reserved180: [u8; 0x10],
379 #[doc = "0x3c0 - Memory Address Register"]
380 pub mar15: MAR,
381 #[doc = "0x3c4 - Peripheral Select Register"]
382 pub psr15: PSR,
383 #[doc = "0x3c8 - Transfer Counter Register"]
384 pub tcr15: TCR,
385 #[doc = "0x3cc - Memory Address Reload Register"]
386 pub marr15: MARR,
387 #[doc = "0x3d0 - Transfer Counter Reload Register"]
388 pub tcrr15: TCRR,
389 #[doc = "0x3d4 - Control Register"]
390 pub cr15: CR,
391 #[doc = "0x3d8 - Mode Register"]
392 pub mr15: MR,
393 #[doc = "0x3dc - Status Register"]
394 pub sr15: SR,
395 #[doc = "0x3e0 - Interrupt Enable Register"]
396 pub ier15: IER,
397 #[doc = "0x3e4 - Interrupt Disable Register"]
398 pub idr15: IDR,
399 #[doc = "0x3e8 - Interrupt Mask Register"]
400 pub imr15: IMR,
401 #[doc = "0x3ec - Interrupt Status Register"]
402 pub isr15: ISR,
403 _reserved192: [u8; 0x0410],
404 #[doc = "0x800 - Performance Control Register"]
405 pub pcontrol: PCONTROL,
406 #[doc = "0x804 - Channel 0 Read Data Cycles"]
407 pub prdata0: PRDATA0,
408 #[doc = "0x808 - Channel 0 Read Stall Cycles"]
409 pub prstall0: PRSTALL0,
410 #[doc = "0x80c - Channel 0 Read Max Latency"]
411 pub prlat0: PRLAT0,
412 #[doc = "0x810 - Channel 0 Write Data Cycles"]
413 pub pwdata0: PWDATA0,
414 #[doc = "0x814 - Channel 0 Write Stall Cycles"]
415 pub pwstall0: PWSTALL0,
416 #[doc = "0x818 - Channel0 Write Max Latency"]
417 pub pwlat0: PWLAT0,
418 #[doc = "0x81c - Channel 1 Read Data Cycles"]
419 pub prdata1: PRDATA1,
420 #[doc = "0x820 - Channel Read Stall Cycles"]
421 pub prstall1: PRSTALL1,
422 #[doc = "0x824 - Channel 1 Read Max Latency"]
423 pub prlat1: PRLAT1,
424 #[doc = "0x828 - Channel 1 Write Data Cycles"]
425 pub pwdata1: PWDATA1,
426 #[doc = "0x82c - Channel 1 Write stall Cycles"]
427 pub pwstall1: PWSTALL1,
428 #[doc = "0x830 - Channel 1 Read Max Latency"]
429 pub pwlat1: PWLAT1,
430 #[doc = "0x834 - Version Register"]
431 pub version: VERSION,
432}
433#[doc = "CR (w) register accessor: an alias for `Reg<CR_SPEC>`"]
434pub type CR = crate::Reg<cr::CR_SPEC>;
435#[doc = "Control Register"]
436pub mod cr;
437#[doc = "IDR (w) register accessor: an alias for `Reg<IDR_SPEC>`"]
438pub type IDR = crate::Reg<idr::IDR_SPEC>;
439#[doc = "Interrupt Disable Register"]
440pub mod idr;
441#[doc = "IER (w) register accessor: an alias for `Reg<IER_SPEC>`"]
442pub type IER = crate::Reg<ier::IER_SPEC>;
443#[doc = "Interrupt Enable Register"]
444pub mod ier;
445#[doc = "IMR (r) register accessor: an alias for `Reg<IMR_SPEC>`"]
446pub type IMR = crate::Reg<imr::IMR_SPEC>;
447#[doc = "Interrupt Mask Register"]
448pub mod imr;
449#[doc = "ISR (r) register accessor: an alias for `Reg<ISR_SPEC>`"]
450pub type ISR = crate::Reg<isr::ISR_SPEC>;
451#[doc = "Interrupt Status Register"]
452pub mod isr;
453#[doc = "MARR (rw) register accessor: an alias for `Reg<MARR_SPEC>`"]
454pub type MARR = crate::Reg<marr::MARR_SPEC>;
455#[doc = "Memory Address Reload Register"]
456pub mod marr;
457#[doc = "MAR (rw) register accessor: an alias for `Reg<MAR_SPEC>`"]
458pub type MAR = crate::Reg<mar::MAR_SPEC>;
459#[doc = "Memory Address Register"]
460pub mod mar;
461#[doc = "MR (rw) register accessor: an alias for `Reg<MR_SPEC>`"]
462pub type MR = crate::Reg<mr::MR_SPEC>;
463#[doc = "Mode Register"]
464pub mod mr;
465#[doc = "PCONTROL (rw) register accessor: an alias for `Reg<PCONTROL_SPEC>`"]
466pub type PCONTROL = crate::Reg<pcontrol::PCONTROL_SPEC>;
467#[doc = "Performance Control Register"]
468pub mod pcontrol;
469#[doc = "PRDATA0 (r) register accessor: an alias for `Reg<PRDATA0_SPEC>`"]
470pub type PRDATA0 = crate::Reg<prdata0::PRDATA0_SPEC>;
471#[doc = "Channel 0 Read Data Cycles"]
472pub mod prdata0;
473#[doc = "PRDATA1 (r) register accessor: an alias for `Reg<PRDATA1_SPEC>`"]
474pub type PRDATA1 = crate::Reg<prdata1::PRDATA1_SPEC>;
475#[doc = "Channel 1 Read Data Cycles"]
476pub mod prdata1;
477#[doc = "PRLAT0 (r) register accessor: an alias for `Reg<PRLAT0_SPEC>`"]
478pub type PRLAT0 = crate::Reg<prlat0::PRLAT0_SPEC>;
479#[doc = "Channel 0 Read Max Latency"]
480pub mod prlat0;
481#[doc = "PRLAT1 (r) register accessor: an alias for `Reg<PRLAT1_SPEC>`"]
482pub type PRLAT1 = crate::Reg<prlat1::PRLAT1_SPEC>;
483#[doc = "Channel 1 Read Max Latency"]
484pub mod prlat1;
485#[doc = "PRSTALL0 (r) register accessor: an alias for `Reg<PRSTALL0_SPEC>`"]
486pub type PRSTALL0 = crate::Reg<prstall0::PRSTALL0_SPEC>;
487#[doc = "Channel 0 Read Stall Cycles"]
488pub mod prstall0;
489#[doc = "PRSTALL1 (r) register accessor: an alias for `Reg<PRSTALL1_SPEC>`"]
490pub type PRSTALL1 = crate::Reg<prstall1::PRSTALL1_SPEC>;
491#[doc = "Channel Read Stall Cycles"]
492pub mod prstall1;
493#[doc = "PSR (rw) register accessor: an alias for `Reg<PSR_SPEC>`"]
494pub type PSR = crate::Reg<psr::PSR_SPEC>;
495#[doc = "Peripheral Select Register"]
496pub mod psr;
497#[doc = "PWDATA0 (r) register accessor: an alias for `Reg<PWDATA0_SPEC>`"]
498pub type PWDATA0 = crate::Reg<pwdata0::PWDATA0_SPEC>;
499#[doc = "Channel 0 Write Data Cycles"]
500pub mod pwdata0;
501#[doc = "PWDATA1 (r) register accessor: an alias for `Reg<PWDATA1_SPEC>`"]
502pub type PWDATA1 = crate::Reg<pwdata1::PWDATA1_SPEC>;
503#[doc = "Channel 1 Write Data Cycles"]
504pub mod pwdata1;
505#[doc = "PWLAT0 (r) register accessor: an alias for `Reg<PWLAT0_SPEC>`"]
506pub type PWLAT0 = crate::Reg<pwlat0::PWLAT0_SPEC>;
507#[doc = "Channel0 Write Max Latency"]
508pub mod pwlat0;
509#[doc = "PWLAT1 (r) register accessor: an alias for `Reg<PWLAT1_SPEC>`"]
510pub type PWLAT1 = crate::Reg<pwlat1::PWLAT1_SPEC>;
511#[doc = "Channel 1 Read Max Latency"]
512pub mod pwlat1;
513#[doc = "PWSTALL0 (r) register accessor: an alias for `Reg<PWSTALL0_SPEC>`"]
514pub type PWSTALL0 = crate::Reg<pwstall0::PWSTALL0_SPEC>;
515#[doc = "Channel 0 Write Stall Cycles"]
516pub mod pwstall0;
517#[doc = "PWSTALL1 (r) register accessor: an alias for `Reg<PWSTALL1_SPEC>`"]
518pub type PWSTALL1 = crate::Reg<pwstall1::PWSTALL1_SPEC>;
519#[doc = "Channel 1 Write stall Cycles"]
520pub mod pwstall1;
521#[doc = "SR (r) register accessor: an alias for `Reg<SR_SPEC>`"]
522pub type SR = crate::Reg<sr::SR_SPEC>;
523#[doc = "Status Register"]
524pub mod sr;
525#[doc = "TCRR (rw) register accessor: an alias for `Reg<TCRR_SPEC>`"]
526pub type TCRR = crate::Reg<tcrr::TCRR_SPEC>;
527#[doc = "Transfer Counter Reload Register"]
528pub mod tcrr;
529#[doc = "TCR (rw) register accessor: an alias for `Reg<TCR_SPEC>`"]
530pub type TCR = crate::Reg<tcr::TCR_SPEC>;
531#[doc = "Transfer Counter Register"]
532pub mod tcr;
533#[doc = "VERSION (r) register accessor: an alias for `Reg<VERSION_SPEC>`"]
534pub type VERSION = crate::Reg<version::VERSION_SPEC>;
535#[doc = "Version Register"]
536pub mod version;