atsam4ls8a_pac/iisc/
cr.rs

1#[doc = "Register `CR` writer"]
2pub struct W(crate::W<CR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<CR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<CR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<CR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Receive Enable\n\nValue on reset: 0"]
23#[derive(Clone, Copy, Debug, PartialEq, Eq)]
24pub enum RXENSELECT_AW {
25    #[doc = "0: No effect"]
26    OFF = 0,
27    #[doc = "1: Enables Data Receive if RXDIS is not set"]
28    ON = 1,
29}
30impl From<RXENSELECT_AW> for bool {
31    #[inline(always)]
32    fn from(variant: RXENSELECT_AW) -> Self {
33        variant as u8 != 0
34    }
35}
36#[doc = "Field `RXEN` writer - Receive Enable"]
37pub type RXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, RXENSELECT_AW, O>;
38impl<'a, const O: u8> RXEN_W<'a, O> {
39    #[doc = "No effect"]
40    #[inline(always)]
41    pub fn off(self) -> &'a mut W {
42        self.variant(RXENSELECT_AW::OFF)
43    }
44    #[doc = "Enables Data Receive if RXDIS is not set"]
45    #[inline(always)]
46    pub fn on(self) -> &'a mut W {
47        self.variant(RXENSELECT_AW::ON)
48    }
49}
50#[doc = "Receive Disable\n\nValue on reset: 0"]
51#[derive(Clone, Copy, Debug, PartialEq, Eq)]
52pub enum RXDISSELECT_AW {
53    #[doc = "0: No effect"]
54    OFF = 0,
55    #[doc = "1: Disables Data Receive"]
56    ON = 1,
57}
58impl From<RXDISSELECT_AW> for bool {
59    #[inline(always)]
60    fn from(variant: RXDISSELECT_AW) -> Self {
61        variant as u8 != 0
62    }
63}
64#[doc = "Field `RXDIS` writer - Receive Disable"]
65pub type RXDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, RXDISSELECT_AW, O>;
66impl<'a, const O: u8> RXDIS_W<'a, O> {
67    #[doc = "No effect"]
68    #[inline(always)]
69    pub fn off(self) -> &'a mut W {
70        self.variant(RXDISSELECT_AW::OFF)
71    }
72    #[doc = "Disables Data Receive"]
73    #[inline(always)]
74    pub fn on(self) -> &'a mut W {
75        self.variant(RXDISSELECT_AW::ON)
76    }
77}
78#[doc = "Clocks Enable\n\nValue on reset: 0"]
79#[derive(Clone, Copy, Debug, PartialEq, Eq)]
80pub enum CKENSELECT_AW {
81    #[doc = "0: No effect"]
82    OFF = 0,
83    #[doc = "1: Enables clocks if CKDIS is not set"]
84    ON = 1,
85}
86impl From<CKENSELECT_AW> for bool {
87    #[inline(always)]
88    fn from(variant: CKENSELECT_AW) -> Self {
89        variant as u8 != 0
90    }
91}
92#[doc = "Field `CKEN` writer - Clocks Enable"]
93pub type CKEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, CKENSELECT_AW, O>;
94impl<'a, const O: u8> CKEN_W<'a, O> {
95    #[doc = "No effect"]
96    #[inline(always)]
97    pub fn off(self) -> &'a mut W {
98        self.variant(CKENSELECT_AW::OFF)
99    }
100    #[doc = "Enables clocks if CKDIS is not set"]
101    #[inline(always)]
102    pub fn on(self) -> &'a mut W {
103        self.variant(CKENSELECT_AW::ON)
104    }
105}
106#[doc = "Clocks Disable\n\nValue on reset: 0"]
107#[derive(Clone, Copy, Debug, PartialEq, Eq)]
108pub enum CKDISSELECT_AW {
109    #[doc = "0: No effect"]
110    OFF = 0,
111    #[doc = "1: Disables clocks"]
112    ON = 1,
113}
114impl From<CKDISSELECT_AW> for bool {
115    #[inline(always)]
116    fn from(variant: CKDISSELECT_AW) -> Self {
117        variant as u8 != 0
118    }
119}
120#[doc = "Field `CKDIS` writer - Clocks Disable"]
121pub type CKDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, CKDISSELECT_AW, O>;
122impl<'a, const O: u8> CKDIS_W<'a, O> {
123    #[doc = "No effect"]
124    #[inline(always)]
125    pub fn off(self) -> &'a mut W {
126        self.variant(CKDISSELECT_AW::OFF)
127    }
128    #[doc = "Disables clocks"]
129    #[inline(always)]
130    pub fn on(self) -> &'a mut W {
131        self.variant(CKDISSELECT_AW::ON)
132    }
133}
134#[doc = "Transmit Enable\n\nValue on reset: 0"]
135#[derive(Clone, Copy, Debug, PartialEq, Eq)]
136pub enum TXENSELECT_AW {
137    #[doc = "0: No effect"]
138    OFF = 0,
139    #[doc = "1: Enables Data Transmit if TXDIS is not set"]
140    ON = 1,
141}
142impl From<TXENSELECT_AW> for bool {
143    #[inline(always)]
144    fn from(variant: TXENSELECT_AW) -> Self {
145        variant as u8 != 0
146    }
147}
148#[doc = "Field `TXEN` writer - Transmit Enable"]
149pub type TXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, TXENSELECT_AW, O>;
150impl<'a, const O: u8> TXEN_W<'a, O> {
151    #[doc = "No effect"]
152    #[inline(always)]
153    pub fn off(self) -> &'a mut W {
154        self.variant(TXENSELECT_AW::OFF)
155    }
156    #[doc = "Enables Data Transmit if TXDIS is not set"]
157    #[inline(always)]
158    pub fn on(self) -> &'a mut W {
159        self.variant(TXENSELECT_AW::ON)
160    }
161}
162#[doc = "Transmit Disable\n\nValue on reset: 0"]
163#[derive(Clone, Copy, Debug, PartialEq, Eq)]
164pub enum TXDISSELECT_AW {
165    #[doc = "0: No effect"]
166    OFF = 0,
167    #[doc = "1: Disables Data Transmit"]
168    ON = 1,
169}
170impl From<TXDISSELECT_AW> for bool {
171    #[inline(always)]
172    fn from(variant: TXDISSELECT_AW) -> Self {
173        variant as u8 != 0
174    }
175}
176#[doc = "Field `TXDIS` writer - Transmit Disable"]
177pub type TXDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, TXDISSELECT_AW, O>;
178impl<'a, const O: u8> TXDIS_W<'a, O> {
179    #[doc = "No effect"]
180    #[inline(always)]
181    pub fn off(self) -> &'a mut W {
182        self.variant(TXDISSELECT_AW::OFF)
183    }
184    #[doc = "Disables Data Transmit"]
185    #[inline(always)]
186    pub fn on(self) -> &'a mut W {
187        self.variant(TXDISSELECT_AW::ON)
188    }
189}
190#[doc = "Software Reset\n\nValue on reset: 0"]
191#[derive(Clone, Copy, Debug, PartialEq, Eq)]
192pub enum SWRSTSELECT_AW {
193    #[doc = "0: No effect"]
194    OFF = 0,
195    #[doc = "1: Performs a software reset. Has priority on any other bit in CR"]
196    ON = 1,
197}
198impl From<SWRSTSELECT_AW> for bool {
199    #[inline(always)]
200    fn from(variant: SWRSTSELECT_AW) -> Self {
201        variant as u8 != 0
202    }
203}
204#[doc = "Field `SWRST` writer - Software Reset"]
205pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, SWRSTSELECT_AW, O>;
206impl<'a, const O: u8> SWRST_W<'a, O> {
207    #[doc = "No effect"]
208    #[inline(always)]
209    pub fn off(self) -> &'a mut W {
210        self.variant(SWRSTSELECT_AW::OFF)
211    }
212    #[doc = "Performs a software reset. Has priority on any other bit in CR"]
213    #[inline(always)]
214    pub fn on(self) -> &'a mut W {
215        self.variant(SWRSTSELECT_AW::ON)
216    }
217}
218impl W {
219    #[doc = "Bit 0 - Receive Enable"]
220    #[inline(always)]
221    #[must_use]
222    pub fn rxen(&mut self) -> RXEN_W<0> {
223        RXEN_W::new(self)
224    }
225    #[doc = "Bit 1 - Receive Disable"]
226    #[inline(always)]
227    #[must_use]
228    pub fn rxdis(&mut self) -> RXDIS_W<1> {
229        RXDIS_W::new(self)
230    }
231    #[doc = "Bit 2 - Clocks Enable"]
232    #[inline(always)]
233    #[must_use]
234    pub fn cken(&mut self) -> CKEN_W<2> {
235        CKEN_W::new(self)
236    }
237    #[doc = "Bit 3 - Clocks Disable"]
238    #[inline(always)]
239    #[must_use]
240    pub fn ckdis(&mut self) -> CKDIS_W<3> {
241        CKDIS_W::new(self)
242    }
243    #[doc = "Bit 4 - Transmit Enable"]
244    #[inline(always)]
245    #[must_use]
246    pub fn txen(&mut self) -> TXEN_W<4> {
247        TXEN_W::new(self)
248    }
249    #[doc = "Bit 5 - Transmit Disable"]
250    #[inline(always)]
251    #[must_use]
252    pub fn txdis(&mut self) -> TXDIS_W<5> {
253        TXDIS_W::new(self)
254    }
255    #[doc = "Bit 7 - Software Reset"]
256    #[inline(always)]
257    #[must_use]
258    pub fn swrst(&mut self) -> SWRST_W<7> {
259        SWRST_W::new(self)
260    }
261    #[doc = "Writes raw bits to the register."]
262    #[inline(always)]
263    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
264        self.0.bits(bits);
265        self
266    }
267}
268#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"]
269pub struct CR_SPEC;
270impl crate::RegisterSpec for CR_SPEC {
271    type Ux = u32;
272}
273#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"]
274impl crate::Writable for CR_SPEC {
275    type Writer = W;
276    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
277    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
278}
279#[doc = "`reset()` method sets CR to value 0"]
280impl crate::Resettable for CR_SPEC {
281    const RESET_VALUE: Self::Ux = 0;
282}
atsam4ls8a_pac/iisc/cr.rs

atsam4ls8a_pac/iisc/
cr.rs
